MC14069UB Datasheet by ON Semiconductor

0N Sem manductur® [ 0 ] [ ] [ ] E ] [ ] E ] II II 14 “ﬁnnnnnn rlrlrlrlrlrlrl Nole 1 1 ) D 0 TA Amoienl Temperalure Range ,55 lo +125 “C 1 H H H H H H H u u u u u u 1.1 1:19 Slorage Temperalure Range 765 lo +150 “C TL Lead Temperalu re 260 “C lBeSecond Soldering) 4H n n H H RH Siresses exceeding lhose lisled in me Maximum Ralrngs laole may damage lrre device. ll any or lhese limils are exceeded, device lunclicnahly should rial be va assumed, damage may occur and rehabilily may be allecled, 1. Temperalure Deraling. “D/DW” Package-5,771] mW/“C From 55%: To125°c if“ H EH HH This device cpnlains proleclion circuilry lo guard againsl damage due in high slalic vollages or eleclno lields. However, precaulipns musl be laken la avoid apphoalrons or any vollage higher irran maximum raled vollages lo lrus higheimpedance circuil. For proper operalron, VW and van. should be oonslrained lo lhe range 1/55 s (V,,. or vamp s VDD. Unused inpuls musl always he lied in an appmpvlale logic vollage level (9.9., eilher v55 or VDD) Unused culpuls musl be lell open, See dime m Semiconducluv Campcnenls lnﬂuslrles. up 2014 August, 2014 — Rev. 11

August, 2014 − Rev. 11 1Publication Order Number:

MC14069UB/D

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P−channel

and N−channel enhancement mode devices in a single monolithic

structure. These inverters find primary use where low power

dissipation and/or high noise immunity is desired. Each of the six

inverters is a single stage to minimize propagation delays.

Features

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

•Triple Diode Protection on All Inputs

•Pin−for−Pin Replacement for CD4069UB

•Meets JEDEC UB Specifications

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient) −0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1) 500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering) 260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

MARKING DIAGRAMS

SOIC−14

TSSOP−14

14069UG

AWLYWW

069U

ALYWG

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

SOEIAJ−14

MC14069UB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

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(Note: Microdot may be in either location)

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

105

OUT 5

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

VSS

OUT 3

IN 3

PIN ASSIGNMENT

e_ : _e K Mg KKK 1%

MC14069UB

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Figure 1. Logic Diagram Figure 2. Circuit Schematic

VDD = PIN 14

VSS = PIN 7

VDD

VSS

OUTPUT

INPUT*

*Double diode protection on all inputs not shown

Figure 3. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VDD

VSS

INPUT

OUTPUT

20 ns 20 ns

VDD

VSS

VOH

VOL

tTHL tTLH

OUTPUT

INPUT

tPHL tPLH

90%

50%

10%

90%

50%

10%

(1/6 of circuit shown)

ORDERING INFORMATION

Device Package Shipping†

MC14069UBDG SOIC−14

(Pb−Free) 55 Units / Rail

NLV14069UBDG* SOIC−14

(Pb−Free) 55 Units / Rail

MC14069UBDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

NLV14069UBDR2G* SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC14069UBDTR2G TSSOP−14

(Pb−Free) 2500 Units / Tape & Reel

NLV14069UBDTR2G* TSSOP−14

(Pb−Free) 2500 Units / Tape & Reel

MC14069UBFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

MC14069UB

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbo

VDD

Vdc

−55_C 25_C 125_C

Unit

Min Max Min

Typ

(Note 2) Max Min Max

Output Voltage “0” Leve

Vin = VDD

Vin = 0 “1” Leve

VOL 5.0

−

0.05

−

0.05

−

0.05

Vdc

VOH 5.0

4.95

9.95

14.95

−

4.95

9.95

14.95

5.0

−

4.95

9.95

14.95

−

Vdc

Input Voltage “0” Leve

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

“1” Leve

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

VIL 5.0

−

1.0

2.0

2.5

−

2.25

4.50

6.75

1.0

2.0

2.5

−

1.0

2.0

2.5

Vdc

VIH 5.0

4.0

8.0

12.5

−

4.0

8.0

12.5

2.75

5.50

8.25

−

4.0

8.0

12.5

−

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sin

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOH 5.0

5.0

–3.0

–0.64

–1.6

–4.2

−

–2.4

–0.51

–1.3

–3.4

–4.2

–0.88

–2.25

–8.8

−

–1.7

–0.36

–0.9

–2.4

−

mAdc

IOL 5.0

0.64

1.6

4.2

−

0.51

1.3

3.4

0.88

2.25

8.8

−

0.36

0.9

2.4

−

mAdc

Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc

Input Capacitance

(Vin = 0)

Cin − − − − 5.0 7.5 − − pF

Quiescent Current

(Per Package)

IDD 5.0

−

0.25

0.5

1.0

−

0.0005

0.0010

0.0015

0.25

0.5

1.0

−

7.5

mAdc

Total Supply Current (Notes 3 and 4)

(Dynamic plus Quiescent,

Per Gate) (CL = 50 pF)

IT5.0

IT = (0.3 mA/kHz) f + IDD/6

IT = (0.6 mA/kHz) f + IDD/6

IT = (0.9 mA/kHz) f + IDD/6

mAdc

Output Rise and Fall Times (Note 3)

(CL = 50 pF)

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

tTLH,

tTHL 5.0

−

100

200

100

−

Propagation Delay Times (Note 3)

(CL = 50 pF)

tPLH, tPHL = (0.90 ns/pF) CL + 20 ns

tPLH, tPHL = (0.36 ns/pF) CL + 22 ns

tPLH, tPHL = (0.26 ns/pF) CL + 17 ns

tPLH,

tPHL 5.0

−

125

−

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

l-IEE Wﬁi L % HZ TIE % t |:l ‘ |:| |:l ‘ |:| |:| ‘ |:| IE! 7 + , EFL |:| ‘ at TI:I ‘ |:| |:| ‘ |:|

MC14069UB

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PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

14 8

0.25 B M

X 45

SEATING

PLANE

0.25 B S

13X

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

|:| |:|* a L,,,,,,E , $ \‘0 L Qumowsﬂu® HHHHHHH 41 r; E mef T37 i L ED F-uwmom I T 0 ‘JG L 4" DETAILE/ B: |:| ‘ |:| |:| |:| ‘ |:| E7 742% :I :I I L: ‘ E ‘ ET T: hllp://onsemi.com 5

MC14069UB

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PACKAGE DIMENSIONS

TSSOP−14

CASE 948G

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

SECTION N−N

DETAIL E

JJ1

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

mmmmmmm 7, 6) EMF

MC14069UB

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PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965

ISSUE B

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

14 8

VIEW P

DETAIL P

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MC14069UB/D

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