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MC33172 MC35172
Low power dual bipolar operational amplifiers
Features
■Good consumption/speed ratio: only 200 µA for
2.1MHz, 2V/µs
■Single (or dual) supply operation from +4 V to
+44V (±2V to ±22V)
■Wide input common mode mode voltage range
including VCC-
■Low level output voltage close to VCC- :
100 mV typical
■Pin-to-pin compatible with standard dual
operational amplifiers
Description
The MC3x172 series are dual bipolar operational
amplifiers offering both low consumption
(200 µA/Amp) and good speed (2.1 MHz, 2 V/µs).
Moreover, the input common mode range extends
down to the lower supply rail, allowing single
supply operation from +4 V to +44 V.
N
DIP8
(Plastic package)
D
SO-8
(Plastic micropackage)
1
2
3
45
6
7
8
-
+-
+
Ouptut
Inverting Input 2
Non-inverting Input 2
Inverting Input 1
Output 1
Non-inverting Input 1
VCC
V
CC
Pin connections
(top view)
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Circuit schematics MC33172 MC35172
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1 Circuit schematics
Figure 1. Typical schematic diagram (1/2 MC33172/MC35172)
V +
CC
T1
T7
R4
T8 T9
R3
T6
T2
T5
T3
R1
T4
R2
T13
T14
T19
R5
R7 R8
T10 T11
R6
T15 T16
R9
T20
R10
T17
Input +
T12 T13
T24
C
T21
T22
R11
T23
T27
T29
R12
R15 T30 T31
T28
R14
Output
R13
V -
CC
Input -
T25
T26
MC33172 MC35172 Absolute maximum ratings and operating conditions
3/9
2 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage ±22 V
Vid Differential input voltage see note (1)
1. Either or both input voltages must not exceed the magnitude of VCC.
V
Vin Input voltage see note 1 V
Output short-circuit duration Indefinite s
Toper
Operating free-air temperature range
MC33172
MC35172
-40 to 105
-55 to 125
°C
Rthja
Thermal resistance junction to ambient(2)
SO-8
DIP8
2. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
125
85
°C/W
Rthjc
Thermal resistance junction to case(2)
SO-8
DIP8
40
41
°C/W
TjJunction temperature 150 °C
Tstg Storage temperature -65 to 150 °C
ESD
HBM: human body model(3)
3. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
2kV
MM: machine model(4)
4. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
connected pin combinations while the other pins are floating.
200 V
CDM: charged device model(5)
5. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
1kV
Latch-up immunity Class A
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage ±2 to ±22 V
1H1
Electrical characteristics MC33172 MC35172
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3 Electrical characteristics
Table 3. VCC+ = +15V, VCC- = -15V, RL connected to Ground, Tamb = 25°C (unless otherwise
specified)
Symbol Parameter Min. Typ. Max. Unit
Vio
Input offset voltage
VCC+ = +15V, VCC- = -15V, Vic = 0V
VCC+ = 5V, VCC- = 0V, Vic = 0V, Vo = 1.4V
VCC+ = +15V, VCC- = -15V, Vic = 0V, Tmin ≤ T
amb ≤ T
max
1
1
4.5
5
6.5
mV
DVio Input offset voltage drift 10 µV/°C
Iio
Input offset current (Vic = 0V)
Tmin ≤ T
amb ≤ T
max
520
40 nA
Iib
Input bias current (Vic = 0V)
Tmin ≤ T
amb ≤ T
max
20 100
200 nA
Avd
Large signal voltage gain (RL = 10kΩ, Vo = ±10V)
Tmin ≤ T
amb ≤ T
max
50
25
100 V/mV
VOH
High level output voltage
VCC+= 5V, VCC-= 0V, RL = 10kΩ
VCC+= +15V, VCC = -15V, RL= 10kΩ
VCC+= +15V, VCC-= -15V, RL= 10kΩ, Tmin ≤ T
amb ≤ T
max
3.5
13.6
13.3
4.2
14.2 V
VOL
Low level output voltage
VCC+= 5V, VCC-= 0V, RL= 10kΩ
VCC+= +15V, VCC-= -15V, RL= 10kΩ
VCC+= +15V, VCC-= -15V, RL= 10kΩ, Tmin ≤ T
amb ≤ T
max
0.1
-14
0.15
-13.6
-13.3
V
Isc
Output short-circuit current (Vid = ±1V, Vo = 0V)
Source
Sink
3
15
6
27
mA
Vicm
Input common mode voltage range
Tmin ≤ T
amb ≤ T
max
VCC- to VCC+ - 1.8)
VCC- to (VCC+ - 2.2) V
CMR Common-mode rejection ratio (Vic = Vicm-min) 80 100 dB
SVR Supply voltage rejection ratio (VCC = ±5 to ±15V) 80 100 dB
ICC
Supply current
VCC+ = 5V, VCC- = 0V, no load
VCC+ = +15V, VCC- = -15V, no load
VCC+ = +15V, VCC- = -15V no load, Tmin ≤ T
amb ≤ T
max
200
220
250
250
300
µA
SR Slew rate (Vin = ±10V, RL = 10kΩ, CL = 100pF) 1.6 2 V/µs
GBP Gain bandwidth product
RL = 10kΩ, CL = 100pF, F= 100kHz 1.4 2.1 MHz
φm Phase margin (RL = 10kΩ, CL = 100pF) 45 Degrees
enEquivalent input noise voltage (F = 1kHz) 29
THD Total harmonic distortion 0.05 %
VO1/VO2 Channel separation 120 dB
nV
Hz
------------
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MC33172 MC35172 Package information
5/9
4 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK® packages. These packages have a lead-free second level interconnect. The
category of second level interconnect is marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com.
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EEO ENV: BONE
Package information MC33172 MC35172
6/9
4.1 DIP8 package information
Figure 2. DIP8 package mechanical drawing
Table 4. DIP8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A5.330.210
A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b 0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D 9.02 9.27 10.16 0.355 0.365 0.400
E 7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280
e 2.54 0.100
eA 7.62 0.300
eB 10.92 0.430
L 2.92 3.30 3.81 0.115 0.130 0.150
MC33172 MC35172 Package information
7/9
4.2 SO-8 package information
Figure 3. SO-8 package mechanical drawing
Table 5. SO-8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k1° 8°1° 8°
ccc 0.10 0.004
Ordering information MC33172 MC35172
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5 Ordering information
6 Revision history
Table 6. Order codes
Order code Temperature
range Package Packing Marking
MC33172N
-40°C, +105°C
DIP8 Tape MC33172N
MC33172D
MC33172DT SO-8 Ta p e or
Tape & reel 33172
MC35172N
-55°C, +125°C
DIP8 Tape MC35172N
MC35172D
MC35172DT SO-8 Ta p e or
Tape & reel 35172
Table 7. Document revision history
Date Revision Changes
24-Nov-2001 1 Initial release.
01-Jul-2008 2 ESD values and latch-up immunity added in Table 1: Absolute
maximum ratings (AMR).
MC33172 MC35172
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