SI2337DS Datasheet by Vishay Siliconix

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Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 1Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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P-Channel 80 V (D-S) MOSFET
Marking code: E7
FEATURES
• TrenchFET® power MOSFET
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
Notes
a. Package limited
b. Surface mounted on 1" x 1" FR4 board
c. t = 10 s
d. Maximum under steady state conditions is 166 °C/W
PRODUCT SUMMARY
VDS (V) -80
RDS(on) max. () at VGS = -10 V 0.270
RDS(on) max. () at VGS = -6 V 0.303
Qg typ. (nC) 7
ID (A) a-2.2
Configuration Single
Top View
SOT-23 (TO-236)
1
G
2
S
D
3
Available
S
G
D
P-Channel MOSFET
ORDERING INFORMATION
Package SOT-23
Lead (Pb)-free Si2337DS-T1-E3
Lead (Pb)-free and halogen-free Si2337DS-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS -80 V
Gate-source voltage VGS ± 20
Continuous drain current (TJ = 150 °C)
TC = 25 °C
ID
-2.2
A
TC = 70 °C -1.75
TA = 25 °C -1.2 b, c
TA = 70 °C -0.96 b, c
Pulsed drain current IDM -7
Continuous source-drain diode current TC = 25 °C IS
-2.1
TA = 25 °C -0.63 b, c
Avalanche current L = 0.1 mH IAS 11
Single-pulse avalanche energy EAS 6mJ
Maximum power dissipation
TC = 25 °C
PD
2.5
W
TC = 70 °C 1.6
TA = 25 °C 0.76 b, c
TA = 70 °C 0.48 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
Soldering recommendations (peak temperature) d, e 260
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient b, d t 10 s RthJA 120 166 °C/W
Maximum junction-to-foot (drain) Steady state RthJF 40 50
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Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 2Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = -250 μA -80 - - V
VDS temperature coefficient VDS/TJID = -250 μA - -35.8 - mV/°C
VGS(th) temperature coefficient VGS(th)/TJ-5.45-
Gate-source threshold voltage VGS(th) VDS = VGS, ID = -250 μA -2 - -4 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
Zero gate voltage drain current IDSS
VDS = -80 V, VGS = 0 V ---1
μA
VDS = -80 V, VGS = 0 V, TJ = 55 °C ---10
On-state drain current aID(on) VDS 5 V, VGS = -10 V -7 - - A
Drain-source on-state resistance a RDS(on)
VGS = -10 V, ID = -1.2 A - 0.216 0.270
VGS = -6 V, ID = -1.1 A - 0.242 0.303
Forward transconductance a gfs VDS = -15 V, ID = -1.2 A -4.3- S
Dynamic b
Input capacitance Ciss
VDS = -40 V, VGS = 0 V, f = 1 MHz
-500-
pFOutput capacitance Coss -40-
Reverse transfer capacitance Crss -25-
Total gate charge Qg
VDS = -40 V, VGS = -10 V, ID = -1.2 A -1117
nC
VDS = -40 V, VGS = -6 V, ID = -1.2 A
-711
Gate-source charge Qgs -2.1-
Gate-drain charge Qgd -3.2-
Gate resistance Rgf = 1 MHz - 4.8 -
Turn-on delay time td(on)
VDD = -40 V, RL = 42
ID -0.96 A, VGEN = -10 V, Rg = 1
-1015
ns
Rise time tr-1523
Turn-off delay time td(off) -2030
Fall time tf-1523
Turn-on delay time td(on)
VDD = -40 V, RL = 42
ID -0.96 A, VGEN = -6 V, Rg = 1
-1523
Rise time tr-1827
Turn-off delay time td(off) -2030
Fall time tf-1218
Drain-Source Body Diode Characteristics
Continuous source-drain diode current ISTC = 25 °C ---2.1
A
Pulse diode forward current aISM ---7
Body diode voltage VSD IS = 0.63 A - -0.8 -1.2 V
Body diode reverse recovery time trr
IF = 0.63 A, di/dt = 100 A/μs,
TJ = 25 °C
-3045ns
Body diode reverse recovery charge Qrr -4570nC
Reverse recovery fall time ta-25-ns
Reverse recovery rise time tb-5-
— VISHAY. V mas TA=25“ "c \/~/; \ \ \\ fi \ pmosmcnsuggomiwshaymm www.v\shay,com/doc?91000
Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 3Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
1
2
3
4
5
6
7
01234
V
GS
= 10 thru 6 V
V
GS
= 4 V
V
DS
- Drain-to-Source Voltage (V)
)A( tnerruC niarD -I
D
V
GS
= 5 V
0.10
0.15
0.20
0.25
0.30
01234567
V
GS = 10 V
ID - Drain Current (A)
VGS = 6 V
R)no(SD () ecnatsis
e
R-nO -
0
2
4
6
8
10
024681012
I
D
= 1.2 A
)
V
(
eg
a
t
lo
V
ec
r
u
o
S
-
ot
-
e
t
aG
-
Q
g
- Total Gate Charge (nC)
V
SG
V
DS
= 64 V
V
DS
= 40 V
0
1
2
3
4
5
6
7
0.0 1.0 2.0 3.0 4.0 5.0
V
GS
- Gate-to-Source Voltage (V)
)A( tnerruC niarD -I
D
T
A
= 25 °C
T
A
= - 55 °C
T
A
= 125 °C
0
100
200
300
400
500
600
700
0 1020304050607080
C
oss
Ciss
VDS - Drain-to-Source Voltage (V)
)Fp( ec
na
t
i
c
apaC
-
C
Crss
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
TJ- Junction Temperature (°C)
R)
n
o
(
SD e
cn
a
t
si
s
eR
-
n
O - )
d
ezi
l
amro
N
(
ID = 1.2 A
VGS = 6 V
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Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 4Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
Safe Operating Area, Junction-to-Ambient
1.0 1.20.0 0.2 0.4 0.6 0.8
T
J
= 25 °C
T
J
= 150 °C
V
SD
- Source-to-Drain Voltage (V)
)A( tnerruC ecruoS -I
S
0.1
1
10
20
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
- 50 - 25 0 25 50 75 100 125 150
I
D
= 250 µA
T
J
- Temperature (°C)
V
)
h
t(
S
G
)
V(
0.1
0.2
0.3
0.4
0.5
0.6
34567
VGS - Gate-to-Source Voltage (V)
R)no(SD () ecnatsiseR-nO ecruoS-ot-niarD -
TA= 25 °C
TA = 125 °C
ID = 1.2 A
0
2
4
6
8
10
12
14
16
)W(
rewoP
Time (s)
0.01 0.1 1 10 100 1000
0.001
0.01
0.1
1
10
100
1000
0.1 1 10 100 1000
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
T
A
= 25 °C
Single Pulse
1 ms
10 ms
100 ms
DC
1 s
10 s
Limited by R
DS(on)
*I
DM
Limited
I
D(on)
Limited
BVDSS Limited
VISHAY. 5n pmosmcnsuggomiwshaymm www.v\shay,com/doc?91000
Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 5Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating aPower Derating
Single Pulse Avalanche Capability
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
0 25 50 75 100 125 150
ID)A( tnerruC niarD -
TC - Case Temperature (°C)
0.0
0.5
1.0
1.5
2.0
2.5
25 50 75 100 125 150
TC
- Case Temperature (°C)
r (W)ewoP
1
10
T
A
- Time In Avalanche (s)
I
C
)A(
t
n
err
uC
e
h
cn
al
a
v
A
ka
eP
-
T
A
L I
A
BV V
DD
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3
-
VISHAY. wwwwshayfium/ggg973533 pmosmcnsuggomiwshamam www.v\shay,com/doc?91000
Si2337DS
www.vishay.com Vishay Siliconix
S19-0386-Rev. F, 20-May-2019 6Document Number: 73533
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73533.
10-3 10-2 110-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
tneisnarT ev
i
tceffE de
z
ilamroN
ecnadepmI
la
mre
hT
— VISHAYm V
Vishay Siliconix
Package Information
Document Number: 71196
09-Jul-01
www.vishay.com
1
SOT-23 (TO-236): 3-LEAD
b
E
E1
1
3
2
Se
e1
D
A2
A
A1C
Seating Plane
0.10 mm
0.004"
CC
L1
L
q
Gauge Plane
Seating Plane
0.25 mm
Dim MILLIMETERS INCHES
Min Max Min Max
A0.89 1.12 0.035 0.044
A10.01 0.10 0.0004 0.004
A20.88 1.02 0.0346 0.040
b0.35 0.50 0.014 0.020
c0.085 0.18 0.0030.007
D2.80 3.04 0.110 0.120
E2.10 2.64 0.0830.104
E11.20 1.40 0.047 0.055
e0.95 BSC 0.0374 Ref
e11.90 BSC 0.0748 Ref
L0.40 0.60 0.016 0.024
L10.64 Ref 0.025 Ref
S0.50 Ref 0.020 Ref
q3°8°3°8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
VISHAY ‘5 H u 0394 o 037 ‘ u ass
AN807
Vishay Siliconix
Document Number: 70739
26-Nov-03
www.vishay.com
1
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
ambient air. This pattern uses all the available area underneath the
body for this purpose.
FIGURE 1. Footprint With Copper Spreading
0.114
2.9
0.059
1.5
0.0394
1.0
0.037
0.95
0.150
3.8
0.081
2.05
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
— VISHAY.. mos (2 692) Recammended Mlmmum Pads Dimensmns m \nchesr‘(mm} D, Rex men Number 72609 on 2er ca
Application Note 826
Vishay Siliconix
Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SOT-23
0.106
(2.692)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.022
(0.559)
0.049
(1.245)
0.029
(0.724)
0.037
(0.950)
0.053
(1.341)
0.097
(2.459)
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Revision: 01-Jan-2019 1Document Number: 91000
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