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RENESAS Half-Bridge Drivers with Adjustable Dead 'I'Ime FN 7670 RENESAS
FN7668 Rev 0.00 Page 1 of 16
December 23, 2011
FN7668
Rev 0.00
December 23, 2011
HIP2120, HIP2121
100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time
Control and PWM Input
DATASHEET
The HIP2120 and HIP2121 are 100V, high frequency, half-bridge
MOSFET driver ICs. They are based on the popular ISL2100A and
ISL2101A half-bridge drivers.
These drivers have a programmable dead-time to insure
break-before-make operation between the high-side and low-side
drivers. The dead-time is adjustable up to 250ns.
A single PWM logic input controls both bridge outputs (HO, LO). An
enable pin (EN), when low, drives both outputs to a low state. All
logic inputs are VDD tolerant and the HIP2120 has CMOS inputs
with hysteresis for superior operation in noisy environments.
The HIP2120 has hysteretic inputs with thresholds that are
proportional to VDD. The HIP2121 has 3.3V logic/TTL compatible
inputs.
Two package options are provided. The 10 Ld 4x4 DFN package
has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
Features
• 9 Ld TDFN “B” Package Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
• Break-Before-Make Dead-Time Prevents Shoot-through and
is adjustable up to 220ns
• Bootstrap Supply Max Voltage to 114VDC
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
• CMOS Compatible Input Thresholds with Hysteresis
(HIP2120)
•1.6/1 Typical Output Pull-up/Pull-down Resistance
•On-Chip 1 Bootstrap Diode
Applications
• Telecom Half-Bridge DC/DC Converters
•UPS and Inverters
•Motor Drives
• Class-D Amplifiers
• Forward Converter with Active Clamp
Related Literature
•FN7670 “HIP2122, HIP2123 100V, 2A Peak, High
Frequency Half-Bridge Driver with Delay Timers”
FIGURE 1. TYPICAL APPLICATION FIGURE 2. DEAD-TIME vs TIMING RESISTOR
VDD HB
HO
HS
LOVSS
PWM
EN
100V max
RDT
FEEDBACK
WITH
ISOLATION
PWM
CONTROLLER
SECONDARY
CIRCUITS
HIP2120/21
EPAD
HALF BRIDGE
RDT (k)
8162432485640 64 80
DEAD-TIME (ns)
200
160
140
120
100
80
60
40
20
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 2 of 16
December 23, 2011
Block Diagram
Pin Configurations
HIP2120, HIP2121
(10 LD 4X4 TDFN)
TOP VIEW
HIP2120, HIP2121
(9 LD 4X4 TDFN)
TOP VIEW
LEVEL
SHIFT
UNDER
VOLTAGE
UNDER
VOLTAGE
EPAD
DELAY
HIP2120,
HIP2121
HIP2121
HIP2121
HIP2120/21
HIP2120/21
Optional
inversion
for future
part
numbers
VDD
PWM
RDT
EN
HB
HO
HS
LO
VSS
DELAY
EPAD IS
ELECTRICALLY
ISOLATED
EPAD
1
2
3
4
5
10
9
8
7
6
VDD
HB
HO
HS
NC
LO
VSS
PWM
EN
RDT
EPAD
1
3
4
5
10
9
8
7
6
VDD
HB
HO
HS
LO
VSS
PWM
EN
RDT
13347 HIP2120 H|P2121 RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 3 of 16
December 23, 2011
Pin Descriptions
10 LD 9 LD SYMBOL DESCRIPTION
1 1 VDD Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to
VSS.
2 3 HB High-side bootstrap supply voltage referenced to HS. Connect the positive side of the
bootstrap capacitor to this pin. Bootstrap diode is on-chip.
3 4 HO High-side output. Connect to gate of high-side power MOSFET.
4 5 HS High-side source connection. Connect to source of high-side power MOSFET. Connect
negative side of bootstrap capacitor to this pin.
8 8 PWM PWM input. For PWM = 1, HO = 1 and LO = 0. For PWM = 0, HO = 0 and LO = 1.
7 7 EN Output enable, when low, HO = LO = 0
9 9 VSS Negative voltage supply, which will generally be ground.
10 10 LO Low-side output. Connect to gate of low-side power MOSFET.
5 - NC No Connect. This pin is isolated from all other pins.
6 6 RDT A resistor connected between this pin and VSS adds additional delay time to the falling and
rising edges of the PWM input.
- - EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other
pins.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING INPUT
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
HIP2120FRTAZ HIP 2120AZ CMOS -40 +125 10 Ld 4x4 TDFN L10.4x4
HIP2121FRTAZ HIP 2121AZ 3.3V/TTL -40 +125 10 Ld 4x4 TDFN L10.4x4
HIP2120FRTBZ (Note 3) HIP 2120BZ CMOS -40 +125 9 Ld 4x4 TDFN L9.4x4
HIP2121FRTBZ (Note 3) HIP 2121BZ 3.3V/TTL -40 +125 9 Ld 4x4 TDFN L9.4x4
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2120, HIP2121. For more information on MSL please see tech brief
TB363.
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 4 of 16
December 23, 2011
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L9.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L10.4x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
mt: www.mlevs mm hhee Ph-FveeReflaw.as T3379 RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 5 of 16
December 23, 2011
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD, VHB - VHS (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V
PWM and EN Input Voltage (Note 6) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Maximum Recommended Operating
Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . 42 4
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . 42 4
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The HIP2120 and HIP2121 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to VSS unless otherwise specified.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETERS SYMBOL TEST CONDITIONS
TA = +25°C TA = -40°C to +125°C
UNITSMIN TYP MAX MIN (Note 9) MAX (Note 9)
SUPPLY CURRENTS
VDD Quiescent Current
IDD80 RDT = 80k - 470 850 - 900 µA
IDD8k RDT = 8k - 1.0 2.1 - 2.2 mA
VDD Operating Current
IDDO80k f = 500kHz, RDT = 80k - 2.5 3 - 3mA
IDDO8k f = 500kHz, RDT = 8k - 3.4 4 - 4mA
Total HB Quiescent Current IHB LI = HI = 0V - 65 115 - 150 µA
Total HB Operating Current IHBO f = 500kHz - 2.0 2.5 - 3mA
HB to VSS Current, Quiescent IHBS LI = HI = 0V; VHB = VHS = 114V - 0.05 1.5 - 10 µA
HB to VSS Current, Operating IHBSO f = 500kHz; VHB = VHS = 114V - 1.2 1.5 - 1.6 mA
INPUT PINS
Low Level Input Voltage
Threshold
VIL HIP2120 (CMOS) 3.7 4.4 - 2.7 - V
Low Level Input Voltage
Threshold
VIL HIP2121 (3.3V/TTL) 1.4 1.8 - 1.2 -V
High Level Input Voltage
Threshold
VIH HIP2120 (CMOS) - 6.54 7.93 5.3 8.2 V
High Level Input Voltage
Threshold
VIH HIP2121 ((3.3V/TTL) - 1.8 2.2 -2.4V
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 6 of 16
December 23, 2011
Input Voltage Hysteresis VIHYS HIP2120 (CMOS) - 2.2 - --V
Input Pull-down Resistance RI-210- 100 500 k
UNDERVOLTAGE PROTECTION
VDD Rising Threshold VDDR 6.8 7.3 7.8 6.5 8.1 V
VDD Threshold Hysteresis VDDH -0.6- --V
HB Rising Threshold VHBR 6.2 6.9 7.5 5.9 7.8 V
HB Threshold Hysteresis VHBH -0.6- --V
BOOTSTRAP DIODE
Low Current Forward Voltage VDL IVDD-HB = 100mA - 0.6 0.7 -0.8V
High Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.9 -1V
Dynamic Resistance RDIVDD-HB = 100mA - 0.8 1 -1.5
LO GATE DRIVER
Low Level Output Voltage VOLL ILO = 100mA - 0.25 0.4 -0.5V
High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD - VLO - 0.25 0.4 -0.5V
Peak Pull-Up Current IOHL VLO = 0V - 2 - --A
Peak Pull-Down Current IOLL VLO = 12V - 2 - --A
HO GATE DRIVER
Low Level Output Voltage VOLH IHO = 100mA - 0.25 0.4 -0.5V
High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB - VHO - 0.25 0.4 -0.5V
Peak Pull-Up Current IOHH VHO = 0V - 2 - --A
Peak Pull-Down Current IOLH VHO = 12V - 2 - --A
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
TA = +25°C TA = -40°C to +125°C
UNITSMIN TYP MAX MIN (Note 9) MAX (Note 9)
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0k, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C.
PARAMETERS SYMBOL
TEST
CONDITIONS
TJ = +25°C TJ = -40°C to +125°C
UNITSMIN TYPE MAX
MIN
(Note 9)
MAX
(Note 9)
HO Turn-Off Propagation Delay
PWM Falling to HO Falling tPLHO -3250 - 60 ns
LO Turn-Off Propagation Delay
PWM Rising to LO Falling tPLLO -3250 - 60 ns
Minimum Dead-Time Delay (see Note 10)
HO Falling to LO Rising tDTHLmin
RDT = 80k,
PWM 1 to 0 15 35 50 10 60 ns
Minimum Dead-Time Delay (see Note 10)
LO Falling to HO Rising tDTLHmin
RDT = 80k
PWM 0 to 1 15 25 50 10 60 ns
Maximum Dead-Time Delay (see Note 10)
HO Falling to LO Rising tDTHLmax
RDT = 8k,
PWM 1 to 0 150 220 300 --ns
Maximum Dead-Time Delay (see Note 10)
LO Falling to HO Rising tDTLHmax
RDT = 8k,
PWM 0 to 1 150 220 300 --ns
Either Output Rise/Fall Time
(10% to 90%/90% to 10%) tRC,tFC CL = 1nF - 10 - - - ns
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 7 of 16
December 23, 2011
Timing Diagram
Either Output Rise/Fall Time
(3V to 9V/9V to 3V) tR,tFCL = 0.1mF - 0.5 0.6 - 0.8 µs
Bootstrap Diode Turn-On or Turn-Off Time tBS -10- - - ns
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising.
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0k, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL
TEST
CONDITIONS
TJ = +25°C TJ = -40°C to +125°C
UNITSMIN TYPE MAX
MIN
(Note 9)
MAX
(Note 9)
PWM
HO
LO
EN
tPLHO tPLLO
tDTLH
tDTHL
tR
90%
10%
tF
90%
10%
\\ RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 8 of 16
December 23, 2011
Typical Performance Curves
FIGURE 3. HIP2120 IDD OPERATING CURRENT vs FREQUENCY FIGURE 4. HIP2121 IDD OPERATING CURRENT vs FREQUENCY
FIGURE 5. IHB OPERATING CURRENT vs FREQUENCY FIGURE 6. IHBS OPERATING CURRENT vs FREQUENCY
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 9 of 16
December 23, 2011
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FIGURE 11. HIP2120 PROPAGATION DELAYS vs TEMPERATURE FIGURE 12. HIP2121 PROPAGATION DELAYS vs TEMPERATURE
FIGURE 13. HIP2120 DELAY MATCHING vs TEMPERATURE FIGURE 14. HIP2121 DELAY MATCHING vs TEMPERATURE
Typical Performance Curves (Continued)
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 10 of 16
December 23, 2011
FIGURE 15. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 16. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
FIGURE 17. HIP2120 QUIESCENT CURRENT vs VOLTAGE FIGURE 18. HIP2121 QUIESCENT CURRENT vs VOLTAGE
FIGURE 19. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 20. VHS VOLTAGE vs VDD VOLTAGE
Typical Performance Curves (Continued)
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 11 of 16
December 23, 2011
Functional Description
Functional Overview
When connected to a half bridge, the output of the bridge on the
HS node follows the PWM input. In other words, when the PWM
input is high, the high-side bridge FET is turned on and the
low-side FET is off. When the PWM input is low, the low-side
bridge FET is turned on and the high-side is turned off. The
enable pin (EN), when low, drives both outputs to a low state.
When the PWM input transitions high or low, it is necessary to
insure that both bridge FETS are not on at the same time to
prevent shoot-through currents (break before make). The internal
programmable timers delay the rising edge of either output
resulting with both outputs being off before either of the bridge
FETs is driven on. An 8k resistor connected between RDT and
VSS results in a nominal dead time of 220ns. An 80k results
with a minimum nominal dead time of 25ns. Resistors values
less than 8k and greater than 80k are not recommended.
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to VDD.
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
boot capacitor, the boot voltage will charge very close to VDD
(less the boot diode drop and the low-side FET on voltage).
When the PWM input transitions high, the high-side bridge FET is
driven on after the dead time. Because the HS node is connected
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is VDD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after the charge has been transferred from the boot
capacitor to the gate capacitance.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
The following equations calculate the total charge required for
the Period. This equation assumes that all of the parameters are
constant during the period duration. The error is insignificant if
the ripple is small.
Qc = Qgate80V + Period x (IHB + VHO/RGS + Igate_leak)
Cboot = Qc/(Ripple * VDD)
Cboot = 0.52µF
If the gate to source resistor is removed (RGS is usually not needed
or recommended), then:
Cboot = 0.33µF
VDD = 10V VDD can be any value between 7 and 14VDC
VHB = VDD - 0.6V
= VHO
High side driver bias voltage (VDD - boot diode
voltage) referenced to VHS
Period = 1ms This is the longest expected switching period
IHB = 100µA Worst case high side driver current when
xHO = high
(this value is specified for VDD = 12V but the
error is not significant)
RGS = 100kGate-source resistor
(usually not needed)
Ripple= 5% Desired ripple voltage on the boot cap (larger
ripple is not recommended)
Igate_leak = 100nA From the FET vendor’s datasheet
Qgate80V = 64nC From Figure 21
FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET
12
10
8
6
4
2
0
10 20 30 40 50 60 70 80
QG TOTAL GATE CHARGE (nC)
VGS, GATE-TO-SOURCE VOLTAGE (V)
0
VDS = 80V
VDS = 50V
VDS = 20V
ID = 33A
«PH RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 12 of 16
December 23, 2011
Typical Application Circuit
Figure 22 is an example of how the HIP2120/21 can be
configured for a half bridge power supply application.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high-side FETs
are not usually required if low-side gate-source resistors are
used. If relatively small gate-source resistors are used on the
high-side FETs, be aware that they will load the boot capacitor,
which will then require a larger value for the boot capacitor.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
When the high-side bridge FET turns off (see Figure 23), because
of the inductive characteristics the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low-side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
L is the total parasitic inductance of the low-side FET
drain-source path and di/dt is the rate at which the high-side FET
is turned off. With the increasing power levels of power supplies
and motor, clamping this transient become more and more
significant for the proper operation of the HIP2120/21.
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 19
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low-side FET, a
small value resistor is necessary to limit current when the body
diode of the low-side bridge FET is conducting during the dead
time.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage. The
Absolute Max voltage rating for the xHS node does need to be
observed when the positive transient occurs.
ISL78420
HI
DRIVER
LO
DRIVER
LOGIC
HO
LO
HS
PWM
EN
RDT
VSS
VDD HB
8V TO 15V
100V MAX
PWM
CONTROLLER
FIGURE 22. TYPICAL HALF BRIDGE APPLICATION
VSS
HS
LO
HO
INDUCTIVE
LOAD
+
-
+
-
FIGURE 23. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 13 of 16
December 23, 2011
Power Dissipation
The dissipation of the HIP2120/21 is dominated by the gate
charge required by the driven bridge FETs and the switching
frequency. The internal bias and boot diode also contribute to the
total dissipation but these losses are usually insignificant
compared to the gate charge losses.
The calculation of the power dissipation of the HIP2120/21 is
very simple.
GATE POWER (FOR THE HO AND LO OUTPUTS)
Pgate = 4 x Qgate x Freq x VDD
where
Qgate is the charge of the driven bridge FET at VDD, and
Freq is the switching frequency.
BOOT DIODE DISSIPATION
Idiode_avg = Qgate x Freq
Pdiode = Idiode_avg x 0.6V
where 0.6V is the diode conduction voltage
BIAS CURRENT
Pbias = Ibias x VDD
where Ibias is the internal bias current of the HIP2120/21 at the
switching frequency
TOTAL POWER DISSIPATION
Ptotal = Pgate + Pdiode + Pbias
OPERATING TEMPERATURES
Tj = Ptotal x JA + Tamb
where Tj is the junction temperature at the operating air
temperature, Tamb, in the vicinity of the part.
Tj = Ptotal x JC + TPCB
where Tj is the junction temperature with the operating
temperature of the PCB, TPCB , measured where the EPAD is
soldered.
PC Board Layout
The AC performance of the HIP2120/21 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the HIP2120/21:
• Understand well how power currents flow. The high amplitude
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they’re usually more effective than
parallel traces.
• Planes can also be non-grounded nodes.
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
• The use of low inductance components such as chip resistors
and chip capacitors is recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. The most likely circuit will be the HO and LO
outputs. In PCB designs with long leads on the LI and HI inputs,
it may also be necessary to add series resistors with the LI and
HI inputs.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components.
DEM DEM sil.oom: HIP2120 HIP2121 www.intersil.com askourstaff athlt : rel.inlersil.oom le arts Search. h wwm nlevsiLcomgenlgmducts‘mml www.intersi|.cumLenfiupgugmualandrehamhty‘mml www.mmrsiLcom RENESAS
FN7668 Rev 0.00 Page 14 of 16
December 23, 2011
HIP2120, HIP2121
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
EPAD Design Considerations
The thermal pad of the HIP2120/21 is electrically isolated. It’s
primary function is to provide heat sinking for the IC. It is
recommended to tie the EPAD to VSS (GND).
Figure 24 is an example of how to use vias to remove heat from
the IC substrate.
Depending on the amount of power dissipated by the HIP2120/21,
it may be necessary, to connect the EPAD to one or more ground
plane layers. A via array, within the area of the EPAD, will conduct
heat from the EPAD to the gnd plane on the bottom layer. If inner
PCB layers are available, it is also be desireable to connect these
additional layers with the plated-through vias.
The number of vias and the size of the GND planes required for
adequate heatsinking is determined by the power dissipated by
the HIP2120/21, the air flow, and the maximum temperature of
the air around the IC.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: HIP2120, HIP2121
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
FIGURE 24. PCB VIA PATTERN
EPAD
GND
PLANE
COMPONENT
LAYER
EPAD
GND
PLANE
BOTTOM
LAYER
FIGURE 24. TYPICAL PCB PATTERN FOR THERMAL VIAS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
December 23, 2011 FN7668.0 Initial Release
00 $ 0|-W u|Lfl‘ m _ mL nkLlfiJ a _ u m P ‘M\ _ ,I ' El 7E7B, rim AL 4|.— RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 15 of 16
December 23, 2011
Package Outline Drawing
L9.4x4
9 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/10
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
SIDE VIEW
TOP VIEW
BOTTOM VIEW
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
E-Pad is offset from center.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
4.00 2.20
0.15
(3.80)
(4X)
(9X 0.30)
(6X 0.8)
0 .75
BASE PLANE
C
SEATING PLANE
0.08
C
0.10
C
9 X 0.30
SEE DETAIL "X"
0.10
4
CAMB
INDEX AREA
6
PIN 1
4.00
A
B
PIN #1 INDEX AREA
BSC
3.2 REF
6X 0.80
6
(9 X 0.60)
0 . 00 MIN.
0 . 05 MAX.
C
0 . 2 REF
9X 0 . 40 ± 0.100
3.00
(2.20)
(3.00)
0.05 M C
5
4
9
1
1.2 REF
4
(1.2)
[0. 'm 1% H e w \ \ rflrfiflh ‘ OH J“$O 4‘4 % i fin : r m 3L , RENESAS
HIP2120, HIP2121
FN7668 Rev 0.00 Page 16 of 16
December 23, 2011
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
SIDE VIEW
TOP VIEW
BOTTOM VIEW
NOTES:
4.00 2.60
0.15
( 3.80)
(4X)
( 10X 0 . 30 )
( 8X 0 . 8 )
0 .75
BASE PLANE
C
SEATING PLANE
0.08
C
0.10
C
10 X 0.30
SEE DETAIL "X"
0.10
4
CAMB
INDEX AREA
6
PIN 1
4.00
A
B
PIN #1 INDEX AREA
BSC
3.2 REF
8X 0.80
6
( 10 X 0.60 )
0 . 00 MIN.
0 . 05 MAX.
C
0 . 2 REF
10X 0 . 40
3.00
( 2.60)
( 3.00 )
0.05 M C
6
5
10
1