Fiche technique pour STL60N10F7 de STMicroelectronics

PowerFLAT 5x6
AM15540v2
5
6
7
8
1 2 3 4
Top View
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
Features
Order code VDS RDS(on) max. IDPTOT
STL60N10F7 100 V 18 mΩ 12 A 5 W
• Among the lowest RDS(on) on the market
• Excellent FoM (figure of merit)
• Low Crss/Ciss ratio for EMI immunity
• High avalanche ruggedness
Applications
• Switching applications
Description
This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced
trench gate structure that results in very low on-state resistance, while also reducing
internal capacitance and gate charge for faster and more efficient switching.
Product status link
STL60N10F7
Product summary
Order code STL60N10F7
Marking 60N10F7
Package PowerFLAT 5x6
Packing Tape and reel
N-channel 100 V, 14.5 mΩ typ., 12 A, STripFET F7 DeepGATE Power MOSFET
in a PowerFLAT 5x6 package
STL60N10F7
Datasheet
DS9584 - Rev 4 - February 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 100 V
VGS Gate-source voltage 20 V
ID(1)
Drain current (continuous) at TC = 25 °C 46 A
Drain current (continuous) at TC= 100 °C 33 A
ID(2)
Drain current (continuous) at Tpcb = 25 °C 12 A
Drain current (continuous) at Tpcb= 100 °C 9 A
IDM(2)(3) Drain current (pulsed) 48 A
PTOT(1) Total power dissipation at TC = 25 °C 72 W
PTOT(2) Total power dissipation at Tpcb = 25 °C 5 W
Tstg Storage temperature range
- 55 to 175
°C
TJOperating junction temperature range °C
1. This value is rated according to Rthj-c.
2. This value is rated according to Rthj-pcb.
3. Pulse width is limited by safe operating area.
Table 2. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 2.08
°C/W
Rthj-pcb(1) Thermal resistance junction-pcb 31
1. When mounted on a 1-inch² FR-4 board, 2oz Cu, t < 10 s.
STL60N10F7
Electrical ratings
DS9584 - Rev 4 page 2/17
2Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 3. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 100 V
IDSS Zero gate voltage drain current
VGS = 0 V, VDS = 100 V 1 µA
VGS = 0 V, VDS = 100 V, TC = 125 °C 100 µA
IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V
RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 6 A 14.5 18 mΩ
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance
VDS = 50 V, f = 1 MHz, VGS = 0 V
- 1640 - pF
Coss Output capacitance - 360 - pF
Crss Reverse transfer capacitance - 25 - pF
QgTotal gate charge VDD = 50 V, ID = 12 A, VGS = 10 V
(see Figure 13. Test circuit for gate
charge behavior)
- 25 - nC
Qgs Gate-source charge - 12 - nC
Qgd Gate-drain charge - 5 - nC
Qoss Output charge VDD = 40 V, VGS = 0 V - 28 - nC
Table 5. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 50 V, ID = 6 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 12. Test circuit for resistive
load switching times and
Figure 17. Switching time waveform)
- 15 - ns
trRise time - 17 - ns
td(off) Turn-off-delay time - 24 - ns
tfFall time - 8 - ns
STL60N10F7
Electrical characteristics
DS9584 - Rev 4 page 3/17
Table 6. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 12 A
ISDM(1) Source-drain current (pulsed) - 48 A
VSD (2) Forward on voltage VGS = 0 V, ISD = 16 A - 1.1 V
trr Reverse recovery time ISD = 12 A, di/dt = 100 A/µs,
VDD = 50 V, TJ = 150 °C
(see Figure 14. Test circuit for inductive
load switching and diode recovery times)
- 53 ns
Qrr Reverse recovery charge - 67 nC
IRRM Reverse recovery current - 2.5 A
1. Pulse width limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
STL60N10F7
Electrical characteristics
DS9584 - Rev 4 page 4/17
I mm. (M In I O l O l l [D VDSlV wmw AMmzsw (A) l (A) 40 4|) 30 20 2|) 10 10 D I) I) 2 4 6 8 VHS 3 4 5 6 VGs Ammzm mm”. (V) ‘ ‘ (m 6 1—— 4 14.4 2 14.3 0 14 Z n 10 in Q5 4 12 mm
2.1 Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
10
1
0.1
0.1 1 V
DS
(V)
10
(A)
Ope ration in thisare ais
Limited by max R
DS(on)
1s
100ms
10ms
0.01
Tj=175°C
Tpcb=25°C
Single puls e
AM16122v1
Figure 2. Thermal impedance
Single puls e
0.05
0.02
0.01
δ=0.5
0.2
0.1
K
10 t
p
(s)
-4 10-3
10-2
10-1
10-5
10-3
10-2 10-1 10010
pcb
1
AM16123v1
Figure 3. Output characteristics
I
D
30
10
0
0 2 V
DS
(V)
4
(A)
6
4V
V
GS
=7, 8, 9, 10V
20
40
8
6V
5V
AM16124v1
Figure 4. Transfer characteristics
I
D
40
20
0
35 V
GS
(V)
(A)
4 6
10
30
V
DS
=8V
AM16125v1
Figure 5. Gate charge vs gate-source voltage
V
GS
6
4
2
0
0 10 Q
g
(nC)
(V)
30
8
15 20
10
V
DD
=50V
12
5 25
I
D
=12A
AM16126v1
Figure 6. Static drain-source on-resistance
R
DS(on)
14.4
14.3
14.2
4 I
D
(A)
(mΩ)
2 6
14.5
V
GS
=10V
810
14.6
14.7
12
14.8
AM16127v1
STL60N10F7
Electrical characteristics (curves)
DS9584 - Rev 4 page 5/17
(DP 1000 101) 15 05 21) “mum xo Vast AMlélzgvl 1,2 ox 11.5 11,4 0.2 ,75 , 1,0 1 112 11,99 so 150 T1(°C
Figure 7. Capacitance variations
C
1000
100
0
0 20 V
DS
(V)
(pF)
Cis s
Coss
Crss
40 60 80
AM16114v1
Figure 8. Normalized gate threshold voltage vs
temperature
V
GS(th)
0.8
0.6
0.4
0.2
-75 T
J
(°C)
(norm)
-50
1.2
75
25 50 100
I
D
=250µA
0 125 150
1
-25
AM16129v1
1.0
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
1
0
T
J
(°C)
(norm)
0.5
1.5
2
-75 -50 75
25 50 100
0 125 150
-25
I
D
=6A
V
GS
=10V
AM16130v1
2.0
1.0
Figure 10. Normalized V(BR)DSS vs temperature
AM16132v1
1.00
1.01
Figure 11. Source-drain diode forward characteristics
V
SD
0 4 I
SD
(A)
(V)
2 10
68
0.2
0.3
0.4
0.5
T
J
=-55°C
T
J
=175°C
T
J
=25°C
0.6
0.7
12
0.8
0.9
1
1.1
AM16131v1
1.0
0.9
0.8
STL60N10F7
Electrical characteristics (curves)
DS9584 - Rev 4 page 6/17
3Test circuits
Figure 12. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200
μF VDD
3.3
μF
+
pulse width
VGS
Figure 13. Test circuit for gate charge behavior
AM01469v1
47 kΩ 1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST 100 Ω
100 nF
D.U.T.
+
pulse width
VGS
2200
μF
VG
VDD
Figure 14. Test circuit for inductive load switching and
diode recovery times
AM01470v1
A
D
D.U.T.
SB
G
25 Ω
AA
BB
RG
G
D
S
100 µH
µF
3.3 1000
µF VDD
D.U.T.
+
_
+
fast
diode
Figure 15. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD
+
pulse width
Vi
3.3
µF
2200
µF
Figure 16. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
Figure 17. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STL60N10F7
Test circuits
DS9584 - Rev 4 page 7/17
w [W wwm m «was: TO"
4Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
4.1 PowerFLAT 5x6 type R package information
Figure 18. PowerFLAT 5x6 type R package outline
A0ER_8231817_Rev20
STL60N10F7
Package information
DS9584 - Rev 4 page 8/17
Table 7. PowerFLAT 5x6 type R mechanical data
Dim.
mm
Min. Typ. Max.
A 0.80 1.00
A1 0.02 0.05
A2 0.25
b 0.30 0.50
C 5.80 6.00 6.20
D 5.00 5.20 5.40
D2 4.15 4.45
D3 4.05 4.20 4.35
D4 4.80 5.00 5.20
D5 0.25 0.40 0.55
D6 0.15 0.30 0.45
e 1.27
E 5.95 6.15 6.35
E2 3.50 3.70
E3 2.35 2.55
E4 0.40 0.60
E5 0.08 0.28
E6 0.20 0.325 0.45
E7 0.75 0.90 1.05
K 1.275 1.575
L 0.60 0.80
L1 0.05 0.15 0.25
θ 0° 12°
STL60N10F7
PowerFLAT 5x6 type R package information
DS9584 - Rev 4 page 9/17
S‘DE V‘EW A1 BOTTOM V‘EW I ”'LZ TOP V‘EW
4.2 PowerFLAT 5x6 type R SUBCON package information
Figure 19. PowerFLAT 5x6 type R SUBCON package outline
8472137_SUBCON_998G_REV4
8472137_SUBCON_998G_Type_R_REV4
STL60N10F7
PowerFLAT 5x6 type R SUBCON package information
DS9584 - Rev 4 page 10/17
Table 8. PowerFLAT 5x6 type R SUBCON package mechanical data
Dim.
mm
Min. Typ. Max.
A 0.90 0.95 1.00
A1 0.02
b 0.35 0.40 0.45
b1 0.30
c 0.21 0.25 0.34
D 5.10
D1 4.80 4.90 5.00
D2 3.91 4.01 4.11
e 1.17 1.27 1.37
E 5.90 6.00 6.10
E1 5.70 5.75 5.80
E2 3.34 3.44 3.54
E4 0.15 0.25 0.35
E5 0.06 0.16 0.26
H 0.51 0.61 0.71
K 1.10
L 0.51 0.61 0.71
L1 0.06 0.13 0.20
L2 0.10
P 1.00 1.10 1.20
θ 8° 10° 12°
STL60N10F7
PowerFLAT 5x6 type R SUBCON package information
DS9584 - Rev 4 page 11/17
4.60 3.15 1.90 4.10 0.65 (x4) I '1.15~ 0.80 6.60 H.274 3.81
Figure 20. PowerFLAT 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_20
STL60N10F7
PowerFLAT 5x6 type R SUBCON package information
DS9584 - Rev 4 page 12/17
F1 F0 amines 2.0: .1 (w) Aoku.‘ (I: Do 11.551u.n5 a - —.2 Kg mm H \X ‘ ‘ h /T\ rh (h KM m d x y W \p \p q; q W ‘ 7 7 7 7 7 \ 3 C W (5 A» (5 W :. w \ J \ \7) i J Q J L A“ /
4.3 PowerFLAT 5x6 packing information
Figure 21. PowerFLAT 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 22. PowerFLAT 5x6 package orientation in carrier tape
Pin 1
identification
STL60N10F7
PowerFLAT 5x6 packing information
DS9584 - Rev 4 page 13/17
ma :3» WM m 12 b Mm) Au dimensions are in millimeters 5234350_Reel_rev_c
Figure 23. PowerFLAT 5x6 reel
STL60N10F7
PowerFLAT 5x6 packing information
DS9584 - Rev 4 page 14/17
Revision history
Table 9. Document revision history
Date Revision Changes
29-Mar-2013 1 First release.
23-May-2013 2
– Document status promoted from target data to production data
– Modified: VGS(th) values in Table 4
28-Oct-2013 3
– Modified: title, RDS(on) in cover page
– Modified: RDS(on) typical and max values in Table 4, Ciss typical value in table 5
– Added: QSS in Table 5
– Modified: td(on) and Tr typical values
– Modified: Trr, Qrr and IRRM typical values in Table 7
– Added: Section 2.1: Electrical characteristics (curves)
– Updated: Section 4: Package mechanical data
– Minor text changes
13-Feb-2020 4 Updated Section 4 Package information.
Minor text changes.
STL60N10F7
DS9584 - Rev 4 page 15/17
Contents
1Electrical ratings ..................................................................2
2Electrical characteristics...........................................................3
2.1 Electrical characteristics (curves) .................................................5
3Test circuits .......................................................................7
4Package information...............................................................8
4.1 PowerFLAT 5x6 type R package information........................................8
4.2 PowerFLAT 5x6 type R SUBCON package information ...............................9
4.3 PowerFLAT 5x6 packing information .............................................12
Revision history .......................................................................15
STL60N10F7
Contents
DS9584 - Rev 4 page 16/17
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STL60N10F7
DS9584 - Rev 4 page 17/17