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© Semiconductor Components Industries, LLC, 2016
April, 2019 − Rev. 3
1Publication Order Number:
CAV25256/D
CAV25256
EEPROM Serial 256-Kb SPI
Automotive Grade 1
Description
The CAV25256 is a EEPROM Serial 256−Kb SPI Automotive
Grade 1 device internally organized as 32Kx8 bits. This features a
64−byte page write buffer and supports the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip Select (CS)
input. In addition, the required bus signals are clock input (SCK), data
input (SI) and data output (SO) lines. The HOLD input may be used to
pause any serial communication with the CAV25256 device. The
device features software and hardware write protection, including
partial as well as full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
•Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified
•10 MHz (5 V) SPI Compatible
•2.5 V to 5.5 V Supply Voltage Range
•SPI Modes (0,0) & (1,1)
•64−byte Page Write Buffer
•Additional Identification Page with Permanent Write Protection
•Self−timed Write Cycle
•Hardware and Software Protection
•Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•8−lead SOIC, TSSOP and 8−Ball WLCSP Packages
•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SI
SO
CAV25256
SCK
VSS
VCC
CS
WP
HOLD
Figure 1. Functional Symbol
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
PIN CONFIGURATIONS
SI
HOLD
VCC
VSS
WP
SO
CS 1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−8
V SUFFIX
CASE 751BD
SCK
SOIC (V), TSSOP (Y)
TSSOP−8
Y SUFFIX
CASE 948AL
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundVSS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyVCC
(Top Views)
WLCSP−8*
C8A SUFFIX
CASE 567DG
CSP−8B (X)
VSS
SO
CS
WP
SI
SCK
HOLD
VCC
(*Under development. Contact Sales for availability.)
1
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2
DEVICE MARKINGS
(SOIC−8)(TSSOP−8)
S56E
AYMXXX
S56E = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G= Pb−Free Package
25256E = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G= Pb−Free Package
25256E
AYMXXX
G
G
(WLCSP−8)
25256E = Specific Device Code
A = Assembly Location
L = Wafer Lot
YY = Year
WW = Work Week
25256A
ALYYWW
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Supply Current (Read Mode) Read, SO open, fSCK = 10 MHz 2 mA
ICCW Supply Current (Write Mode) Write, CS = VCC 2 mA
ISB1 Standby Current VIN = GND or VCC, CS = VCC,
WP = VCC, VCC = 5.5 V
3 mA
ISB2 Standby Current VIN = GND or VCC, CS = VCC,
WP = GND, VCC = 5.5 V
5 mA
ILInput Leakage Current VIN = GND or VCC −2 2 mA
ILO Output Leakage Current CS = VCC VOUT = GND or VCC −2 2 mA
VIL Input Low Voltage −0.5 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage IOL = 3.0 mA 0.4 V
VOH Output High Voltage IOH = −1.6 mA VCC − 0.8 V V
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CAV25256
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3
Table 4. PIN CAPACITANCE (Note 5) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (SO) VOUT = 0 V 8 pF
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6)
Symbol Parameter Min Max Units
fSCK Clock Frequency DC 10 MHz
tSU Data Setup Time 10 ns
tHData Hold Time 10 ns
tWH SCK High Time 40 ns
tWL SCK Low Time 40 ns
tLZ HOLD to Output Low Z 25 ns
tRI (Note 7) Input Rise Time 2ms
tFI (Note 7) Input Fall Time 2ms
tHD HOLD Setup Time 0 ns
tCD HOLD Hold Time 10 ns
tVOutput Valid from Clock Low 40 ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 20 ns
tHZ HOLD to Output High Z 25 ns
tCS CS High Time 40 ns
tCSS CS Setup Time 30 ns
tCSH CS Hold Time 30 ns
tCNS CS Inactive Setup Time 20 ns
tCNH CS Inactive Hold Time 20 ns
tWPS WP Setup Time 10 ns
tWPH WP Hold Time 10 ns
tWC (Note 8) Write Cycle Time 5 ms
6. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWER−UP TIMING (Notes 7, 9)
Symbol Parameter Min Max Units
tPUR Power−up to Read Operation 0.1 1 ms
tPUW Power−up to Write Operation 0.1 1 ms
9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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CAV25256
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4
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAV25256.
CS: The chip select input pin is used to enable/disable the
CAV25256. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAV25256 must be
preceded by a high to low transition and concluded with a low
to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAV25256, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
VCC, either directly or through a resistor.
Functional Description
The CAV25256 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the CAV25256 is accomplished by
simply providing the READ command and an address.
Writing to the CAV25256, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAV25256 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAV25256 features an additional Identification Page
(64 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected.
Table 7. INSTRUCTION SET
Instruction Opcode Operation
WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory
WRITE 0000 0010 Write Data to Memory
Figure 2. Synchronous Data Timing
CS
SCK
SI
SO
tCNH
tCSS tWH tWL
tSU
tH
HI−Z
VALID
IN
VALID
OUT
tCSH
tRI
tFI
tVtV
tHO
tCNS
tCS
HI−Z
tDIS
The RDY um W pin is high m m: WPEN [m is 0. The WPEN hiLW Ihc W
CAV25256
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5
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations.
The LIP bit is set by the user with the WRSR command
and is non−volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read−only mode).
Note: The IPL and LIP bits cannot be set to 1 using the
same WRSR instruction. If the user attempts to set (“1”)
both the IPL and LIP bit in the same time, these bits cannot
be written and therefore they will remain unchanged.
Table 8. STATUS REGISTER
7 6 5 4 3 2 1 0
WPEN IPL 0 LIP BP1 BP0 WEL RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
Array Address Protected Protection
BP1 BP0
0 0 None No Protection
0 1 6000−7FFF Quarter Array Protection
1 0 4000−7FFF Half Array Protection
1 1 0000−7FFF Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN WP WEL Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
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CAV25256
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6
WRITE OPERATIONS
The CAV25256 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAV25256. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 3. WREN Timing
SCK
SI
SO
00000 110
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
Figure 4. WRDI Timing
SCK
SI
SO
00000 100
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
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CAV25256
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Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 15 significant address
bits are used by the CAV25256. The 16th address bit is don’t
care, as shown in Table 11. Internal programming will start
after the low to high CS transition. During an internal write
cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY bit will indicate if the
internal write cycle is in progress (RDY high), or the device
is ready to accept commands (RDY low).
Page Write
After sending the first data byte to the CAV25256, the host
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAV25256 is
automatically returned to the write disable state. While the
internal write cycle is in progress, the RDSR command will
output the RDY (Ready) bit status only (i.e., data out = FFh).
Write Identification Page
The additional 64−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
The address bits [A15:A6] are Don’t Care and the
[A5:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
Also, the write to the IP is not accepted if the LIP bit from
the Status Register is set to 1 (the page is locked in
Read−only mode).
Table 11. BYTE ADDRESS
Address Significant Bits Address Don’t Care Bits # Address Clock Pulses
Main Memory Array A14 − A0 A15 16
Identification Page A5 − A0 A15 − A6 16
Figure 5. Byte WRITE Timing
SCK
SI
SO
0000 01 0 D7 D6 D5 D4 D3 D2 D1 D0
012345678
OPCODE DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
21 22 23 24 25 26 27 28 29 30 31
Dashed Line = mode (1, 1)
CS
A0
AN
0
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
SCK
SI
SO
0000 0 10
BYTE ADDRESS*
Data
Byte 1
012345678 212223
24−31 32−39
Data Byte N
OPCODE
7..1 0
24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
ANA0
Data
Byte 3
Data
Byte 2
0
* Please check the Byte Address Table (Table 11)
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8
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
Figure 7. WRSR Timing
0123 45678 10911121314
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
7 6 5 4 3 2 10
0000000 1
OPCODE
Dashed Line = mode (1, 1)
CS
Figure 8. WP Timing
SCK
WP
Dashed Line = mode (1, 1)
WP
CS
tWPH
tWPS
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CAV25256
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9
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the CAV25256 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
Reading the additional 64−byte Identification Page (IP) is
achieved using the same Read command sequence as used
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A5:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
address register defined by [A5:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 64−byte page
boundary.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAV25256 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register. For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
Figure 9. READ Timing
SCK
SI
SO
BYTE ADDRESS*
0123456789
7 6 5 4 3 2 1 0
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
2120 22 23 24 25 26 27 28 29 30
00 00 0 11
Dashed Line = mode (1, 1)
A0
AN
CS
* Please check the Byte Address Table (Table 11)
0
10
Figure 10. RDSR Timing
012345678 10911121314
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO 7 6 54 3 2 1 0
00000 1 01
Dashed Line = mode (1, 1)
CS
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CAV25256
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10
Hold Operation
The HOLD input can be used to pause communication
between host and CAV25256. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
The CAV25256 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The CAV25256 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Figure 11. HOLD Timing
SCK
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
tLZ
CS
HOLD
tCD
tHD
tHD
tCD
tHZ
ORDERING INFORMATION (Notes 10 − 12)
Device Order
Number
Specific
Device
Marking
Package
Type Temperature Range Lead Finish Shipping†
CAV25256VE−GT3 25256E SOIC−8−40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel
CAV25256YE−GT3 S56E TSSOP−8−40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel
CAV25256C8ATR
(Note 13)
25256A WLCSP−8−40°C to +125°C SnAgCu Tape & Reel, 4,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.All packages are RoHS−compliant (Lead−free, Halogen−free).
11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
12.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
13.This package option is currently under development. Please contact your nearest ON Semiconductor Sales office for availability.
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SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34272E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC 8, 150 MILS
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" :Fa | i? :L ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
DATE 19 DEC 2008
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34428E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP8, 4.4X3
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
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