Fiche technique pour HMC637ALP5E de Analog Devices Inc.

ANALOG DEVICES
GaAs, pHEMT, MMIC,
1 W Power Amplifier, 0.1 GHz to 6 GHz
Data Sheet HMC637ALP5E
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
P1dB output power: 29 dBm
Gain: 13 dB
Output IP3: 44 dBm
50 Ω matched input/output
32-lead, 5 mm × 5 mm LFCSP package: 25 mm2
APPLICATIONS
Telecom infrastructure
Microwave radio
Very small aperture terminal (VSAT)
Military and space
Test instrumentation
Fiber optics
FUNCTIONAL BLOCK DIAGRAM
17308-001
NIC = NO INTERNAL CONNECTION
17
1
3
4
2
9
5
6
7
8
18
19
20
21
22
23
24
12
11
10
13
14
15
16 25
26
27
28
29
30
31
32
HMC637ALP5E
NIC
V
GG2
NIC
GND
RFIN
NIC
NIC
NIC NIC
NIC
NIC
NIC
RFOUT/V
DD
GND
NIC
NIC
NIC
GND
NIC
NIC
V
GG1
NIC
ACG4
ACG3 NIC
NIC
NIC
NIC
ACG2
ACG1
NIC
NIC
Figure 1.
GENERAL DESCRIPTION
The HMC637ALP5E is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT) distributed power
amplifier which operates between 0.1 GHz and 6 GHz. The
amplifier provides 13 dB of gain, 44 dBm output third-order
intercept (IP3), and 29 dBm of output power at 1 dB gain
compression while requiring 400 mA from a 12 V supply. Gain
flatness is ±0.75 dB from 100 MHz to 6 GHz making the
HMC637ALP5E ideal for electronic warfare (EW), electronic
counter-measure (ECM), radar and test equipment applications.
The HMC637ALP5E amplifier radio frequency (RF) I/Os are
internally matched to 50 Ω, and the 5 mm × 5 mm lead frame
chip scale package (LFCSP) is compatible with high volume
surface-mount technology (SMT) assembly equipment.
HMC637ALP5E Data Sheet
Rev. C | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution...................................................................................4
Pin Configuration and Function Descriptions ..............................5
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Applications Information .................................................................9
Evaluation PCB ............................................................................... 10
List of Materials for PCB EV1HMC637ALP5E ..................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
4/2019—v02.0418 to Rev. C
Updated Format .................................................................. Universal
Changed HMC637ALP5 to HMC637ALP5E ........... Throughout
Changes to Product Title, Features Section, Applications
Section, General Description Section, and Figure 1 .................... 1
Changes to Electrical Specifications Section and Table 1 ........... 3
Changes to Table 2 ............................................................................ 4
Added Thermal Resistance Section ............................................... 4
Added Table 3; Renumbered Sequentially ..................................... 4
Added Figure 2; Renumbered Sequentially ................................... 5
Changes to Table 4 ............................................................................. 5
Changes to Figure 10 Caption through Figure 14 Caption ......... 7
Changes to Figure 15 Caption, Figure 16 Caption, Figure 18
Caption, and Figure 20 Caption ...................................................... 8
Changes to Application Information Section and Figure 21 ....... 9
Changes to List of Materials for PCB EV1HMC637ALP5E
Section and Table 5 ......................................................................... 10
Changes to Ordering Guide .......................................................... 11
Data Sheet HMC637ALP5E
Rev. C | Page 3 of 11
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, drain bias voltage (VDD) = 12 V, gate bias voltage (VGG2) = 5 V, supply current (IDD) = 400 mA (adjust VGG1 between −2 V to 0 V to
achieve IDD = 400 mA typical), 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Units
FREQUENCY RANGE 0.1 6 GHz
GAIN 12 13 dB
Gain Flatness ±0.75 dB
Gain Variation Over Temperature 0.015 dB/°C
RETURN LOSS
Input 12 dB
Output 15 dB
OUTPUT
Output Power for 1 dB Compression P1dB 27 29 dBm
Saturated Output Power PSAT 31 dBm
Output Third-Order Intercept OIP3 POUT per tone = 10 dBm, 1 MHz spacing 44 dBm
NOISE FIGURE 12 dB
2.0 GHz to 6.0 GHz 5 dB
SUPPLY CURRENT IDD 320 400 480 mA
Drain Bias Voltage1 V
DD I
DD = 400 mA 11.5 V
12.0 V
12.5 V
1 VGG1 set initially for nominal bias condition of VDD = 12 V and VGG2 = 5 V to achieve IDD = 400 mA typical; then adjusting VDD ±0.5 V from 12 V to measure IDD variation.
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HMC637ALP5E Data Sheet
Rev. C | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Drain Bias Voltage (VDD) 14 VDC
Gate Bias Voltage
VGG1 −3 VDC to 0 VDC
VGG2 4 VDC to 7 VDC
RF Input Power (RFIN), VDD = 12 VDC 25 dBm
Channel Temperature 175°C
Continuous PDISS (T = 85°C, Derate
95 mW/°C Above 85°C)
8.6 W
Maximum Peak Reflow Temperature 260°C (MSL31 Rating)
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) Class 1B
1 MSL3 stands for Moisture Sensitivity Level 3.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJC1 Unit
HCP-32-1 10.5 °C/W
1 Thermal impedance simulated values are based on a JEDEC 1S0P thermal
test board. See JEDEC JESD51.
ESD CAUTION
H MCGS7ALP5E row vusw (NM m 5cm)
Data Sheet HMC637ALP5E
Rev. C | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17308-002
17
1
3
4
2
9
5
6
7
8
18
19
20
21
22
23
24
12
11
10
13
14
15
16 25
26
27
28
29
30
31
32
HMC637ALP5E
TOP VIEW
(Not to Scale)
NIC
NOTES
1. NIC = NO INTERNAL CONNECTION. THESE PINS MAY BE CONNECTED TO
RF GROUND. PERFORMANCE IS NOT AFFECTED.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
V
GG2
NIC
GND
RFIN
NIC
NIC
NIC NIC
NIC
NIC
NIC
RFOUT/V
DD
GND
NIC
NIC
NIC
GND
NIC
NIC
V
GG1
NIC
ACG4
ACG3 NIC
NIC
NIC
NIC
ACG2
ACG1
NIC
NIC
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description1
1, 3, 6 to 11, 14, 17 to 20, 23 to 28, 31, 32 NIC No Internal Connection. These pins may be connected to RF ground. Performance
is not affected.
2 VGG2 Gate Control 2 for Amplifier. Apply 5 V to VGG2 for nominal operation. Attach a bypass
capacitor per the application circuit shown in the Applications Information section.
4, 12, 22 GND Ground. Connect Pin 4, Pin 12, and Pin 22 to RF/dc ground.
5 RFIN This pad is dc-coupled and matched to 50 Ω.
13 VGG1 Gate Control 1 for Amplifier. Attach a bypass capacitor per the application circuit
shown in the Applications Information section. Follow the power up and power
down sequences outlines in the Applications Information section.
15 ACG4
Low Frequency Termination. Attach a bypass capacitor per the application circuit
shown in the Applications Information section.
16 ACG3
Low Frequency Termination. Attach a bypass capacitor per the application circuit
shown in the Applications Information section.
21 RFOUT/VDD RF Output/Power Supply Voltage for Amplifier. Connect the dc bias (VDD) network
to provide drain current (IDD). See the application circuit shown in the
Applications Information section.
29 ACG2
Low Frequency Termination. Attach a bypass capacitor per the application circuit
shown in the Applications Information section.
30 ACG1
Low Frequency Termination. Attach a bypass capacitor per the application circuit
shown in the Applications Information section.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
1 See the Interface Schematics section for pin interfaces.
WI: ; HE
HMC637ALP5E Data Sheet
Rev. C | Page 6 of 11
INTERFACE SCHEMATICS
V
GG2
17308-003
Figure 3. VGG2 Interface Schematic
ACG2
ACG1
RFOUT/V
DD
17308-004
Figure 4. ACG1, ACG2, and RFOUT/VDD Interface Schematic
RFIN
17308-005
Figure 5. RFIN Interface Schematic
ACG3
ACG4
17308-006
R
FIN
Figure 6. RFIN, ACG4, and ACG3 Interface Schematic
V
GG1
17308-007
Figure 7. VGG1 Interface Schematic
GND
17308-008
Figure 8. GND Interface Schematic
/\w
Data Sheet HMC637ALP5E
Rev. C | Page 7 of 11
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–20
–10
0
10
20
02468
RESPONSE (dB)
FREQUENCY (GHz)
S21
S11
S22
17308-009
Figure 9. Gain and Return Loss
–30
–25
–20
–15
–5
0
02468
RETURN LOSS (dB)
FREQUENCY (GHz)
–10
+85°C
+25°C
–40°C
17308-010
Figure 10. Input Return Loss vs. Frequency at Various Temperatures
–60
–50
–40
–30
–10
0
02468
ISOLATION (dB)
FREQUENCY (GHz)
–20
+85°C
+25°C
–40°C
17308-011
Figure 11. Reverse Isolation vs. Frequency at Various Temperatures
0
2
6
10
16
18
02468
GAIN (dB)
FREQUENCY (GHz)
14
4
8
12
17308-012
+85°C
+25°C
–40°C
Figure 12. Gain vs. Frequency at Various Temperatures
–30
–25
–20
–15
–5
0
02468
RETURN LOSS (dB)
FREQUENCY (GHz)
–10
+85°C
+25°C
–40°C
17308-013
Figure 13. Output Return Loss vs. Frequency at Various Temperatures
02468
NOISE FIGURE (dB)
FREQUENCY (GHz)
17308-014
2
4
6
8
10
12
14
16
18
20
22
24
+85°C
+25°C
–40°C
Figure 14. Noise Figure vs. Frequency at Various Temperatures
HMC637ALP5E Data Sheet
Rev. C | Page 8 of 11
20
22
24
26
30
32
02468
P1dB (dBm)
FREQUENCY (GHz)
28 +85°C
+25°C
–40°C
17308-015
Figure 15. P1dB vs. Frequency at Various Temperatures
02468
OUTPUT IP3 (dBm)
FREQUENCY (GHz)
17308-016
+85°C
+25°C
–40°C
20
25
30
35
40
45
50
55
60
Figure 16. Output IP3 vs. Frequency at Various Temperatures
–30
–20
–10
0
10
20
0.01 0.1 1 10
RESPONSE (dB)
FREQUENCY (GHz)
17308-017
S21
S11
S22
Figure 17. Gain and Return Loss vs. Frequency, Log Scale
20
22
24
26
30
32
02468
P
SAT
(dB)
FREQUENCY (GHz)
28
+85°C
+25°C
–40°C
17308-018
Figure 18. PSAT vs. Frequency at Various Temperatures
11.5 12.0 12.5
V
DD
(V)
17308-019
10
15
30
25
30
35
40
45
50
GAIN (dB), P1dB (dBm), P
SAT
(dBm), IP3 (dBm)
GAIN
P1DB
P
SAT
OIP3
Figure 19. Gain, Power, and Output IP3 vs. Supply Voltage at 3 GHz, Fixed VGG
0.01 0.1 1 10
OUTPUT IP3 (dBm)
FREQUENCY (GHz)
17308-020
20
25
30
35
40
45
50
55
60
+85°C
+25°C
–40°C
Figure 20. Output IP3 vs. Frequency at Various Temperatures, Log Scale
Data Sheet HMC637ALP5E
Rev. C | Page 9 of 11
APPLICATIONS INFORMATION
For the application circuit shown in Figure 21, VDD must be
applied through a broadband bias tee or external bias network.
The power-up bias sequence is as follows:
1. Set VGG1 to −2 V
2. Set VDD to 12 V
3. Set VGG2 to 5 V
4. Adjust VGG1 to achieve IDD for 400 mA
The power-down sequence is as follows:
1. Remove VGG2 bias
2. Remove VDD bias
3. Remove VGG1 bias
C3
1000pF
V
GG2
RFIN
C1
1000pF
C9
4.7µF
C2
100pF
C5
1000pF
C6
1000pF
C8
4.7µF
C4
1000pF
C7
4.7µF
RFOUT
ACG1 ACG2
ACG4
ACG3
V
DD
HMC637ALP5E
2
5
30
13
15
29
16
21
V
GG1
+
+
+
17308-021
Figure 21. Application Circuit
J2
HMC637ALP5E Data Sheet
Rev. C | Page 10 of 11
EVALUATION PCB
17308-022
Figure 22. Evaluation Board PCB
LIST OF MATERIALS FOR PCB EV1HMC637ALP5E
It is recommended that the circuit board used in the application
follows proper RF circuit design techniques. Signal lines must
have 50 Ω impedance while the package ground leads and
package bottom are connected directly to the ground plane
similar to that shown in Figure 22. Ensure that a sufficient
number of via holes are used to connect the top and bottom
ground planes. The evaluation board thermal design must also
be considered and mounted to an appropriate heat sink. The
evaluation circuit board shown is available from Analog
Devices, Inc. upon request.
Table 5. Bill of Materials for Evaluation PCB
EV1HMC637ALP5E
Item Description
J1, J2 SRI SMA connector
J3, J4 2 mm Molex header
C1, C2 100 pF capacitor, 0402 package
C3 to C6 1000 pF capacitor, 0603 package
C7 to C9 4.7 μF capacitor, tantalum
U1 HMC637ALP5E
PCB1 109765 evaluation PCB
1 Circuit board material: Rogers 4350.
: "ZS-Ho fliykfi Human,” 3 £71 LE E TE E : 3 E l v 7 ‘2; 7J, mrwnnnm’ L ANALOG DEVICES www.ana|ng.cum
Data Sheet HMC637ALP5E
Rev. C | Page 11 of 11
OUTLINE DIMENSIONS
02-19-2019-B
1
0.50
BSC
BOTTOM VIEWTOP VIEW
32
916
17
24
25
8
EXPOSED
PAD
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.90
0.85
0.80
0.45
0.40
0.35
0.20 MIN
3.80
3.70 SQ
3.60
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4
PKG-004898
3.50 REF
PIN 1
INDICATORAREAOPTIONS
(SEEDETAILA)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATOR
AREA
SEATING
PLANE
Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm and 0.85 mm Package Height
(HCP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC637ALP5E −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] HCP-32-1
HMC637ALP5ETR −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] HCP-32-1
EV1HMC637ALP5 Evaluation Board
1 All devices are RoHS compliant.
2 See the Absolute Maximum Ratings section.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17308-0-4/19(C)