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INA28x-Q1 Automotive Grade, –14-V to +80-V, Bidirectional, High Accuracy,
Low- or High-Side, Voltage Output, Current Shunt Monitor
1 Features
• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C5
•Functional Safety-Capable
–Documentation available to aid functional safety
system design
• Wide Common-Mode Range: –14 V to +80 V
• Offset Voltage: ±20 μV
• CMRR: 140 dB
• Accuracy:
– ±1.4% Gain Error (Maximum)
– 0.3 μV/°C Offset Drift
– 0.005%/°C Gain Drift (Maximum)
• Available Gains:
– 50 V/V: INA282-Q1
– 100 V/V: INA286-Q1
– 200 V/V: INA283-Q1
– 500 V/V: INA284-Q1
– 1000 V/V: INA285-Q1
• Quiescent Current: 900 μA (Maximum)
2 Applications
• EV and HEV Battery Management
• EV and HEV Chargers
• Electric Power Steering (EPS) Systems
• Body Control Modules
• Brake Systems
• Electronic Stability Control (ESC) Systems
3 Description
The INA28x-Q1 family includes the INA282-Q1,
INA283-Q1, INA284-Q1, INA285-Q1, and INA286-Q1
devices. These devices are voltage output current
shunt monitors that can sense drops across shunts at
common-mode voltages from –14 V to +80 V,
independent of the supply voltage. The low offset of
the zero-drift architecture enables current sensing
with maximum drops across the shunt as low as 10
mV full-scale.
These current sense amplifiers operate from a single
2.7-V to 18-V supply, drawing a maximum of 900 μA
of supply current. These devices are specified over
the extended operating temperature range of –40°C to
+125°C, and offered in SOIC-8 and VSSOP-8
packages.
Device Information (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
INA28x-Q1 SOIC (8) 4.90 mm × 3.91 mm
VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
‡1‡2‡2‡1
‡2‡2
Bus Supply
±14 V to +80 V Load
Zer -
Drift
‡
‡1‡1
OUT
REF2
REF1
GND
2.7 V to 18 V
V+
+IN ±IN
Output
33.3 k
33.3 k
Detailed Block Diagram
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 21
9 Power Supply Recommendations................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Receiving Notification of Documentation Updates.. 26
11.2 Support Resources................................................. 26
11.3 Trademarks............................................................. 26
11.4 Electrostatic Discharge Caution.............................. 26
12 Glossary....................................................................... 26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
Changes from Revision B (December 2015) to Revision C (January 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added Functional-Safety Capable bullets...........................................................................................................1
Changes from Revision A (July 2015) to Revision B (December 2015) Page
• Changed VSSOP package from product preview to production data.................................................................1
Changes from Revision * (March 2012) to Revision A (May 2015) Page
• Changed data sheet title from High-Accuracy, Wide Common-Mode Range, Bi-Directional CURRENT SHUNT
MONITOR Zerø-Drift Series to INA28x-Q1 Automotive Grade, –14-V to 80-V, Bidirectional, High Accuracy,
Low- or High-Side, Voltage Output Current Shunt Monitor ................................................................................1
• Added DGK (VSSOP) package to data sheet.................................................................................................... 1
• Changed Applications ........................................................................................................................................1
• Changed front page diagram..............................................................................................................................1
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 3
• Added RVRR as symbol for reference rejection ratio ........................................................................................5
• Changed order of figures in Typical Characteristics section...............................................................................7
• Changed Figure 6-16 .........................................................................................................................................7
• Changed VDRIVE condition in Figure 6-20 and Figure 6-21 ................................................................................7
• Added functional block diagram........................................................................................................................13
• Changed Figure 7-1 and Figure 7-2 ................................................................................................................ 15
• Changed Figure 7-3 and Figure 7-4 ................................................................................................................ 16
• Changed Figure 7-5 and Figure 7-6 ................................................................................................................ 16
• Changed Figure 7-7 .........................................................................................................................................17
• Changed Reference Common-Mode Rejection to Reference Voltage Rejection Ratio ...................................18
• Changed RCMR to RVRR in Table 7-1 and Table 7-2 .......................................................................................19
• Changed Figure 8-1 .........................................................................................................................................20
• Changed Figure 8-2 .........................................................................................................................................21
• Changed Figure 8-4 .........................................................................................................................................23
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
-IN
GND
REF2
NC(1) OUT
V+
REF1
+IN
A. NC: This pin is not internally connected. The NC pin should either be left floating or connected to GND.
Figure 5-1. D and DGK Package 8-Pin SOIC and VSSOP Top View
Table 5-1. Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 –IN Analog input Connection to negative side of shunt resistor.
2 GND Analog Ground
3 REF2 Analog input Reference voltage, 0 V to V+. See Section 7.4.1 for connection options.
4 NC — This pin is not internally connected. The NC pin should either be left floating or connected to
GND.
5 OUT Analog output Output voltage
6 V+ Analog Power supply, 2.7 V to 18 V
7 REF1 Analog input Reference voltage, 0 V to V+. See Section 7.4.1 for connection options.
8 +IN Analog input Connection to positive side of shunt resistor.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Supply voltage, V+ 18 V
Analog inputs,
V+IN, V–IN (2)
Differential (V+IN) – (V–IN)(3) –5 5 V
Common-Mode –14 80 V
REF1, REF2, OUT GND–0.3 (V+) + 0.3 V
Input current into any pin 5 mA
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) V+IN and V–IN are the voltages at the +IN and –IN pins, respectively.
(3) Input voltages must not exceed common-mode rating.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCM Common-mode input voltage 12 V
V+ Operating supply voltage 5 V
TAOperating free-air temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)
INA28x-Q1
UNITD (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 134.9 164.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.9 56.4 °C/W
RθJB Junction-to-board thermal resistance 61.3 85.0 °C/W
ψJT Junction-to-top characterization parameter 18.9 6.5 °C/W
ψJB Junction-to-board characterization parameter 54.3 83.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
at TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset Voltage, RTI(1) VSENSE = 0 mV ±20 ±70 μV
dVOS/dT vs Temperature TA = –40°C to 125°C ±0.3 ±1.5 μV/°C
PSRR vs Power Supply VS = 2.7 V to 18 V, VSENSE = 0 mV 3 μV/V
VCM Common-Mode Input Range TA = –40°C to 125°C –14 +80 V
CMRR Common-Mode Rejection V+IN = –14 V to 80 V, VSENSE = 0 mV
TA = –40°C to 125°C 120 140 dB
IBInput Bias Current per Pin(2) VSENSE = 0 mV 25 μA
IOS Input Offset Current VSENSE = 0 mV 1 μA
Differential Input Impedance 6 kΩ
REFERENCE INPUTS
Reference Input Gain 1 V/V
Reference Input Voltage Range(3) 0 VGND + 9 V
Divider Accuracy(4) ±0.2% ±0.5%
RVRR
Reference Voltage Rejection Ratio
(VREF1 = VREF2 = 40 mV to 9 V,
V+ = 18 V)
INA282-Q1 ±25 ±75 μV/V
TA = –40°C to 125°C 0.055 μV/V/°C
INA283-Q1 ±13 ±30 μV/V
TA = –40°C to 125°C 0.040 μV/V/°C
INA284-Q1 ±6 ±25 μV/V
TA = –40°C to 125°C 0.015 μV/V/°C
INA285-Q1 ±4 ±10 μV/V
TA = –40°C to 125°C 0.010 μV/V/°C
INA286-Q1 ±17 ±45 μV/V
TA = –40°C to 125°C 0.040 μV/V/°C
GAIN (6) (GND + 0.5 V ≤ VOUT ≤ (V+) – 0.5 V; VREF1 = VREF2 = (V+) / 2 for all devices)
G Gain
INA282-Q1, V+ = 5 V 50 V/V
INA283-Q1, V+ = 5 V 200 V/V
INA284-Q1, V+ = 5 V 500 V/V
INA285-Q1, V+ = 5 V 1000 V/V
INA286-Q1, V+ = 5 V 100 V/V
Gain Error
INA282-Q1, INA283-Q1, INA286-Q1 ±0.4% ±1.4%
INA284-Q1, INA285-Q1 ±0.4% ±1.6%
TA = –40°C to 125°C 0.0008 0.005 %/°C
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at TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
Nonlinearity Error ±0.01%
Output Impedance 1.5 Ω
Maximum Capacitive Load No sustained oscillation 1 nF
VOLTAGE OUTPUT (5)
Swing to V+ Power-Supply Rail V+ = 5 V, RLOAD = 10 kΩ to GND
TA = –40°C to 125°C (V+)–0.17 (V+)–0.4 V
Swing to GND TA = –40°C to 125°C GND+0.015 GND+0.04 V
FREQUENCY RESPONSE
BW Effective Bandwidth(7)
INA282-Q1 10
kHz
INA283-Q1 10
INA284-Q1 4
INA285-Q1 2
INA286-Q1 10
NOISE, RTI (1)
Voltage Noise Density 1 kHz 110 nV/√ Hz
POWER SUPPLY
VSSpecified Voltage Range TA = –40°C to 125°C 2.7 18 V
IQQuiescent Current 600 900 μA
TEMPERATURE RANGE
Specified Range –40 125 °C
(1) RTI = referred-to-input.
(2) See typical characteristic graph Figure 6-7 .
(3) The average of the voltage on pins REF1 and REF2 must be between VGND and the lesser of (VGND+9 V) and V+.
(4) Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 7-5.
(5) See typical characteristic graphs Figure 6-16 through Figure 6-18.
(6) See typical characteristic graph Figure 6-12.
(7) See typical characteristic graph Figure 6-1 and Section 7.3.2 in the Applications Information.
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TEXAS INSTRUMENTS Frequency (Hz)
6.6 Typical Characteristics
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN,
unless otherwise noted.
60
50
40
30
20
10
0
-10
-20
Gain (dB)
10 100 1k 10k 100k 1M
Frequency (Hz)
INA282-Q1 (50V/V)
INA285- (1kV/V)
INA284 (500V/V)
INA283 (200V/V)
INA286 (100V/V)
Q1
-Q1
-Q1
-Q1
Figure 6-1. Gain vs Frequency
100 1k 10k 100k 1M
Frequency(Hz)
120
110
100
90
80
70
60
50
40
30
20
Power-SupplyRejectionRatio(dB)
Figure 6-2. INA282-Q1 PSRR (RTI) vs Frequency
150
140
130
120
110
100
90
80
70
Common-ModeRejectioRatio(dB)
1 10 100 1k 10k 100k
Frequency(Hz)
Figure 6-3. INA284-Q1 Common-Mode Rejection
Ratio (RTI)
1k 10k 100k 1M
V SlewRate(V/sec)
CM
0.1
0.01
0.001
0.0001
0.00001
0.000001
V ,Referred-to-Input(V)
OS
Figure 6-4. INA282-Q1 Common-Mode Slew Rate
Induced Offset
1k
100
10
1
0.1
R ( )W
OUT
10 100 1k 10k 100k 1M
Frequency(Hz)
Figure 6-5. INA286-Q1 Output Impedance vs
Frequency
Figure 6-6. INA282-Q1 Typical Nonlinearity vs
Output Voltage
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-20 -10 0 10 20 30 40 50 60 70 80
Common-ModeVoltage(V)
30
20
10
0
10
20
30
40-
-
-
-
+INBiasCurrent( A)m
V+=2.7V V+=5V
V+=18V
Figure 6-7. INA283-Q1 +IN BIAS Current vs
Common-Mode Voltage
900
850
800
750
700
650
600
550
500
450
400
QuiescentCurrent( A)m
-20 0 20 40 60 80
Common-ModeVoltage(V)
V+=2.7V
V+=5V
V+=18V
Figure 6-8. INA283-Q1 Quiescent Current vs
Common-Mode Voltage
900
800
700
600
500
400
300
200
100
0
Quiescent Current ( A)m
246 8 10 12 14 16 18
Supply Voltage (V)
Figure 6-9. Quiescent Current vs Supply Voltage
170
160
150
140
130
120
110
100
90
80
Common-Mode Rejection Ratio (dB)
-75 -50 -25 0 25 50 75 100 125 150
Temperature ( C)
°
V+ = 5V
V+ = 12V
Figure 6-10. Common-Mode Rejection Ratio vs
Temperature
980
880
780
680
580
480
380
280
180
80
Quiescent Current ( A)m
-75 -50 -25 0 25 50 75 100 125 150
Temperature ( C)
°
V+ = 2.7V
V+ = 5V
V+ = 18V
Figure 6-11. Quiescent Current vs Temperature
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0-
-
-
-
-
DeviationinGain(%)
-75 -50 -25 0 25 50 75 100 125 150
Temperature( C)
°
V+=5V
V+=12V
Figure 6-12. Deviation in Gain vs Temperature
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0
5
10
15
20
25
30
35
40
-
-
-
-
-
-
-
-
+IN Bias Current ( A)m
-75 -50 -25 0 25 50 75 100 125 150
Temperature ( C)
°
V+ = 2.7V
V+ = 5V
V+ = 18V
V = 0V
CM
Figure 6-13. +IN BIAS Current vs Temperature
VoltageNoise,RTI(200nV/div)
Time(1s/div)
Figure 6-14. INA282-Q1 0.1-Hz to 10-Hz Voltage
Noise, RTI
VoltageNoise,RTO( V/ )mHz
Ö
VoltageNoise,RTI( V/ )mHzÖ
Frequency(Hz)
100 1k 10k 100k
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.12
0.11
0.10
0.09
0.08
0.07
0.06
Figure 6-15. INA282-Q1 Voltage Noise vs
Frequency
0 1 2 3 4 5 678 9 10
I (mA)
OUT
V+
V+) – 2
V+) – 4
V+) – 6
V+) – 8
(
(
(
(
GND + 8
GND + 6
GND + 4
GND + 2
GND
Output Voltage Swing (V)
18V
5V
2.7V
Figure 6-16. INA284-Q1 Output Voltage Swing vs
Output Current
SwingtoRail(mV)
800
700
600
500
400
300
200
100
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
I ,Sourcing(mA)
OUT
2.7VSwing
5VSwing
+25 C°
+125 C°+85 C°
-40 C°
Figure 6-17. INA283-Q1 Swing to Rail vs Output
Current
SwingtoGround(mV)
400
350
300
250
200
150
100
50
0
0 0.5 1.0 1.5 2.0 2.5
I ,Sinking(mA)
OUT
+25 C°
+125 C°
+85 C°
-40 C°
2.7VSwing
5VSwing
18VSwing
Figure 6-18. INA283-Q1 Swing to Ground vs Output
Current
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V+
VOUT
C = 10pF
V = GND
V = 50mV
R = 10k
LOAD
REF
SENSE
LOAD W
25 s/divm
5V/div 500mV/div
Figure 6-19. Start-Up Transient Response
V+
VOUT
250 s/divm
5V/div 500mV/div
V = GND, V = 50mV, R = 10k , C = 10pFW
REF SENSE LOAD LOAD
Figure 6-20. Start-Up Transient Response
VCM
VOUT
2.5 s/divm
5V/div 500mV/div
Figure 6-21. 12-V Common-Mode Step Response
VCM
VOUT
2.5 s/divm
5V/div 500mV/div
Figure 6-22. 12-V Common-Mode Step Response
2.5 s/divm
5V/div 500mV/div
VCM
VOUT
Figure 6-23. 12-V Common-Mode Step Response
VCM
VOUT
2.5 s/divm
5V/div 500mV/div
Figure 6-24. 12-V Common-Mode Step Response
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VCM
VOUT
5 s/divm
10V/div 500mV/div
Figure 6-25. 50-V Common-Mode Step Response
VCM
VOUT
5 s/divm
10V/div 500mV/div
Figure 6-26. 50-V Common-Mode Step Response
10 s/divm
20mV/div
Figure 6-27. 100-mV Step Response
10 s/divm
100mV/div
Figure 6-28. 500-mV Step Response
25 s/divm
1V/div
Figure 6-29. 4-V Step Response
5V/div
25 s/divm
Figure 6-30. 17-V Step Response
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InputDrive(1Vto0V)
V (5Vtomidsupply)
OUT
1V/div
25 s/divm
Figure 6-31. Input Overload
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7 Detailed Description
7.1 Overview
The INA28x-Q1 family of voltage output current-sensing amplifiers are specifically designed to accurately
measure voltages developed across current-sensing resistors on common-mode voltages that far exceed the
supply voltage powering the devices. This family features a common-mode range that extends 14 V less than
the negative supply rail, as well as up to 80 V, allowing for either low-side or high-side current sensing while the
device is powered from supply voltages as low as 2.7 V.
The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as 70
µV with a maximum temperature contribution of 1.5 µV/°C over the full temperature range of –40°C to 125°C.
7.2 Functional Block Diagram
+
±
+
±
V+
±IN
REF1
+IN
GND
REF2
OUT
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7.3 Feature Description
7.3.1 Selecting RS
The zero-drift offset performance of the INA28x-Q1 family offers several benefits. Most often, the primary
advantage of the low offset characteristic enables lower full-scale drops across the shunt. For example, nonzero-
drift, current-shunt monitors typically require a full-scale range of 100 mV. The INA28x-Q1 family gives
equivalent accuracy at a full-scale range on the order of 10 mV. This accuracy reduces shunt dissipation by an
order of magnitude, with many additional benefits. Alternatively, applications that must measure current over a
wide dynamic range can take advantage of the low offset on the low end of the measurement. Most often, these
applications can use the lower gains of the INA282-Q1, INA286-Q1, or INA283-Q1 to accommodate larger shunt
drops on the upper end of the scale. For instance, an INA282-Q1 operating on a 3.3-V supply can easily handle
a full-scale shunt drop of 55 mV, with only 70 μV of offset.
7.3.2 Effective Bandwidth
The extremely high DC CMRR of the INA28x-Q1 results from the switched capacitor input structure. Because of
this architecture, the INA28x-Q1 exhibits discrete time system behaviors as illustrated in the gain versus
frequency graph of Figure 6-3 and the step response curves of Figure 6-21 through Figure 6-28. The response
to a step input depends somewhat on the phase of the internal INA28x-Q1 clock when the input step occurs. It is
possible to overload the input amplifier with a rapid change in input common-mode voltage (see Figure 6-4).
Errors as a result of common-mode voltage steps and/or overload situations typically disappear within 15 μs
after the disturbance is removed.
7.3.3 Transient Protection
The –14-V to 80-V common-mode range of the INA28x-Q1 is ideal for withstanding automotive fault conditions
that range from 12-V battery reversal up to 80-V transients; no additional protective components are needed up
to those levels. In the event that the INA28x-Q1 is exposed to transients on the inputs in excess of its ratings,
then external transient absorption with semiconductor transient absorbers (Zener or Transzorbs) will be
necessary. Use of MOVs or VDRs is not recommended except when they are used in addition to a
semiconductor transient absorber. Select the transient absorber such that it cannot allow the INA28x-Q1 to be
exposed to transients greater than 80 V (that is, allow for transient absorber tolerance, as well as additional
voltage as a result of transient absorber dynamic impedance). Despite the use of internal zener-type electrostatic
discharge (ESD) protection, the INA28x-Q1 does not lend itself to using external resistors in series with the
inputs without degrading gain accuracy.
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7.4 Device Functional Modes
7.4.1 Reference Pin Connection Options
Figure 7-1 illustrates a test circuit for reference divider accuracy. The output of the INA28x-Q1 can be connected
for unidirectional or bidirectional operation. Neither the REF1 pin nor the REF2 pin may be connected to any
voltage source lower than GND or higher than V+, and that the effective reference voltage (REF1 + REF2)/2
must be 9 V or less. This parameter means that the V+ reference output connection shown in Figure 7-3 is not
allowed for V+ greater than 9 V. However, the split-supply reference connection shown in Figure 7-5 is allowed
for all values of V+ up to 18 V.
Input Stage
+
±
REF2
REF1
V+
GND
OUT
V+
See Note (1)
±IN+IN
A. Reference divider accuracy is determined by measuring the output with the reference voltage applied to alternate reference resistors,
and calculating a result such that the amplifier offset is cancelled in the final measurement.
Figure 7-1. Test Circuit for Reference Divider Accuracy
7.4.1.1 Unidirectional Operation
Unidirectional operation allows the INA28x-Q1 to measure currents through a resistive shunt in one direction. In
the case of unidirectional operation, the output could be set at the negative rail (near ground, and the most
common connection) or at the positive rail (near V+) when the differential input is 0V. The output moves to the
opposite rail when a correct polarity differential input voltage is applied.
The required polarity of the differential input depends on the output voltage setting. If the output is set at the
positive rail, the input polarity must be negative to move the output down. If the output is set at ground, the
polarity is positive to move the output up.
The following sections describe how to configure the output for unidirectional operation.
7.4.1.1.1 Ground Referenced Output
When using the INA28x-Q1 in this mode, both reference inputs are connected to ground; this configuration takes
the output to the negative rail when there is 0V differential at the input (as Figure 7-2 shows).
Input Stage
+
±
REF2
REF1
V+
GND
OUT
V+
±IN+IN
Figure 7-2. Ground Referenced Output
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7.4.1.1.2 V+ Referenced Output
This mode is set when both reference pins are connected to the positive supply. It is typically used when a
diagnostic scheme requires detection of the amplifier and the wiring before power is applied to the load (as
shown in Figure 7-3).
Input Stage
+
±
±IN+IN
REF2
REF1
V+
GND
OUT
V+
Figure 7-3. V+ Referenced Output
7.4.1.2 Bidirectional Operation
Bidirectional operation allows the INA28x-Q1 to measure currents through a resistive shunt in two directions. In
this case, the output can be set anywhere within the limits of what the reference inputs allow (that is, from 0 V to
9 V, but never to exceed the supply voltage). Typically, it is set at half-scale for equal range in both directions. In
some cases, however, it is set at a voltage other than half-scale when the bidirectional current is
nonsymmetrical.
The quiescent output voltage is set by applying voltage(s) to the reference inputs. REF1 and REF2 are
connected to internal resistors that connect to an internal offset node. There is no operational difference between
the pins.
7.4.1.2.1 External Reference Output
Connecting both pins together and to a reference produces an output at the reference voltage when there is no
differential input; this configuration is illustrated in Figure 7-4. The output moves down from the reference voltage
when the input is negative relative to the –IN pin and up when the input is positive relative to the –IN pin. This
technique is the most accurate way to bias the output to a precise voltage.
Input Stage
+
±
±IN+IN
REF2
REF1
V+
GND
OUT
V+
REF3020
2.048-V
Reference
Figure 7-4. External Reference Output
7.4.1.2.2 Splitting the Supply
By connecting one reference pin to V+ and the other to the ground pin, the output is set at half of the supply
when there is no differential input, as shown in Figure 7-5. This method creates a midscale offset that is
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ratiometric to the supply voltage; thus, if the supply increases or decreases, the output remains at half the
supply.
Input Stage
+
±
±IN+IN
REF2
REF1
V+
GND
OUT Output
V+
Figure 7-5. Split-Supply Output
7.4.1.2.3 Splitting an External Reference
In this case, an external reference is divided by 2 with an accuracy of approximately 0.5% by connecting one
REF pin to ground and the other REF pin to the reference (as Figure 7-6 illustrates).
Input Stage
+
±
±IN+IN
REF2
REF1
V+
GND
OUT
V+
REF02
5-V
Reference
Figure 7-6. Split Reference Output
7.4.2 Shutdown
While the INA28x-Q1 family does not provide a shutdown pin, the quiescent current of 600 μA enables the
device to be powered from the output of a logic gate. Take the gate low to shut down the INA28x-Q1 family
devices.
7.4.3 Extended Negative Common-Mode Range
Using a negative power supply can extend the common-mode range 14 V more negative than the supply used.
For instance, a –10 V supply allows up to –24-V negative common-mode. Remember to keep the total voltage
between the GND pin and V+ pin to less than 18 V. The positive common-mode decreases by the same amount.
The reference input simplifies this type of operation because the output quiescent bias point is always based on
the reference connections. Figure 7-7 shows a circuit configuration for common-mode ranges from –24 V to 70
V.
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Input Stage
+
±
±IN+IN
REF2
REF1
V+
GND
OUT
Bus Supply
±24 V to +70 V Load
V+ = 5 V
Output
Connect to ±10 V
See Note (1)
A. Connect the REF pins as desired; however, they cannot exceed 9 V greater than the GND pin voltage.
Figure 7-7. Circuit Configuration for Common-Mode Ranges from –24 V to 70 V
7.4.4 Calculating Total Error
The electrical specifications for the INA28x-Q1 family of devices include the typical individual errors terms such
as gain error, offset error, and nonlinearity error. Total error including all of these individual error components is
not specified in Section 6.5. To accurately calculate the expected error of the device, the operating conditions of
the device must first be known. Some current shunt monitors specify a total error in the product data sheet.
However, this total error term is accurate under only one particular set of operating conditions. Specifying the
total error at this one point has little practical value because any deviation from these specific operating
conditions no longer yields the same total error value. This section discusses the individual error sources, with
information on how to apply them to calculate the total error value for the device under any normal operating
conditions.
The typical error sources that have the largest impact on the total error of the device are input offset voltage,
common-mode rejection ratio, gain error, and nonlinearity error. For the INA28x-Q1, an additional error source
referred to as reference voltage rejection ratio is also included in the total error value.
The nonlinearity error of the INA28x-Q1 is relatively low compared to the gain error specification. This low error
results in a gain error that can be expected to be relatively constant throughout the linear input range of the
device. While the gain error remains constant across the linear input range of the device, the error associated
with the input offset voltage does not. As the differential input voltage developed across a shunt resistor at the
input of the INA28x-Q1 decreases, the inherent input offset voltage of the device becomes a larger percentage
of the measured input signal resulting in an increase in error in the measurement. This varying error is present
among all current shunt monitors, given the input offset voltage ratio to the voltage being sensed by the device.
The relatively low input offset voltages present in the INA28x-Q1 devices limit the amount of contribution the
offset voltage has on the total error term.
The term reference voltage rejection ratio refers to the amount of error induced by applying a reference voltage
to the INA28x-Q1 device that deviates from the inherent bias voltage present at the output of the first stage of
the device. The output of the switched-capacitor network and first-stage amplifier has an inherent bias voltage of
approximately 2.048 V. Applying a reference voltage of 2.048 V to the INA28x-Q1 reference pins results in no
additional error term contribution. Applying a voltage to the reference pins that differs from 2.048 V creates a
voltage potential in the internal difference amplifier, resulting in additional current flowing through the resistor
network. As a result of resistor tolerances, this additional current flow causes additional error at the output
because of resistor mismatches. Additionally, as a result of resistor tolerances, this additional current flow
causes additional error at the output based on the common-mode rejection ratio of the output stage amplifier.
This error term is referred back to the input of the device as additional input offset voltage. Increasing the
difference between the 2.048-V internal bias and the external reference voltage results in a higher input offset
voltage. Also, as the error at the output is referred back to the input, there is a larger impact on the input-referred
offset, VOS, for the lower-gain versions of the device.
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Two examples are provided that detail how different operating conditions can affect the total error calculations.
Typical and maximum calculations are shown as well, to provide the user more information on how much error
variance is present from device to device.
7.4.4.1 Example 1 INA282-Q1
Table 7-1. V+ = 5 V; VCM = 12 V; VREF1 = VREF2 = 2.048 V; VSENSE = 10 mV
TERM SYMBOL EQUATION TYPICAL VALUE MAXIMUM VALUE
Initial input offset
voltage VOS — 20 μV 70 μV
Added input offset
voltage because of
common-mode
voltage
VOS_CM
´(V 12V)-
CM
1
CMRR_dB
20
(
(
10
0 μV 0 μV
Added input offset
voltage because of
reference voltage
VOS_REF
±REF
RVRR 2.048 V Vu
0 μV 0 μV
Total input offset
voltage VOS_Total
(V ) +(V ) +(V )
OS OS_CM OS_REF
2 2 2
20 μV 70 μV
Error from input offset
voltage Error_VOS
V
V
OS_Total
SENSE
´100
0.20% 0.70%
Gain error Error_Gain — 0.40% 1.40%
Nonlinearity error Error_Lin — 0.01% 0.01%
Total error —
(Error_V ) +(Error_Gain) +(Error_Lin)
OS
2 2 2
0.45% 1.56%
7.4.4.2 Example 2 INA286-Q1
Table 7-2. V+ = 5 V; VCM = 24 V; VREF1 = VREF2 = 0 V; VSENSE = 10 mV
TERM SYMBOL EQUATION TYPICAL VALUE MAXIMUM VALUE
Initial input offset
voltage VOS — 20 μV 70 μV
Added input offset
voltage because of
common-mode
voltage
VOS_CM
´(V 12V)-
CM
1
CMRR_dB
20
(
(
10
1.2 μV 12 μV
Added input offset
voltage because of
reference voltage
VOS_REF
±REF
RVRR 2.048 V Vu
34.8 μV 92.2 μV
Total input offset
voltage VOS_Total
(V ) +(V ) +(V )
OS OS_CM OS_REF
2 2 2
40.2 μV 116.4 μV
Error from input offset
voltage Error_VOS
V
V
OS_Total
SENSE
´100
0.40% 1.16%
Gain error Error_Gain — 0.40% 1.40%
Nonlinearity error Error_Lin — 0.01% 0.01%
Total error —
(Error_V ) +(Error_Gain) +(Error_Lin)
OS
2 2 2
0.57% 1.82%
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The INA28x-Q1 family of devices measure the voltage developed across a current-sensing resistor when current
passes through it. The ability to drive the reference pins to adjust the functionality of the output signal is shown in
multiple configurations.
8.1.1 Basic Connections
Figure 8-1 shows the basic connection of an INA28x-Q1 family device. Connect the input pins, +IN and –IN, as
close as possible to the shunt resistor to minimize any resistance in series with the shunt resistance.
Input Stage
+
±
REF2
REF1
V+
GND
OUT
Bus Supply
±14 V to +80 V Load
Device Supply
2.7 V to 18 V
0.1 F
CBYPASS
Output
±IN+IN
Figure 8-1. Basic Connections
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
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8.2 Typical Applications
8.2.1 Current Summing
The outputs of multiple INA28x-Q1 family devices are easily summed by connecting the output of one INA28x-
Q1 family device to the reference input of a second INA28x-Q1 family device. The circuit configuration shown in
Figure 8-1 is an easy way to achieve current summing.
Input Stage
+±
±IN+IN
REF2
REF1
V+
GND
OUT
Output
V+
Input Stage
±IN+IN
REF2
REF1
V+
GND
OUT
Output
V+
First Circuit Second Circuit
Summed
Output
VREF
+±
NOTE: The voltage applied to the reference inputs must not exceed 9 V.
Figure 8-2. Summing the Outputs of Multiple INA28x-Q1 Family Devices
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8.2.1.1 Design Requirements
In order to sum multiple load currents, multiple INA28x-Q1 devices must be connected. Figure 8-2 shows
summing for two devices. Summing beyond two devices is possible by repeating this connection. The reference
input of the first INA28x-Q1 family device sets the output quiescent level for all the devices in the string.
8.2.1.2 Detailed Design Procedures
Connect the output of one INA28x-Q1 family device to the reference input of the next INA28x-Q1 family device in
the chain. Use the reference input of the first circuit to set the reference of the final summed output. The currents
sensed at each circuit in the chain are summed at the output of the last device in the chain.
8.2.1.3 Application Curve
Figure 8-3 shows an example output response of a summing configuration. The reference pins of the first circuit
are connected to ground, and sine waves at different frequencies are applied to the two circuits to produce a
summed output as shown. The sine wave voltage input for the first circuit is offset so that the whole wave is
above GND.
Time (4 ms/div)
5 V/div
100 mV/div
Output
Inputs
VREF = 0 V
Figure 8-3. Current Summing Application Output Response
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8.2.2 Current Differencing
Occasionally, the need arises to confirm that the current into a load is identical to the current out of a load,
usually as part of diagnostic testing or fault detection. This situation requires precision current differencing, which
is the same as summing except that the two amplifiers have the inputs connected opposite of each other.
Input Stage
+±
±IN+IN
REF2
REF1
V+
GND
OUT
Output
V+
First Circuit Second Circuit
VREF
Bus Supply Load
Input Stage
±IN+IN
REF2
REF1
V+
GND
OUT
Output
V+
Difference
Output
+±
NOTE: The voltage applied to the reference inputs must not exceed 9 V.
Figure 8-4. Current Differencing Using an INA28x-Q1 Device
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8.2.2.1 Design Requirements
For current differencing, connect two INA28x-Q1 devices, and connect the inputs opposite to each other, as
shown in Figure 8-4. The reference input of the first INA28x-Q1 family device sets the output quiescent level for
all the devices in the string.
8.2.2.2 Detailed Design Procedure
Connect the output of one INA28x-Q1 family device to the reference input of the second INA28x-Q1 family
device. The reference input of the first circuit sets the reference at the output. This circuit example is identical to
the current summing example, except that the two shunt inputs are reversed in polarity. Under normal operating
conditions, the final output is very close to the reference value and proportional to any current difference. This
current differencing circuit is useful in detecting when current into and out of a load do not match.
8.2.2.3 Application Curve
Figure 8-5 shows an example output response of a difference configuration. The reference pins of the first circuit
are connected to a reference voltage of 2.048 V. The inputs to each circuit is a 100-Hz sine wave, 180° out of
phase with each other, resulting in a zero output as shown. The sine wave input to the first circuit is offset so that
the input wave is completely above GND.
Time (4 ms/div)
5 V/div
100 mV/div
Output
Inputs
VREF = 2.048 V
Figure 8-5. Current Differencing Application Output Response
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9 Power Supply Recommendations
The INA28x-Q1 can make accurate measurements well outside of its own power-supply voltage, V+, because its
inputs (+IN and –IN) may operate anywhere from –14 V to 80 V independent of V+. For example, the V+ power
supply can be 5 V while the common-mode voltage being monitored by the shunt may be as high as 80 V. Of
course, the output voltage range of the INA28x-Q1 is constrained by the supply voltage that powers it on V+.
When the power to the INA28x-Q1 is off (that is, no voltage is supplied to the V+ pin), the input pins (+IN and –
IN) are high impedance with respect to ground and typically leak less than ±1 μA over the full common-mode
range of –14 V to 80 V.
10 Layout
10.1 Layout Guidelines
Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique
makes sure that only the current-sensing resistor impedance is detected between the input pins. Poor routing of
the current-sensing resistor commonly results in additional resistance present between the input pins. Given the
very low ohmic value of the current resistor, any additional high-current carrying impedance causes significant
measurement errors.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. TI recommends a
bypass capacitor with a value of 0.1 uF. Add additional decoupling capacitance to compensate for noisy or high-
impedance power supplies.
10.2 Layout Example
Supply Bypass
Capacitor
VIA to Power Plane
VIA to Ground Plane
Supply Voltage
Output Signal Trace
GND
±IN
NC
REF2
+IN
REF1
OUT
V+
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1
SBOS554C – MARCH 2012 – REVISED JANUARY 2021 www.ti.com
26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: INA282-Q1 INA283-Q1 INA284-Q1 INA285-Q1 INA286-Q1
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
INA282AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 11GF
INA282AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 282Q1
INA283AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 11FF
INA283AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 283Q1
INA284AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 11HF
INA284AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 284Q1
INA285AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 11IF
INA285AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 285Q1
INA286AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 11JF
INA286AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 286Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1 :
•Catalog: INA282, INA283, INA284, INA285, INA286
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
INA282AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA282AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA283AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA283AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA284AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA284AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA285AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA285AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA286AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA286AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA282AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0
INA282AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
INA283AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0
INA283AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
INA284AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0
INA284AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
INA285AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0
INA285AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
INA286AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0
INA286AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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