Fiche technique pour ONET4291VA de Texas Instruments

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FEATURES
APPLICATIONS
DESCRIPTION
BLOCK DIAGRAM
ONET4291VA
SLLS674 – SEPTEMBER 2005
1 GBPS TO 4.25 GBPS MULTI-RATE VCSEL DRIVER
•Operating Temperature –40 °C to 85 °C•Multi-Rate Operation from 1 Gbps Up •Small Footprint Surface Mount 4 mm ×4 mm,To 4.25 Gbps 20-Pin QFN Package•2-Wire Digital Interface•Digitally Selectable Modulation Current
•Multirate SFP/SFF Modules•Digitally Selectable Bias Current
•1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre•Automatic Power Control (APC) Loop
Channel Transmitters•Supports Transceiver Management
•Gigabit Ethernet TransmittersSystem (TMS)•Includes Laser Safety Features•Analog Temperature Sensor Output•Single 3.3-V Supply
The ONET4291VA is a versatile high-speed multi-rate VCSEL driver for fiber optic applications with data rates upto 4.25 Gbps.
The device provides a 2-wire interface which allows digital control of the modulation and bias currents,eliminating the need for of external components.
The ONET4291VA includes an integrated automatic power control loop as well as circuitry to support laser safetyand transceiver management systems.
The part is available in a small footprint 4 mm ×4 mm 20-pin QFN package and it requires a single 3.3-V supply.
This power efficient multi-rate VCSEL driver is characterized for operation from –40 °C to 85 °C ambienttemperature.
A simplified block diagram of the ONET4291VA is shown in Figure 1 .
This compact, low power 1-Gbps to 4.25-Gbps multi-rate VCSEL driver consists of a high-speed currentmodulator, a modulation current generator, power-on reset circuitry, a 2-wire interface and control logic block, abias current generator and automatic power control loop, and an analog reference block.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DIN+
DIN−
Limiting
Gain Stage
GND
DOUT+
DOUT−
Power-On Reset
GND VCC
RESET
RESET
Modulation
Current
Generator
MODC IMOD
MODR
ENA
MODC MODR ENA
FLT
VCC
SCK
SDA
DIS
SCK
SDA
DIS
FLT
Bias Current Generator
and Automatic Power
Control Loop (APC)
BIAS
MONB
MONP
BIAS
MONB
MONP
MD
COMP
MD
COMP
RZTC
TS
RZTC
TS
2-Wire Interface and Control Logic Clock
FAULTPDPBIASCOLEENA
High-Speed Current Modulator
3
2
100 Ω
8
8
60 Ω60 Ω
8
FAULTPDPBIASCOLEENA
Analog Reference
B0072-01
ONET4291VA
SLLS674 – SEPTEMBER 2005
Figure 1. Simplified Block Diagram of the ONET4291VA
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HIGH-SPEED CURRENT MODULATOR
MODULATION CURRENT GENERATOR
2-WIRE SERIAL INTERFACE AND CONTROL LOGIC
ONET4291VA
SLLS674 – SEPTEMBER 2005
The data signal is applied to the high-speed current modulator by means of the input signal pins DIN+/DIN–,which provide on-chip differential 100- Ωline-termination. The succeeding limiting gain stage ensures sufficientdrive amplitude and edge-speed for driving the current modulator differential pair.
The modulation current is sunk from the common emitter node of the differential pair by means of a modulationcurrent generator, which is digitally controlled by the 2-wire interface and control logic block.
The collector nodes of the differential pair are connected to the output pins DOUT+/DOUT–, which includeon-chip 2 ×60- Ωback-termination to VCC. The 60- Ωback-termination helps to sufficiently suppress signaldistortion caused by double reflections for VCSEL diodes with impedances ranging from 50 Ωthrough 75 Ω.
The modulation current generator provides the current for the current modulator described above. The circuit isdigitally controlled by the 2-wire interface and control logic block.
An 8-bit wide control bus, MODC, is used to set the desired modulation current.
Furthermore, two modulation current ranges are selected by means of the MODR signal.
The ENA signal enables or disables the modulation current generator.
The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current isalso disabled in a fault condition if the fault detection enable register flag FLTEN is set.
For more information about the register functionality, see the register mapping description.
The ONET4291VA uses a 2-wire serial interface for digital control. A simplified block diagram of this interface isshown in Figure 2 .
The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from amicroprocessor, for example. Both inputs include 100-k Ωpullup resistors to VCC. For driving these inputs, anopen drain output is recommended.
A write cycle consists of a START command, three address bits with MSB first, eight data bits with MSB first,and a STOP command. In idle mode, both SDA and SCK lines are at a high level.
A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level.
Bits are clocked into an 11-bit wide shift register during the high level of the system clock SCK.
A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level.
At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected8-bit register. Register selection occurs according to the three address bits in the shift register, which aredecoded to eight independent select signals using a 3 to 8 decoder block.
In the ONET4291VA, only addresses 0 (000b) through 3 (011b) are used.
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Start/Stop
Detector
Logic
111
110
101
100
011
010
001
000
START
STOP
SDA
SCK
8 Bit Register
Control Functions (6 Bit)
Unused (2 Bit)
8
8
8 Bit Register
Modulation Current (8 Bit)
8
11 Bit Shift Register
8 Bits Data 3 Bits Addr
3 to 8 Decoder
3
B0068-02
8 Bit Register
Bias Current (8 Bit)
8
8 Bit Register
Unused (8 Bit)
8
ONET4291VA
SLLS674 – SEPTEMBER 2005
Figure 2. Simplified 2-Wire Interface Block Diagram
The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 3 .
The corresponding timing requirements are listed in Table 1 .
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START STOP1 0 1 0 1 1
SDA
SCK
DTAR
DTAF
STRTHLD
CLKR
CLKF
CLKHI
DTAHI
DTASTP
DTAWT
DTAHLD
STOPSTP
T0077-01
REGISTER MAPPING
ONET4291VA
SLLS674 – SEPTEMBER 2005
Figure 3. 2-Wire Interface Timing Diagram
Table 1. 2-Wire Interface Timing
PARAMETER DESCRIPTION MIN MAX UNIT
STRT
HLD
START hold time Time required from data falling edge to clock falling edge at START 10 ns
CLK
R
, DTA
R
Clock and data rise time Clock and data rise time 10 ns
CLK
F
, DTA
F
Clock and data fall time Clock and data fall time 10 ns
CLK
HI
Clock high time Minimum clock high period 50 ns
DTA
HI
Data high time Minimum data high period 100 ns
DTA
STP
Data setup time Minimum time from data rising edge to clock rising edge 10 ns
DTA
WT
Data wait time Minimum time from data falling edge to data rising edge 50 ns
DTA
HLD
Data hold time Minimum time from clock falling edge to data falling edge 10 ns
STOP
STP
STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns
The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 to Table 5 .Register 3 is included for future enhancements. It is not used in the current device.
Table 6 describes the circuit functionality based on the register settings.
Table 2. Register 0 (000b) Mapping
address 0 (000b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ENA PDP PDR OLE FLTEN MODR – –
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ONET4291VA
SLLS674 – SEPTEMBER 2005
Table 3. Register 1 (001b) Mapping
address 1 (001b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MODC7 MODC6 MODC5 MODC4 MODC3 MODC2 MODC1 MODC0
Table 4. Register 2 (010b) Mapping
address 2 (010b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2 BIASC1 BIASC0
Table 5. Register 3 (011b) Mapping
address 3 (011b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
––––––––
Table 6. Register Functionality
Symbol Register Function
ENA Enable Enables chip when set to 1. Can be toggled to reset a fault condition.
PDP Photodiode polarity Photodiode polarity bit:1 = common anode0 = common cathode
PDR Photodiode current range Photodiode current range bit:1 = 0 µA – 500 µA with 2- µA resolution0 = 0 µA – 250 µA with 1- µA resolution
OLE Open loop enable Open loop enable bit:1 = open loop bias current control0 = closed loop bias current control
FLTEN Fault detection enable Fault detection enable bit:1 = fault detection on0 = fault detection off
MODR Modulation current range Laser modulation current range:1 = 0 mA – 15 mA0 = 0 mA – 12 mA
MODC7 Modulation current bit 7 (MSB) Modulation current setting:
MODC6 Modulation current bit 6
MODC5 Modulation current bit 5 MODR = 1 (see above):
MODC4 Modulation current bit 4 Modulation current: 100 µA – 15.4 mA with 68 µA step size
MODC3 Modulation current bit 3
MODC2 Modulation current bit 2 MODR = 0 (see above):
MODC1 Modulation current bit 1 Modulation current: 100 µA – 12 mA with 51 µA step size
MODC0 Modulation current bit 0 (LSB)
BIASC7 Bias current bit 7 (MSB) closed loop (APC):
BIASC6 Bias current bit 6 Coupling ratio CR between VCSEL bias current and photodiode current is:
BIASC5 Bias current bit 5 CR = I
BIAS-VCSEL
/ I
PD
BIASC4 Bias current bit 4 PDR = 0 (see above), BIASC = 0 .. 255, I
BIAS-VCSEL
≤12 mA:
BIASC3 Bias current bit 3 I
BIAS-VCSEL
= 100 µA + (1 µA×CR ×BIASC)
BIASC2 Bias current bit 2 PDR = 1 (see above), BIASC = 0 .. 255, I
BIAS-VCSEL
≤12 mA:
BIASC1 Bias current bit 1 I
BIAS-VCSEL
= 100 µA + (2 µA×CR ×BIASC)
BIASC0 Bias current bit 0 (LSB) open loop: I
BIAS-VCSEL
= 100 µA + (47 µA×BIASC)
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BIAS CURRENT GENERATION AND APC LOOP
ANALOG REFERENCE
POWER-ON RESET AND REGISTER LOADING SEQUENCE
LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
ONET4291VA
SLLS674 – SEPTEMBER 2005
The bias current generation and APC loop are controlled by means of the 2-wire interface.
In open loop operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bitwide control word BIASC[0..7] (register 2).
In automatic power control mode, selected by setting OLE = 0, the bias current depends on the register settingsBIASC[0..7] and the coupling ratio (CR) between the VCSEL bias current and the photodiode current.CR = I
BIAS-VCSEL
/ I
PD
.
Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). Thephotodiode range should be chosen to keep the laser bias control DAC close to the center of its range. Thiskeeps the laser bias current setpoint resolution high and the loop settling time constant within specification.
For details regarding the bias current setting in open loop as well as in closed loop mode, see Table 6 .
In closed loop mode, the photodiode polarity bit, PDP, must be set for common anode or common cathodeconfiguration to ensure proper operation. In open loop mode if a photodiode is still present, the photodiodepolarity bit must be set to the opposite setting.
The ONET4291VA is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This voltage isreferenced to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from whichall other internally required voltages and bias currents are derived.
An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground(GND). This resistor is used to generate a precise zero TC current which is used as a reference current for theon-chip DACs.
In order to minimize the module component count, the ONET4291VA VCSEL driver provides an on-chiptemperature sensor. The output voltage of the temperature sensor is available at the TS pin.
The voltage is V
TS
= 9.4 mV ×TEMP + 1337 mV with TEMP given in °C.
Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.
The ONET4291VA has power on reset circuitry which ensures that all registers are reset to zero during startup.After the power-on to initialize time (T
INIT1
), the internal registers are ready to be loaded. It is important that theregisters are loaded in the following order:
1. Bias current register (register 2, 010b),
2. Modulation current register (register 1, 001b),
3. Control register (register 0, 000b).
The part will be ready to transmit data after the initialize to transmit time T
INIT2
, assuming that the control registerenable bit ENA is 1 and the disable pin DIS is low.
The ONET4291VA can be disabled using either the ENA control register bit or the disable pin DIS. In both casesthe internal registers are not reset. After the disable pin DIS is de-asserted and/or the enable bit ENA isre-asserted the part returns to its prior output settings.
The ONET4291VA provides built in laser safety features. The following fault conditions are detected:
1. Voltage at MONB exceeds 1.2 V,
2. Photodiode current exceeds 150% of its target value,
3. Bias control DAC drops in value by more than 33% in one step.
If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET4192VA responds by:
1. Setting the VCSEL bias current to zero.
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PACKAGE
GND
MOD
MOD+
GND
BIAS
DIS
RZTC
TS
SCK
SDA
VCC
DIN+
DIN−
VCC
FLT
RGP PACKAGE
(TOP VIEW)
20
19
18
17
16
6
7
8
9
10
PD
VCC
CAPC
MONP
MONB
P0031-01
15
14
13
12
11
1
2
3
4
5
EP
ONET4291VA
SLLS674 – SEPTEMBER 2005
2. Setting the modulation current to zero.
3. Asserting and latching the FLT pin.
Fault recovery is performed by the following procedure:
1. The disable pin DIS and/or the enable control bit ENA are toggled for at least the fault latch reset timeT
RESET
.
2. The FLT pin de-asserts while the disable pin DIS is asserted or the enable bit ENA is de-asserted.
3. If the fault condition is no longer present, the part will return to normal operation with its prior output settingsafter the disable negate time T
ON
.
4. If the fault condition is still present, FLT re-asserts once DIS is set to low level and the part will not return tonormal operation.
For the ONET4291VA, a small footprint 4 mm ×4 mm 20-pin QFN package with a lead pitch of 0,5 mm is used.The pin out is shown in Figure 4 .
Figure 4. Pinout of ONET4291VA in a 4 mm ×4 mm 20-Pin QFN Package
TERMINAL FUNCTIONS
TERMINAL
TYPE DESCRIPTIONNO. NAME
1 DIS CMOS-in Disables both bias and modulation current when set to high state. Toggle to reset a faultcondition
2 RZTC Analog Connect external zero TC 30-k Ωto ground (GND). Used to generate a defined zero TC referencecurrent for internal DACs.
3 TS Analog-out Temperature sensor output. Not buffered, capacitive load only.
4 SCK CMOS-in 2-wire interface serial clock. Includes a 100-k Ωpullup resistor to VCC.
5 SDA CMOS-in 2-wire interface serial data input. Includes a 100-k Ωpullup resistor to VCC.
6, 9, 14 VCC Supply 3.3-V ±10% supply voltage
7 DIN+ Analog-in Non-inverted data input. On-chip differentially 100- Ωterminated to DIN–. Must be ac coupled.
8 DIN– Analog-in Inverted data input. On-chip differentially 100- Ωterminated to DIN+. Must be ac coupled.
10 FLT CMOS-out Fault detection flag
11 MONB Analog-out Bias current monitor. Sources an 8.3% replica of the bias current. Connect an external resistor toground (GND). If the voltage at this pin exceeds 1.2 V a fault is triggered.
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ONET4291VA
SLLS674 – SEPTEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
TYPE DESCRIPTIONNO. NAME
12 MONP Analog-out Photodiode current monitor. Sources a 50% replica of the photodiode current. Connect anexternal resistor to ground (GND).
13 CAPC Analog Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01- µF capacitor toground.
15 PD Analog Monitor photodiode input. The pin can source or sink current dependent on PDP register setting.Pin supplies >1.5-V reverse bias.
16 BIAS Analog VCSEL diode bias current source. Connect to laser anode through inductor. MurataBLM15HG102SN1 is recommended.
17, 20, EP GND Supply Circuit ground. The exposed die pad (EP) must be grounded.
18 MOD+ CML-out Non-inverted modulation current output. AC coupled to anode of common cathode VCSEL.On-chip 60- Ωback-terminated to VCC.
19 MOD– CML-out Inverted modulation current output. AC coupled through VCSEL matching resistor to ground(GND). On-chip 60- Ωback-terminated to VCC.
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
V
CC
Supply voltage –0.3 V to 4 V
V
DIS
, V
RZTC
, V
TS
, V
SCK
, V
SDA
, V
DIN+
, Voltage at DIS, RZTC, TS, SCK, SDA, DIN+, DIN–, FLT, MONB, MONP, –0.3 V to 4 VV
DIN–
, V
FLT
, V
MONB,
V
MONP
, V
CAPC
, CAPC, PD, BIAS, MOD+, MOD–
(2)
V
PD
, V
BIAS
, V
MOD+
, V
MOD–
ESD ESD rating at all pins 3 kV (HBM)
T
J,max
Maximum junction temperature 125 °C
T
STG
Storage temperature range –65 °C to 85 °C
T
A
Characterized free-air operating temperature range –40 °C to 85 °C
T
LEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
PARAMETER CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.9 3.3 3.6 V
V
IH
CMOS input high voltage DIS, SCK, SDA 2 V
V
IL
CMOS input low voltage DIS, SCK, SDA 0.8 V
Bias output headroom voltage V
CC
– V
BIAS
, I
BIAS
= 10 mA 500 mV
Control bit PDR = 1, step size = 2 µA 10 500Photodiode current range µAControl bit PDR = 0, step size = 1 µA 5 250
R
RZTC
Zero TC resistor value
(1)
1.22-V bias across resistor 29.7 30 30.3 k Ω
V
IN
Differential input voltage swing 200 800 2400 mVp-p
20%–80%, f
BIT
= 1.25 Gbps 160t
R-IN
Input rise time ps20%–80%, f
BIT
≥2.125 Gbps 100
20%–80%, f
BIT
= 1.25 Gbps 160t
F-IN
Input fall time ps20%–80%, f
BIT
≥2.125 Gbps 100
T
A
Operating free-air temperature –40 85 °C
(1) Changing the value alters DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
ONET4291VA
SLLS674 – SEPTEMBER 2005
over recommended operating conditions, all values are for open loop operation, I
MOD
= 6 mA,I
BIAS
= 5 mA, and R
RZTC
= 30 k Ω, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.9 3.3 3.6 V
I
MOD
= 6 mA, I
BIAS
= 5 mA, including I
MOD
and I
BIAS
40 45I
VCC
Supply current mADisabled, DIS = high and/or control bit ENA = low 22
R
IN
Data input/output resistance Differential between DIN+/DIN– 85 100 115 Ω
R
OUT
Data output/output resistance Single-ended to VCC 50 60 70 Ω
CMOS input current SCK, SDA, 100-k Ωpullup to VCC –50 10 µA
CMOS input current DIS –10 10 µA
V
OH
CMOS output high voltage FLT, I
SINK
= 1 mA 2.5 V
V
OL
CMOS output low voltage FLT, I
SOURCE
= 1 mA 0.5 V
I
BIAS-DIS
Bias current during disable 100 µA
I
BIAS-MIN
Minimum bias current See
(1)
0.2 mA
I
BIAS-MAX
Maximum bias current DAC set to maximum, closed loop 8.5
mADAC set to maximum, open loop 11
V
PD
Photodiode reverse bias voltage APC active, I
PD
= max 1.5 2.1 V
Photodiode fault current level Percent of target I
PD
(2)
150%
V
TS
Temperature sensor voltage range –40 °C to 120 °C junction temperature. Capacitive load 0.8 2.5 Vonly. After mid-scale calibration.
Temperature sensor accuracy Mid scale calibration ±3°C
I
TS
Temperature sensor drive current Source or sink
(2)
–10 10 µA
Photodiode current monitor ratio I
MONP
/ I
PD
, I
BIAS
> 100 µA 45% 60% 80%
Bias current monitor ratio I
MONB
/ I
BIAS
(nominal 1/12 = 8.3%) 6.7% 8.3% 10%
V
CC-RST
V
CC
reset threshold voltage VCC voltage level which triggers power-on reset 2.4 2.6 2.85 V
V
CC-
VCC reset threshold voltage 120 mV
RSTHYS
hysteresis
V
MONB-FLT
Fault voltage at MONB Fault occurs if voltage at MONB exceeds value 1.05 1.2 1.45 V
(1) The bias current can be set below the specified minimum according to the corresponding register setting described in the registermapping section above, however in closed loop operation settings below the specified value may trigger a fault.(2) Assured by simulation over process, supply, and temperature variation.
over recommended operating conditions with 50- Ωoutput load, open loop operation, I
MOD
= 6 mA, I
BIAS
= 5 mA, andR
RZTC
= 30 k Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
20%–80%, t
R-IN
= 160 ps, single-ended V
IN
> 400 mV
pp
60 125t
R-OUT
Output rise time ps20%–80%, t
R-IN
= 100 ps, single-ended V
IN
> 400 mV
pp
35 100
20%–80%, t
F-IN
= 160 ps, single-ended V
IN
> 400 mV
pp
60 125t
F-OUT
Output fall time ps20%–80%, t
F-IN
= 100 ps, single-ended V
IN
> 400 mV
pp
35 100
Control bit MODR = 1, 50- Ωload 11.5I
MOD-MAX
Maximum modulation current mAControl bit MODR = 0, 50- Ωload 9
Control bit MODR = 1, 50- Ωload 68I
MOD-STEP
Modulation current step size µAControl bit MODR = 0, 50- Ωload 51
DJ Deterministic output jitter f
BIT
= 4.25 Gbps, excluding DJ caused by duty cycle 7 20 ps
p-pdistortion
DCD Duty cycle distortion f
BIT
= 4.25 Gbps 8 ps
p-p
(1) Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C.
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ONET4291VA
SLLS674 – SEPTEMBER 2005
AC ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions with 50- Ωoutput load, open loop operation, I
MOD
= 6 mA, I
BIAS
= 5 mA, andR
RZTC
= 30 k Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
τ
APC
APC time constant C
APC
0.01 µF, I
PD
= 100 µA, PD coupling ratio 200 µsCR = 1/40
(2)
T
OFF
Transmitter disable time Rising edge of DIS to I
BIAS
≤0.1 x I
BIAS-NOMINAL
(2)
2.4 5 µs
T
ON
Disable negate time Falling edge of DIS to I
BIAS
≥0.9 x I
BIAS-NOMINAL
(2)
1 ms
T
INIT1
Power-on to initialize Power-on to registers ready to be loaded 20 250 ms
T
INIT2
Initialize to transmit Register load STOP command to part ready to transmit 2 msvalid data
(2)
T
RESET
DIS pulse width Time DIS must held high to reset part
(2)
100 ns
T
FAULT
Fault assert time Time from fault condition to FLT high
(2)
50 µs
(2) Assured by simulation over process, supply, and temperature variation.
11
*9 TEXAS Modulation Currem — mA EDD} 1A — Free-Air Tempemure — c INSTRUMENTS www.|l.cnm 1.0 IE 0.9 ‘4 E 0.0 .‘ 5 ‘2 § 0.7 g ‘5 ‘ 10 o 0.6 8 3 E - -. E 0.5 a 3 /\ a -= \ E .2 4. 0.4 .5 \\ .0 E a a: ._ . 0.3 2 \\ :2: 3 4 e 02 _= . 0.1 2 0.0 0 4 a s 10 12 Bias Currenl — mA 530‘ 3.0 2.5 E "T 2.0 a. \ l i 1.5 _, E a E g 1.0 0.5 0.0 0.0 0 4 s 3 10 12 14 IS —40 >20 0 20 40 50 00 10
www.ti.com
TYPICAL CHARACTERISTICS
Bias Current − mA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 10 12
IMONB − Bias-Monitor Current − mA
G001
ONET4291VA
SLLS674 – SEPTEMBER 2005
Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C (unless otherwise noted)
BIAS-MONITOR CURRENT I
MONB
DETERMINISTIC JITTERvs vsBIAS CURRENT MODULATION CURRENT
Figure 5. Figure 6.
RANDOM JITTER RANDOM JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 7. Figure 8.
12
*9 TEXAS INSTRUMENTS www.ll.cnm 14 12 4 / E It) . /\ // g l / 5 3 m .E m a. a a _. = o a. / o 0 2 4 6 8 1D 12 W Bias Current Regisler Setting — mA 50 45 E 40 . E e 5 35 U 2‘ E : 30 m 25 20 -40 >20 0 20 4D 60 an In 1A — Free-Air Tempemure — “c Enu‘ Em
www.ti.com
Modulation Current Register Setting − mA
0
2
4
6
8
10
12
14
16
0 2 4 6 8 10 12 14 16
Modulation Current − mA
G007
ONET4291VA
SLLS674 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C (unless otherwise noted)
RISE-TIME AND FALL-TIME BIAS CURRENT IN OPEN LOOP MODEvs vsMODULATION CURRENT BASIC REGISTER SETTING
Figure 9. Figure 10.
MODULATION CURRENT SUPPLY CURRENTvs vsMODC REGISTER SETTING TEMPERATURE
Figure 11. Figure 12.
13
*9 TEXAS INSTRUMENTS www.u.nom Guns 13ml
www.ti.com
G009
Single-Ended Output Voltage − 60 mV/Div
t − Time − 40 ps/Div
G010
Single-Ended Output Voltage − 100 mV/Div
t − Time − 40 ps/Div
G011
Single-Ended Output Voltage − 150 mV/Div
t − Time − 40 ps/Div
G012
Single-Ended Output Voltage − 150 mV/Div
t − Time − 157 ps/Div
ONET4291VA
SLLS674 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C (unless otherwise noted)
EYE-DIAGRAM AT 4.25 GBPS EYE-DIAGRAM AT 4.25 GBPSK28.5 PATTERN, I
MOD
= 5 mA K28.5 PATTERN, I
MOD
= 10 mA
Figure 13. Figure 14.
EYE-DIAGRAM AT 4.25 GBPS EYE-DIAGRAM AT 1.0625 GBPSK28.5 PATTERN, I
MOD
= 15 mA K28.5 PATTERN, I
MOD
= 15 mA
Figure 15. Figure 16.
14
*9 TEXAS INSTRUMENTS www.|l.com DIN+ E>—{ }7 DIN— D—Jii onenzsu VA D'N‘ ZD-Lead om MOD‘ ' ’7 0.1 HF 0.1 HF 7%. U VCSEL BLMI5HG102$NI Lase'dme \ \‘ vcc D a K Monilar l Phutudinde F M o M RMONP m k9
www.ti.com
APPLICATION INFORMATION
DIN+
DIN−
VCC
DIS
MONP
SDA
TS
MONB
VCSEL
Laserdiode
Monitor
Photodiode
C3
0.1 µF
FLT
SDK
DIN+
DIN− MOD+
MOD−
BIAS
GND
VCC
VCC
FLT
ONET4291VA
20-Lead QFN
GND
MONP
CAPC
MONB
VCC
PD
TS
SCK
DIS
SDA
RZTC
50 Ω
L1
BLM15HG102SN1
C4
0.1 µF
RZTC
RMONB
1 kΩ
RMONP
10 kΩC5
0.01 µF
C1
0.1 µF
C2
0.1 µF
S0100-01
30 kΩ
ONET4291VA
SLLS674 – SEPTEMBER 2005
Figure 17 shows a typical application circuit using the ONET4291VA with a common cathode VCSEL connectedto ground.
The VCSEL driver is controlled via the 2-wire interface SDA/SCK by a microprocessor.
In a typical application, the FLT, MONB, MONP, and TS outputs are connected to the microcontroller fortransceiver management purposes.
The component values in Figure 17 are typical examples and may be varied according to the intendedapplication.
Figure 17. Basic Application Circuit With a Common Cathode VCSEL
15
‘5‘ TEXAS INSTRUMENTS rwww 7 fl rdiflwjljljlfl u n 1“ w \ UT J Ii E 7k «J 7! 7 ccgc: XL fl W m 7 m4 7 a J i‘lfww 5 g 7 a U 7 H W RM 7 fl 7 35335 F H 7 71 7 7 maTDL www.ti.com
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
PACKAGE OUTLINE
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RGP0020D
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
PIN 1 INDEX AREA
4.1
3.9
4.1
3.9
1 MAX
0.05
0.00 2.8
2.6
2
2
16X 0.5
(0.2) TYP
PIN 1 IDENTIFICATION
(OPTIONAL)
LEAD DETAIL "A"
(0.1) TYP
LEAD DETAIL "A"
OPTION
20X 0.5
0.3
1
5
610
11
15
16
20
20X 0.30
0.18
SYMM
SEATING PLANE
C
21
17
ONET4291VA
www.ti.com
SLLS674 –SEPTEMBER 2005
Product Folder Links: ONET4291VA
Submit Documentation FeedbackCopyright © 2005, Texas Instruments Incorporated
IN .ti.com
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
RGP0020D
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
( 2.7)
(2)
(3.8)
(2) (3.8)
(1.1)
(1.1)
20X (0.6)
20X (0.24)
16X (0.5)
(R0.05) TYP
(Ø0.2) VIA
TYP
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
5
1
20 16
15
11
10
6
21
18
ONET4291VA
SLLS674 –SEPTEMBER 2005
www.ti.com
Product Folder Links: ONET4291VA
Submit Documentation Feedback Copyright © 2005, Texas Instruments Incorporated
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
EXAMPLE STENCIL DESIGN
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
RGP0020D
PLASTIC QUAD FLATPACK- NO LEAD
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED COVERAGE BY AREA
SCALE: 20X
SYMM
SYMM
4X ( 1.19)
(2)
(3.8)
(2) (3.8)
(0.695)
(0.695)
20X (0.6)
20X (0.24)
16X (0.5)
(R0.05) TYP
5
1
20 16
15
11
10
6METAL
TYP
21
19
ONET4291VA
www.ti.com
SLLS674 –SEPTEMBER 2005
Product Folder Links: ONET4291VA
Submit Documentation FeedbackCopyright © 2005, Texas Instruments Incorporated
I TEXAS INSTRUMENTS Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ONET4291VARGPR ACTIVE QFN RGP 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ONET
4291V
ONET4291VARGPT ACTIVE QFN RGP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ONET
4291V
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET4291VARGPR QFN RGP 20 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ONET4291VARGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET4291VARGPR QFN RGP 20 2500 356.0 356.0 35.0
ONET4291VARGPT QFN RGP 20 250 210.0 185.0 35.0
Pack Materials-Page 2
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