Fiche technique pour BQ24001,2,3 de Texas Instruments

*9 TEXAS INSTRUMENTS SINGLE-CELL Li-ION AND
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
FEATURES
DHighly Integrated Solution With FET Pass
Transistor and Reverse-Blocking Schottky
and Thermal Protection
DIntegrated Voltage and Current Regulation
With Programmable Charge Current
DHigh-Accuracy Voltage Regulation (±1%)
DIdeal for Low-Dropout Linear Charger
Designs for Single-Cell Li-Ion Packs With
Coke or Graphite Anodes
DUp to 1.2-A Continuous Charge Current
DSafety-Charge Timer During Preconditioning
and Fast Charge
DIntegrated Cell Conditioning for Reviving
Deeply Discharged Cells and Minimizing Heat
Dissipation During Initial Stage of Charge
DOptional Temperature or Input-Power
Monitoring Before and During Charge
DVarious Charge-Status Output Options for
Driving Single, Double, or Bicolor LEDs or
Host-Processor Interface
DCharge Termination by Minimum Current and
Time
DLow-Power Sleep Mode
DPackaging: 5 mm × 5 mm MLP or 20-Lead
TSSOP PowerPAD
APPLICATIONS
DPDAs
DInternet Appliances
DMP3 Players
DDigital Cameras
DESCRIPTION
The bq2400x series ICs are advanced Li-Ion linear
charge management devices for highly integrated and
space-limited applications. They combine high-
accuracy current and voltage regulation; FET pass-
transistor and reverse-blocking Schottky; battery
conditioning, temperature, or input-power monitoring;
charge termination; charge-status indication; and
charge timer in a small package.
The bq2400x measures battery temperature using an
external thermistor. For safety reasons, the bq2400x
inhibits charge until the battery temperature is within the
user-defined thresholds. Alternatively, the user can
monitor the input voltage to qualify charge. The
bq2400x series then charge the battery in three phases:
preconditioning, constant current, and constant
voltage. If the battery voltage is below the internal
low-voltage threshold, the bq2400x uses low-current
precharge to condition the battery. A preconditioning
timer is provided for additional safety. Following pre-
conditioning, the bq2400x applies a constant-charge
current to the battery. An external sense-resistor sets
the magnitude of the current. The constant-current
phase is maintained until the battery reaches the
charge-regulation voltage. The bq2400x then
transitions to the constant voltage phase. The user can
configure the device for cells with either coke or
graphite anodes. The accuracy of the voltage regulation
is better than ±1% over the operating junction
temperature and supply voltage range.
Charge is terminated by maximum time or minimum
taper current detection
The bq2400x automatically restarts the charge if the
battery voltage falls below an internal recharge
threshold.
PowerPAD is a trademark of Texas Instruments.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002 − 2004, Texas Instruments Incorporated
*9 TEXAS INSTRUMENTS Am 740‘5 to (ZSCC Operamg Juncmn temperature range TJ
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
CHARGE STATUS
TJ20-LEAD HTTSOP PowerPAD
(PWP)(1) 20-LEAD 5 mm × 5 mm MLP
(RGW)(2)
CHARGE STATUS
CONFIGURATION
bq24001PWP bq24001RGW Single LED
−40°C to 125°Cbq24002PWP bq24002RGW 2 LEDs
−40 C to 125 C
bq24003PWP bq24003RGW Single bicolor LED
(1) The PWP package is available taped and reeled. Add R suffix to device type (e.g. bq24001PWPR) to order. Quantities 2500 devices per reel.
(2) The RGW package is available taped and reeled. Add R suffix to device type (e.g. bq24001RGWR) to order. Quantities 3000 devices per reel.
PACKAGE DISSIPATION RATINGS
PACKAGE ΘJA ΘJC TA 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°C
PWP(1) 30.88°C/W 1.19°C/W 3.238 W 0.0324W/°C
RGW(2) 31.41°C/W 1.25°C/W 3.183 W 0.0318W/°C
(1) This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (6.5 × 3.4 mm), internal 1 oz power and
ground planes, 8 thermal via underneath the die connecting to ground plane.
(2) This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (3.25 × 3.25 mm), internal 1 oz power
and ground planes, 9 thermal via underneath the die connecting to ground plane.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq24001
bq24002
bq24003
Supply voltage (Vcc with respect to GND) 13.5 V
Input voltage (IN, ISNS, EN, APG/THERM/CR/STAT1/STAT2, VSENSE, TMR SEL, VSEL) (all with respect to GND) 13.5 V
Output current (OUT pins) 2 A
Output sink/source current (STAT1 and STAT2) 10 mA
Operating free-air temperature range, TA−40°C to 70°C
Storage temperature range, Tstg −65°C to 150°C
Junction temperature range, TJ−40°C to 125°C
Lead temperature (Soldering, 10 sec) 300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Supply voltage, VCC 4.5 10 V
Input voltage, VIN 4.5 10 V
Continuous output current 1.2 A
Operating junction temperature range, TJ−40 125 °C
*5 TEXAS INSTRUM ENTS Standby current {sum of currems mlo OUT VOLTAGE REGULATION, 0“C 5 TJ ‘0 : 1,2 A, VouT+VDo meMAX
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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3
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature supply and input voltages, and VI (VCC)VI (IN) ( unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC current VCC > VCC_UVLO, EN VIH(EN) 1 mA
VCC current, standby mode EN VIL(EN) 1µA
IN current, standby mode EN VIL(EN) 10 µA
Standby current (sum of currents into OUT
and VSENSE pins)
VCC < VCC_UVLO, VOUT = 4.3 V, VSENSE = 4.3V 2 4
µA
Standby current (sum of currents into OUT
and VSENSE pins) EN <= VilEN, VOUT = 4.3 V, VSENSE = 4.3 V 2 4 µ
A
VOLTAGE REGULATION, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage
VSEL = VSS,0 < IO 1.2 A 4.059 4.10 4.141 V
Output voltage
VSEL = VCC,0 < IO 1.2 A 4.158 4.20 4.242 V
Load regulation 1 mA IO 1.2 A,
VCC =5 V, VI(IN)= 5 V,
TJ = 25°C1 mV
Line regulation VOUT+VDO+Vilim(MAX) < VI(VCC) < 10 V, TJ = 25°C 0.01 %/V
Dropout voltage = VI(IN)-Vout
IO = 1.0 A, 4.9 V <VI(Vcc)< 10 V 0.7 V
Dropout voltage = VI(IN)-Vout
IO = 1.2 A, VOUT+VDO+VilimMAX <VI(VCC)< 10 V 0.8 V
CURRENT REGULATION, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current regulation threshold, VI(limit) VSENSE < VO(VSEL-LOW/HIGH) 0.095 0.1 0.105 V
Delay time VSENSE pulsed above VVLOWV to IO = 10% of
regulated value(1) 1 ms
Rise time IO increasing from 10% to 90% of regulated value.
RSNS 0.2 Ω, (1) 0.1 1 ms
(1) Specified by design, not production tested.
CURRENT SENSE RESISTOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
External current sense resistor range (RSNS)100 mA Ilim 1.2 A 0.083 1
PRECHARGE CURRENT REGULATION, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Precharge current regulation VSENSE<VLOWV, 0.083 RSNS 1.0 40 60 80 mA
VCC UVLO COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold 4.35 4.43 4.50 V
Stop threshold 4.25 4.33 4.40 V
Hysteresis 50 mV
APG/THERM COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Upper trip threshold 1.480 1.498 1.515 V
Lower trip threshold 0.545 0.558 0.570 V
Input bias current 1µA
LOWV COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold 2.80 2.90 3.00 V
Stop threshold 3.00 3.10 3.20 V
Hysteresis 100 mV
*9 TEXAS INSTRUMENTS
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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4
ELECTRICAL CHARACTERISTICS CONTINUED
over recommended operating junction temperature supply and input voltages, and VI (VCC)VI (IN) ( unless otherwise noted)
HIGHV (RECHARGE) COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold 3.80 3.90 4.00 V
OVERV COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold 4.35 4.45 4.55 V
Stop threshold 4.25 4.30 4.35 V
Hysteresis 50 mV
TAPERDET COMPARATOR, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Trip threshold 12 18.5 25 mV
EN LOGIC INPUT, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage 2.25 V
Low-level input voltage 0.8 V
Input pulldown resistance 100 200 k
VSEL LOGIC INPUT, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage 2.25 V
Low-level input voltage 0.8 V
Input pulldown resistance 100 200 k
TMR SEL INPUT 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage 2.7 V
Low-level input voltage 0.6 V
Input bias current VI(TMR SEL) 5V 15 µA
STAT1, STAT2 (bq24001, bq24003), 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output (low) saturation voltage IO = 10 mA 1.5 V
Output (low) saturation voltage IO = 4 mA 0.6 V
Output (high) saturation voltage IO = −10 mA VCC−1.5 V
Output (high) saturation voltage IO = −4 mA VCC−0.5 V
Output turn on/off time IO = ± 10 mA, C = 100 p(1) 100 µs
(1) Assured by design, not production tested.
POWER-ON RESET (POR), 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POR delay See Note 1 1.2 3 ms
POR falling-edge deglitch See Note 1 25 75 µs
(1) Assured by design, not production tested.
*5 TEXAS INSTRUM ENTS c g T J vac VSENSE \SNS AGND N/C N/C APG/THERM STAT1 EN TMR SEL VSEL CR GND/HEATS‘NK N/C
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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5
ELECTRICAL CHARACTERISTICS CONTINUED
over recommended operating junction temperature supply and input voltages, and VI (VCC)VI (IN) ( unless otherwise noted)
APG/THERM DELAY, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
APG/THERM falling-edge deglitch See Note 1 25 75 µs
(1) Assured by design, not production tested.
TIMERS, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
User-selectable timer accuracy
TA = 25°C −15% 15%
User-selectable timer accuracy
−20% 20%
Precharge and taper timer 22.5 minute
THERMAL SHUTDOWN, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Thermal trip See Note 1 165 °C
Thermal hysteresis See Note 1 10 °C
(1) Assured by design, not production tested.
CR PIN, 0°C TJ 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage 0 < IO(CR) < 100 µA 2,816 2.85 2.88 V
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
IN
IN
VCC
ISNS
N/C
APG/THERM
EN
VSEL
GND/HEATSINK
N/C
OUT
OUT
VSENSE
AGND
N/C
STAT1
TMR SEL
CR
N/C
bq24001
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
IN
IN
VCC
ISNS
N/C
APG/THERM
EN
VSEL
GND/HEATSINK
N/C
OUT
OUT
VSENS
E
AGND
STAT2
STAT1
TMR SE
L
CR
N/C
bq24002, bq24003
PWP PACKAGE
(TOP VIEW)
N/C − Do not connect
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6
20
19
18
17
16
6
7
8
9
10
N/C − Do Not Connect
EN
VSEL
GND
CR
N/C
N/C
N/C
N/C
OUT
OUT
11
12
13
14
15
5
4
3
2
1
TMR SEL
STAT1
N/C
AGND
VSENSE
bq24001
RGW PACKAGE
(TOP VIEW)
APG/THERM
ISNS
VCC
IN
IN
bq24002, bq24003
RGW PACKAGE
(TOP VIEW)
20
19
18
17
16
6
7
8
9
10
EN
VSEL
GND
CR
N/C
N/C
N/C
N/C
OUT
OUT
11
12
13
14
15
5
4
3
2
1
TMR SEL
STAT1
STAT2
AGND
VSENSE
APG/THERM
ISNS
VCC
IN
IN
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. NO.
I/O
DESCRIPTION
AGND 16 14 Ground pin; connect close to the negative battery terminal.
APG/THERM 7 5 I Adapter power good input/thermistor sense input
CR 12 9 I Internal regulator bypass capacitor
EN 8 6 I Charge-enable input. Active-high enable input with internal pull down. Low-current stand-by mode
active when EN is low.
GND/HEATSINK 10 8 Ground pin; connect to PowerPAD heat-sink layout pattern.
IN 2, 3 1, 2 IInput voltage. This input provides the charging voltage for the battery.
ISNS 5 4 I Current sense input
N/C 1, 6, 11,
15, 20 10, 13,
18−20 No connect. These pins must be left floating. Pin 15 is N/C on bq24001PWP only. Pin 13 is N/C on
bq24001RGW only.
OUT 18, 19 16, 17 OCharge current output
STAT1 14 12 O Status display output 1
STAT2 15 13 O Status display output 2 (for bq24002 and bq24003 only)
TMR SEL 13 11 ICharge timer selection input
VCC 4 3 I Supply voltage
VSEL 9 7 I 4.1 V or 4.2 V charge regulation selection input
VSENSE 17 15 I Battery voltage sense input
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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7
FUNCTIONAL BLOCK DIAGRAM
+
Charge Control, Charge Timer
and
Display Logic
OSC VCC
VCC
STAT1
STAT2
TaperDet
REG
PWRDWN
CR
ChargeOK
PWRDWN
UVS
Thermal
Shutdown
T
MR SEL
+
+
Power On
Delay
CLRFLTAPG/
THERM
R9
Precharge
Bias and
Ref
Generator
Vref Vuvlo
H: Vreg = 4.2 V/Cell
L: Vreg = 4.1 V/Cell
VSEL
EN
R8
ChipEN
UVS
Vuvlo
+
ChargeOK
LowV
+
Vilim
VCC
ISNS
+TaperDet
IN
Vref AGND
VSENSE
OUT
GND/
HEATSINK
+
OverV
+
HighV
+
LowV
Vref
PWRDWN
Two Ope
n
Drain
Outputs
for
bq24002
0.2*Vilim
if} TEXAS v0 — ompu1VoI1age — v INSTRUMENTS 4.24 1 4.24 ‘ VIN = 5 V V." : 5 v 4.22 , TA = 25°C 4.22 VSEL = Vcc 4.20 4.20 > > ' 4.13 ‘ 4.13 3 3 g E >9 4.16 >5 4.16 s 3. 4.14 g 4.14 = = O O ' 4.12 ‘ 4.12 O O > VSEL = Vss > 4.10 4.10 4.03 4.00 4.05 4.06 0 200 400 500 300 1000 1200 _50 0 50 100 15 1° — 0u1pu1 Currenl — mA TJ — Juncfion Temperalure — °c Figure 1 Figure 2 4.24 103 |o=|00mA Io:1DflmA 4.22 , TA = 25°C TA = 2510 VSEL = Vcc 102 4.20 > E 4.13 ; 101 a / 4.16 i / Z 100 4.14 m 5 / 4.12 g 99 4.10 8 03 4.03 4.06 97 5 6 7 a 9 10 5 6 7 a 9 10 v. — Input Voltage » v v. — Inpul Voltage » v Figure 3 Figure 4
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TYPICAL CHARACTERISTICS
Figure 1
IO − Output Current − mA
4.06
4.08
4.10
4.12
4.14
4.16
4.18
4.20
4.22
4.24
0 200 400 600 800 1000 1200
VIN = 5 V
TA = 25°C
O
vs
OUTPUT CURRENT
VSEL = VSS
VSEL = VCC
Figure 2
TJ − Junction Temperature − °C
4.06
4.08
4.10
4.12
4.14
4.16
4.18
4.20
4.22
4.24
−50 0 50 100 150
VIN = 5 V
VO − Output Voltage − V
vs
JUNCTION TEMPERATURE
VSEL = VSS
VSEL = VCC
Figure 3
VI − Input Voltage − V
4.06
4.08
4.10
4.12
4.14
4.16
4.18
4.20
4.22
4.24
5678910
IO = 100 mA
TA = 25°C
O
vs
INPUT VOLTAGE
VSEL = VSS
VSEL = VCC
Figure 4
VI − Input Voltage − V
97
98
99
100
101
102
103
5678910
IO = 100 mA
TA = 25°C
vs
INPUT VOLTAGE
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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TYPICAL CHARACTERISTICS
Figure 5
TJ − Junction Temperature − °C
98
99
100
101
102
103
−50 0 50 100 150
vs
JUNCTION TEMPERATURE
VCC = 10 V
VCC = 5 V
IO = 100 mA
TA = 25°C
Figure 6
VI − Input Voltage − V
0.0
0.1
0.2
0.3
0.4
0.5
5678910
TA = 25°C
vs
INPUT VOLTAGE
Figure 7
VI − Input Voltage − V
0
5
10
15
20
25
30
5678910
TA = 25°C
(POWER DOWN)
vs
INPUT VOLTAGE
Figure 8
VI − Input Voltage − V
0
100
200
300
400
500
600
4.5 5.5 6.5 7.5 8.5 9.5
TA = 25°C
Dropout Voltage − mV
vs
INPUT VOLTAGE
100 mA
400 mA
1200 mA
800 mA
if} TEXAS INSTRUMENTS Dropout Voltage - mV In — Reverse Current — “A 500 r 300 TA : 25%: 500 700 500 400 E . vcc : 5 v 3 500 m 300 = g / 5 400 a 200 § / vcc = 10 v a 300 100 200 / 0 100 o 200 400 600 300 1000 1200 —50 0 50 100 IE lo — ompui Currenr — mA TJ — Junction Temperature — cc Figure 9 Figure 10 6 4.0 v0.” = 4.3 v 3.5 5 4 1 ‘ 3.0 S 4 2 g 2.5 .r E 3 g 2.0 = U / 3 1.5 2 E / g 1.0 / . 1 E 0.5 o 0.0 —50 0 50 100 150 5 6 7 a 3 10 1,. - Junction Temperature — cc Figure 11 VD — Voltage on om Fin - v Figure 12
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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10
TYPICAL CHARACTERISTICS
Figure 9
IO − Output Current − mA
0
100
200
300
400
500
600
0 200 400 600 800 1000 1200
TA = 25°C
Dropout Voltage − mV
vs
OUTPUT CURRENT
VCC = 5 V
VCC = 10 V
Figure 10
TJ − Junction Temperature − °C
100
200
300
400
500
600
700
800
−50 0 50 100 150
Dropout Voltage − mV
vs
JUNCTION TEMPERATURE
VIN = 10 V
VIN = 5 V
IO = 1.2 A
Figure 11
TJ − Junction Temperature − °C
0
1
2
3
4
5
6
−50 0 50 100 150
R
µ
vs
JUNCTION TEMPERATURE
VOUT = 4.3 V
Figure 12
VO Voltage on Out Pin − V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5678910
IR − Reverse Current Leakage − µA
vs
VOLTAGE ON OUT PIN
TA = 25°C
*5 TEXAS INSTRUMENTS F771 _I ‘ 1 \ \ :7} vcc VSENSE \ ‘ DC" 5 1s \ ISNS AGND PACK» ‘ 1 T is N/c STAT2 ‘5 ‘ \ c2 7 ‘ gm 0.1 “F APG/THM STAT1 1 ‘ 3 EN TMRSEL TEMP ‘ 1 “H VSEL CR GND N/C bq24002PWP 18.7 kn
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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11
APPLICATION INFORMATION
U1
N/C N/C
120
IN OUT
219
IN OUT
318
VCC VSENSE
417
ISNS AGND
516
N/C STAT2
615
APG/THM STAT1
714
VSEL CR
912
EN TMR SEL
813
GND N/C
10 11
VCC
C2
0.1 µF
R1
0.1
C1
10 µF +
DC−
DC+
VCC
bq24002PWP
TEMP
PACK+
PACK−
R2
18.7 k
C3
0.22 µF
+
C4
1 µF
Battery
Pack
R4
500
D1
VCC
R5
500
D2
R3
95.3 k
Figure 13. Li-Ion/Li-Pol Charger
DIf the TMR SEL pin is left floating (3 HR time), a 10-pF capacitor should be installed between TMR SEL and CR.
DIf a micro process is monitoring the STAT pins, it may be necessary to add some hysteresis into the feedback
to prevent the STAT pins from cycling while crossing the taper detect threshold (usually less than one half
second). See SLUU083 EVM or SLUU113 EVM for additional resistors used for the STAT pins.
if} TEXAS INSTRUMENTS
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12
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The bq2400x supports a precision current- and voltage-regulated Li-Ion charging system suitable for cells with either coke
or graphite anodes. See Figure 14 for a typical charge profile and Figure 15 for an operational flowchart.
Preconditioning
Phase
Regulation Voltage
(VOUT)
Current Regulation
Phase Voltage Regulation and
Charge TerminationPhase
Regulation Current
(Ilim)
Minimum Charge
Voltage (LowV)
Preconditioning
Current (IPRECHG)
Charge Voltage
Charge Current
22.5 Minutes 22.5 Minutes
Charge Timer (3, 4.5 or 6 Hours)
Taper Detect
Figure 14. Typical Charge Profile
*5 TEXAS INSTRUM ENTS
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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13
Yes
No
22.5min Timer
Expired?
No
Yes
Indicate Fault
POR?
or
APG/THERM toggle?
or
EN toggle?
Yes
No
Yes
Charge timer
Expired?
No
Indicate Pre−
Charge
Regulate
I(PRECHG)
Indicate Charge
Regulate Current
or Voltage
Reset and Start
22.5 min Timer
POR
Reset All Timers,
Start Charge Timer
(TMR SEL input )
No
Fault Condition
No
Yes
Indicate DONE
Turn Off Charge
Taper
Detected?
No
No
Yes
Yes
No
Yes
No
Yes
22.5min Timer
Expired?
Yes
Yes
Indicate DONE
Start 22.5 minute
Timer
VI(VSENSE) < V(HIGHV)?
or
POR?
or
APG/THERM Toggle?
or
EN Toggle?
VI(VSENSE) < V(LOWV)?
VI(VSENSE) > V(OVERV)?
VI(VSENSE) > V(OVERV)?
VI(VSENSE) < V(LOWV)?
VI(VSENSE) < V(LOWV)?
Figure 15. Operational Flow Chart
*9 TEXAS INSTRUMENTS ‘“‘°°“‘°“"‘““ vcc VSENSE ISNS AGND N/C STAT2 i APG/THM STA“ EN TMR SEL VSEL CR GND N/C ‘ W bq24002PWP < pack»="">
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14
Charge Qualification and Preconditioning
The bq2400x starts a charge cycle when power is applied
while a battery is present. Charge qualification is based on
battery voltage and the APG/THERM input.
As shown in the block diagram, the internal LowV
comparator output prevents fast-charging a deeply
depleted battery. When set, charging current is provided
by a dedicated precharge current source. The precharge
timer limits the precharge duration. The precharge current
also minimizes heat dissipation in the pass element during
the initial stage of charge.
The APG/THERM input can also be configured to monitor
either the adapter power or the battery temperature using
a thermistor. The bq2400x suspends charge if this input is
outside the limits set by the user. Please refer to the
APG/THERM input section for additional details.
APG/THERM Input
The bq400x continuously monitors temperature or system
input voltage by measuring the voltage between the
APG/THERM (adapter power good/thermistor) and GND.
For temperature, a negative- or a positive- temperature
coefficient thermistor (NTC, PTC) and an external voltage
divider typically develop this voltage (see Figure 16). The
bq2400x compares this voltage against its internal VTP1
and VTP2 thresholds to determine if charging is allowed.
(See Figure 17.)
U1
N/C N/C
120
IN OUT
219
IN OUT
318
VCC VSENSE
417
ISNS AGND
516
N/C STAT2
615
APG/THM STAT1
714
VSEL CR
912
EN TMR SEL
813
GND N/C
10 11
bq24002PWP
TEMP
PACK+
PACK−
RT1
C3
0.22 µF
+
Battery Pack
RT2
NTC Thermistor
Figure 16. Temperature Sensing Circuit
*5 TEXAS INSTRUM ENTS Figure 17. Temperature Threshold where VApG Figure 18. AP
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15
If the charger designs incorporate a thermistor, the resistor
divider RT1 and RT2 is calculated by using the following
two equations.
First, calculate RT2.
RT2 +
VBRHRCƪ1
VC*1
VHƫ
RHǒVB
VH*1Ǔ*RCǒVB
VC*1Ǔ
then use the resistor value to find RT1.
RT1 +
VB
VC*1
1
RT2 )1
RC
Where:
VB = VCR (bias voltage)
RH = Resistance of the thermistor at the desired hot trip
threshold
RC = Resistance of the thermistor at the desired cold trip
threshold
VH = VP2 or the lower APG trip threshold
VC = VP2 or the upper APG trip threshold
RT1 = Top resistor in the divider string
RT2 = Bottom resistor in the divider string
GND
VTP2
VTP1
Vcc
Normal Temp Range
Temp Fault
Temp Fault
Figure 17. Temperature Threshold Figure 18. APG Sensing Circuit
U1
N/C N/C
120
IN OUT
219
IN OUT
318
VCC VSENSE
417
ISNS AGND
516
N/C STAT2
615
APG/THM STAT1
714
VSEL CR
912
EN TMR SEL
813
GND N/C
10 11
DC−
DC+
VCC
bq24002PWP
R1
R2
Values of resistors R1 and R2 can be calculated using the following equation:
VAPG +VCC
R2
(R1 )R2)
where V
APG
is the voltage at the APG/THM pin.
Current Regulation
The bq2400x provides current regulation while the battery-pack voltage is less than the regulation voltage. The current
regulation loop effectively amplifies the error between a reference signal, Vilim, and the drop across the external sense
resistor, RSNS.
*9 TEXAS INSTRUMENTS where IREG f
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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16
U1
N/C N/C
120
IN OUT
219
IN OUT
318
VCC VSENSE
417
ISNS AGND
516
N/C STAT2
615
APG/THM STAT1
714
VSEL CR
912
EN TMR SEL
813
GND N/C
10 11
VCC
C2
0.1 µF
RSNS
C1
10 µF+
DC−
DC+
VCC
bq24002PWP
Figure 19. Current Sensing Circuit
Charge current feedback, applied through pin ISNS,
maintains regulation around a threshold of Vilim. The
following formula calculates the value of the sense
resistor:
RSNS +
Vilim
IREG
where I
REG
is the desired charging current.
Voltage Monitoring and Regulation
Voltage regulation feedback is through pin VSENSE. This
input is tied directly to the positive side of the battery pack.
The bq2400x supports cells with either coke (4.1 V) or
graphite (4.2 V) anode. Pin VSEL selects the charge
regulation voltage.
VSEL State
(see Note) CHARGE REGULATION
VOLTAGE
Low 4.1 V
High 4.2 V
NOTE: VSEL should not be left floating.
Charge Termination
The bq2400x continues with the charge cycle until
termination by one of the two possible termination
conditions:
Maximum Charge Time: The bq2400x sets the maximum
charge time through pin TMRSEL. The TMR SEL pin
allows the user to select between three different total
charge-time timers (3, 4, 5, or 6 hours). The charge timer
is initiated after the preconditioning phase of the charge
and is reset at the beginning of a new charge cycle. Note
that in the case of a fault condition, such as an out-of-range
signal on the APG/THERM input or a thermal shutdown,
the bq2400x suspends the timer.
TMRSEL STATE CHARGE TIME
Floating(1) 3 hours
Low 6 hours
High 4.5 hours
(1) To improve noise immunity, it is recommended that a minimum of
10 pF capacitor be tied to Vss on a floating pin.
Minimum Current: The bq2400x monitors the charging
current during the voltage regulation phase. The bq2400x
initiates a 22-minute timer once the current falls below the
taperdet trip threshold. Fast charge is terminated once the
22-minute timer expires.
Charge Status Display
The three available options allow the user to configure the
charge status display for single LED (bq24001), two
individual LEDs (bq24002) or a bicolor LED (bq24003).
The output stage is totem pole for the bq24001 and
bq24003 and open-drain for the bq24002. The following
tables summarize the operation of the three options:
Table 1. bq24001 (Single LED)
CHARGE STATE STAT1
Precharge ON (LOW)
Fast charge ON (LOW)
FAULT Flashing (1 Hz, 50% duty cycle)
Done (>90%) OFF (HIGH)
Sleep-mode OFF (HIGH)
APG/Therm invalid OFF (HIGH)
Thermal shutdown OFF (HIGH)
Battery absent OFF (HIGH)
‘9 TEXAS INSTRUM ENTS
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
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17
Table 2. bq24002 (2 Individual LEDs)
CHARGE STATE STAT1 (RED) STAT2
(GREEN)
Precharge ON (LOW) OFF
Fast charge ON (LOW) OFF
FAULT Flashing (1 Hz,
50% duty cycle) OFF
Done (>90%) OFF ON (LOW)
Sleep-mode OFF OFF
APG/Therm invalid OFF OFF
Thermal shutdown OFF OFF
Battery absent OFF OFF(1)
(1) If thermistor is used, then the Green LED is off.
Table 3. bq24003 (Single Bicolor LED)
CHARGE STATE LED1 (RED) LED2
(GREEN) APPARENT
COLOR
Precharge ON (LOW) OFF (HIGH) RED
Fast charge ON (LOW) OFF (HIGH) RED
FAULT ON (LOW) ON (LOW) YELLOW
Done (>90%) OFF (HIGH) ON (LOW) GREEN
Sleep-mode OFF (HIGH) OFF (HIGH) OFF
APG/Therm
invalid OFF (HIGH) OFF (HIGH) OFF
Thermal
shutdown OFF (HIGH) OFF (HIGH) OFF
Battery absent OFF (HIGH) OFF (HIGH)(1) OFF(1)
(1) If thermistor is used, then the Green LED is off.
Thermal Shutdown
The bq2400x monitors the junction temperature TJ of the DIE and suspends charging if TJ exceeds 165°C. Charging
resumes when TJ falls below 155°C.
DETAILED DESCRIPTION
POWER FET
The integrated transistor is a P-channel MOSFET. The
power FET features a reverse-blocking Schottky diode,
which prevents current flow from OUT to IN.
An internal thermal-sense circuit shuts off the power FET
when the junction temperature rises to approximately
165°C. Hysteresis is built into the thermal sense circuit.
After the device has cooled approximately 10°C, the
power FET turns back on. The power FET continues to
cycle off and on until the fault is removed.
CURRENT SENSE
The bq2400x regulates current by sensing, on the ISNS
pin, the voltage drop developed across an external sense
resistor. The sense resistor must be placed between the
supply voltage (Vcc) and the input of the IC (IN pins).
VOLTAGE SENSE
To achieve maximum voltage regulation accuracy, the
bq2400x uses the feedback on the VSENSE pin.
Externally, this pin should be connected as close to the
battery cell terminals as possible. For additional safety, a
10k internal pullup resistor is connected between the
VSENSE and OUT pins.
ENABLE (EN)
The logic EN input is used to enable or disable the IC. A
high-level signal on this pin enables the bq2400x. A
low-level signal disables the IC and places the device in a
low-power standby mode.
*9 TEXAS INSTRUMENTS E
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
www.ti.com
18
THERMAL INFORMATION
THERMALLY ENHANCED TSSOP-20
The thermally enhanced PWP package is based on the
20-pin TSSOP, but includes a thermal pad (see
Figure 20) to provide an effective thermal contact between
the IC and the PWB.
Traditionally, surface mount and power have been
mutually exclusive terms. A variety of scaled-down
TO220-type packages have leads formed as gull wings to
make them applicable for surface-mount applications.
These packages, however, suffer from several
shortcomings: they do not address the very low profile
requirements (<2 mm) of many of today’s advanced
systems, and they do not offer a pin-count high enough to
accommodate increasing integration. On the other hand,
traditional low-power surface-mount packages require
power-dissipation derating that severely limits the usable
range of many high-performance analog circuits.
The PWP package (thermally enhanced TSSOP)
combines fine-pitch surface-mount technology with
thermal performance comparable to much larger power
packages.
The PWP package is designed to optimize the heat
transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement
is achieved by improving the thermal conduction paths that
remove heat from the component. The thermal pad is
formed using a lead-frame design (patent pending) and
manufacturing technique to provide the user with direct
connection to the heat-generating IC. When this pad is
soldered or otherwise coupled to an external heat
dissipator, high power dissipation in the ultrathin,
fine-pitch, surface-mount package can be reliably
achieved.
DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
Thermal
Pad
Figure 20. Views of Thermally Enhanced
PWP Package
Because the conduction path has been enhanced,
power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply
adding a localized copper plane (heat-sink surface), which
is coupled to the thermal pad, enables the PWP package
to dissipate 2.5 W in free air. (Reference Figure 22(a), 8
cm2 of copper heat sink and natural convection.)
Increasing the heat-sink size increases the power
dissipation range for the component. The power
dissipation limit can be further improved by adding airflow
to a PWB/IC assembly (see Figure 22(b) and 22(c)). The
line drawn at 0.3 cm2 in Figures 21 and 22 indicates
performance at the minimum recommended heat-sink
size.
*5 TEXAS INSTRUM ENTS Nalulal Con 50 film //// X 250 fl/min / //// // /// //
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
www.ti.com
19
THERMAL INFORMATION
100
75
50
25
0235
− Thermal Resistance −
125
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
781460.3
Natural Convection
50 ft/min
250 ft/min
300 ft/min
C/W
°
Copper Heat-Sink Area − cm2
100 ft/min
150 ft/min
200 ft/min
RJA
θ
Figure 21
if} TEXAS INSTRUMENTS son fl/min ‘50 m :00 "min 150 fl/min 7 /muual Convection Nalural Conveclion anon/min ’— / Natural Convemion
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004
www.ti.com
20
THERMAL INFORMATION
1
0.5
3
00246
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA = 55°C
(b)
1
0.5
3
00246
2
1.5
2.5
3.5
8
0.3
300 ft/min 150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA = 105°C
(c)
1
0.5
3
00246
− Power Dissipation Limit − W
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
PD
Copper Heat-Sink Size − cm2
TA = 25°C
(a)
− Power Dissipation Limit − W
PD
− Power Dissipation Limit − W
PD
Figure 22. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ24001PWP ACTIVE HTSSOP PWP 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 BQ24001 Samples
BQ24002PWP ACTIVE HTSSOP PWP 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 0 BQ24002 Samples
BQ24002PWPG4 ACTIVE HTSSOP PWP 20 70 TBD Call TI Call TI 0 to 0 Samples
BQ24002PWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 0 BQ24002 Samples
BQ24002PWPRG4 ACTIVE HTSSOP PWP 20 2000 TBD Call TI Call TI 0 to 0 Samples
BQ24002RGWR ACTIVE VQFN RGW 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 0 24002 Samples
BQ24003PWP ACTIVE HTSSOP PWP 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 BQ24003 Samples
BQ24003PWPG4 ACTIVE HTSSOP PWP 20 70 TBD Call TI Call TI 0 to 70 Samples
BQ24003PWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 BQ24003 Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ24002PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
BQ24002RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
BQ24003PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24002PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0
BQ24002RGWR VQFN RGW 20 3000 367.0 367.0 35.0
BQ24003PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
BQ24001PWP PWP HTSSOP 20 70 530 10.2 3600 3.5
BQ24002PWP PWP HTSSOP 20 70 530 10.2 3600 3.5
BQ24003PWP PWP HTSSOP 20 70 530 10.2 3600 3.5
Pack Materials-Page 3
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VQFN - 1 mm max heightRGW 20
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.65 mm pitch
4227157/A
T I I - is w 17L ¢ CCEE w im " fl 2 \M‘“ ‘ ‘14!“ ‘ ‘m‘ ”J U W H W im , H L 33333 +HJ W J HIT
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
PACKAGE OUTLINE
4219039/A 06/2018
www.ti.com
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RGW0020A
C
0.08 C
0.1 C A B
0.05 C
B
SYMM
SYMM
PIN 1 INDEX AREA
5.1
4.9
5.1
4.9
1 MAX
0.05
0.00
SEATING PLANE
(0.1) TYP
3.15±0.1
2X
2.6
16X 0.65
20X 0.65
0.45
20X 0.36
0.26
2X 2.6
PIN1 ID
(OPTIONAL)
1
5
15
11
21
610
16
20
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219039/A 06/2018
www.ti.com
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL EXPOSED METAL
SOLDER MASK DETAILS
( 3.15)
(2.6)
(4.65)
(2.6)
16X (0.65)
(4.65)
20X (0.75)
20X (0.31)
(Ø0.2) VIA
TYP
(R0.05) TYP
(1.325)
(1.325)
1
5
610
11
15
16
20
21
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
EXAMPLE STENCIL DESIGN
4219039/A 06/2018
www.ti.com
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
4X ( 1.37)
(2.6)
(4.65)
(2.6)
16X (0.65)
(4.65)
20X (0.75)
20X (0.31)
(R0.05) TYP
2X (0.785)
2X (0.785)
1
5
610
11
15
16
20
21
METAL
TYP
MECHANICAL DATA M 1“ AST‘C WAN OUT N’ NOTES, com» AH Hnec' d'vnensmrs c'e m m'hmekers Tm drawer ‘5 subje», ,0 change wnrau: name, Body dimensmns do nut mm mm flcsh m aroms‘ms Mam am an: Drotrns'an she“ no: exceed ms pe' side ”‘3 pomagc \s CCS‘QHCd to be SO‘GL‘YQG to a “WWW pad on the boom Refer k) cchmm‘ HHcf, ’owc'Pad Tr'eurtu Erhuncec Fucmge‘ Texts \nst'mreuts Utemlue No S VAUOZ my Wow-um)" veguvcmg vecovrmenced buuvd \uyuLl Th5 duumen: Es uvu ub‘e u: wwwL r <‘vttu www="" uto'vv=""> See me accmonm hqure 'v the Jmmfl Dam Swee! ‘nr cams reqmdwg Me exaosed Mer'mfl pad features and mmensmns Fc‘s wwtmr JEDEC M0 153 PawevPAD is a trademalk 0! Texas \nurumems. {I} TEXAS INSTRUMENTS www.ti.com
LAND PATTERN DATA PWP (R—PDSO—GZO) PowerPADW PLASTlC SMALL OUTLINE Example Board Layout Stencil Openln s_ Via pattern and copper pad size Based on a slencl‘t Ickness may vary dependlng on layout constraints 0' -tZ7mm (-005Inch)- Reference table below tor other l“”“5'“ae‘°we’ W“ W'” solder stencil thicknesses enhance t rmal performance (See Note D) ,3 4>T l—il8x0,65 20x0.25—— ‘— -—HHTHHHHTH 5.6 2,4 3.4 (See Note E) Y 2.4 _l x l 3.7 Solder: Mask Example Solder Mask _—|:| H :| H H H H [ H H as upper - <52:"l2tepé‘,dal l8x0.65»l="" l6="" 1/="" example="" i="" non="" saldermask="" defined="" pad="" '="" ‘/="" \‘\.="" example="" solder="" mask="" opening="" (see="" nme="" f)="" center="" power="" pud="" solder="" stencil="" opening="" stencil="" thickness="" x="" y="" 0.1mm="" 3.9="" 2.7="" 0.127rnrn="" 3.7="" 2.4="" pad="" geometry="" 0.152mm="" 3.5="" 2.2="" o="" 07="" 0.178mm="" 3.3="" 2.1="" 4207609s8/w="" 09/15="" notes:="" all="" llnear="" dimensions="" are="" ln="" millimeters="" thls="" drawing="" is="" subject="" to="" change="" without="" notice.="" customers="" should="" place="" a="" note="" on="" the="" circuit="" board="" raan'calian="" drawing="" not="" ta="" alter="" the="" center="" solder="" musk="" defined="" pad.="" this="" package="" is="" deslgned="" to="" be="" soldered="" to="" a="" lnennal="" pad="" on="" the="" baard,="" reler="" to="" technical="" brier,="" powerpod="" thermally="" enhanced="" package.="" texas="" instruments="" literature="" no.="" slmaooz,="" slmaom,="" and="" also="" the="" product="" data="" sheets="" (or="" specific="" thermal="" information.="" via="" requirements.="" and="" recommended="" board="" layout.="" these="" documents="" are="" available="" at="" wwwtieam="">. Pablieatlen cherssl is recommended lor alternate deslgns. E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should Contact their board assembly site tor stencil design recommendations. Example stencil design based on a 50% volumetric metal load Solder paste. Reler to |PCi7525 for other stencil recommendations, F. Customers should Contact their board fabrication site for solder mask tolerances between and around signal pads. 539?“? ' TEXAS INSTRUMENTS wwwltlcon
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