Fiche technique pour SN54HCT273, SN74HCT273 de Texas Instruments

U Ordering & Technical Design a 3 Support & naming o o quahiy documentation development TEXAS INSTRUMENTS ( 1D 20 SD 4D SD 7D 3D 11 a '4 ‘ 1 ‘ a 3 M In 15 “KAI L I |_ ‘ L L L L In L ID LID 1D In L ID ID ID vAcu {Acu — e1 —» e1 r~e1 \c1 — —'v :1 c1— R f R F R % R R F R 4 R 1 R m ' 2 5 ‘ 6 ‘I2 I5 16 Is m m m 50 so 1Q an C c | E a F m { rt CLK(I) ’ Tc 7 E E , E ”I ‘4—
SNx4HCT273 Octal D-Type Flip-Flops With Clear
1 Features
• Operating voltage range of 4.5 V to 5.5 V
• Outputs can drive up to 10 LSTTL loads
• Low power consumption, 80 µA maximum ICC
• Typical tpd = 12 ns
• ±4 mA output drive at 5 V
• Low input current of 1 µA maximum
• Inputs are TTL-voltage compatible
• Contain eight D-type flip-flops
• Direct clear input
2 Applications
• Buffer or storage registers
• Shift registers
• Pattern generators
3 Description
These devices are positive-edge-triggered D-type flip-
flops with a common enable input. The ’HCT273
devices are similar to the ’HCT377 devices, but
feature a common clear enable (CLR) input instead
of a latched clock.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCT273DW SOIC (20) 12.80 mm × 7.50 mm
SN74HCT273DB SSOP (20) 7.20 mm × 5.30 mm
SN74HCT273N PDIP (20) 25.40 mm × 6.35 mm
SN74HCT273NS SO (20) 15.00 mm × 5.30 mm
SN74HCT273PW TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, (postive logic)
Logic Diagram, Each Flip Flop (positive logic)
SN54HCT273, SN74HCT273
SCLS068F – NOVEMBER 1988 – REVISED FEBRUARY 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions(1) .................... 4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Timing Requirements.................................................. 5
6.6 Switching Characteristics............................................6
6.7 Switching Characteristics............................................6
6.8 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Device Functional Modes............................................8
9 Power Supply Recommendations..................................9
10 Layout.............................................................................9
10.1 Layout Guidelines..................................................... 9
11 Device and Documentation Support..........................10
11.1 Receiving Notification of Documentation Updates.. 10
11.2 Support Resources................................................. 10
11.3 Trademarks............................................................. 10
11.4 Electrostatic Discharge Caution.............................. 10
11.5 Glossary.................................................................. 10
12 Mechanical, Packaging, and Orderable
Information.................................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2003) to Revision F (February 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
SN54HCT273, SN74HCT273
SCLS068F – NOVEMBER 1988 – REVISED FEBRUARY 2022 www.ti.com
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TEXAS INSTRUMENTS HHHHHHHHHH HHHHHHHHHH
5 Pin Configuration and Functions
1
2
3
7
4
5
6
14
13
12
8
11
18
17
GND
7Q
6D
5D
VCC
15
16
1Q
1D
CLR
3Q
3D
CLK
6Q
5Q
2Q
2D
10
9
3Q
3D
8D
8Q
7D
20
19
DB, DW, N, NS, or PW package
20-Pin SSOP, SOIC, PDIP, SO, or TSSOP
(Top View)
FK package
20-Pin LCCC
(Top View)
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SCLS068F – NOVEMBER 1988 – REVISED FEBRUARY 2022
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TEXAS INSTRUMENTS
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IOContinuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Recommended Operating Conditions(1)
SN54HCT273(2) SN74HCT273 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
Δt/Δv Input transition rise or fall rate 500 500 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Product Preview
6.3 Thermal Information
THERMAL METRIC
DW (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP)
UNIT20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal
resistance(1) 58 70 69 60 83 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
SN54HCT273, SN74HCT273
SCLS068F – NOVEMBER 1988 – REVISED FEBRUARY 2022 www.ti.com
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TEXAS INSTRUMENTS
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC
TA = 25°C SN54HCT273(1) SN74HCT273 UNIT
MIN TYP MAX MIN MAX MIN MAX
VOH VI = VIH or VIL
IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4 V
IOH = –4 mA 4.5 V 3.98 4.30 3.7 3.84
VOL VI = VIH or VIL
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IIVI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
ΔICC (2) One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V 1.4 2.4 3 2.9 mA
Ci
4.5 V to
5 V 3 10 10 10 pF
(1) Product Preview
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VCC
TA = 25°C SN54HCT273(1) SN74HCT273 UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 4.5 V 25 16 20 MHz
5.5 V 28 19 23
twPulse duration
CLK high or low 4.5 V 20 30 25
ns
5.5 V 18 25 22
CLR low 4.5 V 16 24 20
5.5 V 14 20 17
tsu Setup time before CLK↑
Data 4.5 V 20 30 25
ns
5.5 V 17 25 21
CLR inactive 4.5 V 20 30 25
5.5 V 17 25 21
thHold time, data after CLK↑ 4.5 V 0 0 0 ns
5.5 V 0 0 0
(1) Product Preview
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TEXAS INSTRUMENTS cc TA
6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter
Measurement Information)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) VCC
SN54HCT273(1)
UNITTA = 25°C MIN MAX
MIN TYP MAX
fmax
4.5 V 25 31 16 MHz
5.5 V 28 37 19
tpd CLR Any 4.5 V 15 34 50 ns
5.5 V 12 29 42
tPHL CLR Any 4.5 V 17 15 50 ns
5.5 V 15 34 42
ttAny 4.5 V 8 18 22 ns
5.5 V 7 19 21
(1) Product Preview
6.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter
Measurement Information)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) VCC
SN74HCT273
UNITTA = 25°C MIN MAX
MIN TYP MAX
fmax
4.5 V 25 31 20 MHz
5.5 V 28 37 23
tpd CLR Any 4.5 V 15 34 42 ns
5.5 V 12 29 36
tPHL CLR Any 4.5 V 17 34 42 ns
5.5 V 15 29 36
ttAny 4.5 V 8 15 19 ns
5.5 V 7 14 17
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 30 pF
SN54HCT273, SN74HCT273
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
CL(1)
From Output
Under Test
Test
Point
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
1.3V
tw
Input 1.3V
3V
0 V
Figure 7-2. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
Clock
Input 1.3V
3V
0 V
1.3V 1.3V
3V
0 V
tsu
Data
Input
th
Figure 7-3. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
1.3VInput 1.3V
3V
0 V
50% 50%
VOH
VOL
tPLH
(1) tPHL
(1)
VOH
VOL
tPHL
(1) tPLH
(1)
Output
Waveform 1
Output
Waveform 2 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
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ITEXAs INSTRUMENTS 1° so 7n so ‘3 3 ‘14 ‘11 la n CLK L L L ‘D ID 1D ID 1!) .c1 M" Ma *c1 fl 7 m R R f, R f, R R fi‘ ‘ ‘12 315 15 19 50 so 70 ea c c \ D 1:; >0—9— TG 4.— a I. c i C ‘ < [f="" .="" c="" c="" ”i="">
8 Detailed Description
8.1 Overview
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices
are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect
at the output. The circuits are designed to prevent false clocking by transitions at CLR.
8.2 Functional Block Diagram
Figure 8-1. Logic Diagram (positive logic)
Figure 8-2. Logic Diagram, each flip-flop (potitive logic)
8.3 Device Functional Modes
Table 8-1. Function Table
(Each Flip-Flop)
INPUTS OUTPUT
Q
CLR CLK D
L X X L
H ↑ H H
H ↑ L L
H L X Q0
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9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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l TEXAS INSTRUMENTS Am
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
SN54HCT273, SN74HCT273
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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HCT273DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273
SN74HCT273DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273DWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT273N
SN74HCT273NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273
SN74HCT273PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273
SN74HCT273PWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273
SN74HCT273PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273
SN74HCT273PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT273
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pitch between SucCeSSWe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HCT273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HCT273DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74HCT273NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74HCT273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HCT273PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT273DBR SSOP DB 20 2000 853.0 449.0 35.0
SN74HCT273DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74HCT273NSR SO NS 20 2000 367.0 367.0 45.0
SN74HCT273PWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74HCT273PWT TSSOP PW 20 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74HCT273DW DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT273DWE4 DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT273DWG4 DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT273N N PDIP 20 20 506 13.97 11230 4.32
SN74HCT273PW PW TSSOP 20 70 530 10.2 3600 3.5
SN74HCT273PWE4 PW TSSOP 20 70 530 10.2 3600 3.5
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 3
I-III
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PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10
11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
“‘w“‘+“‘w“‘
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EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
mi: 2.5%
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EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
--I L J f T , g T Q f fl g
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
6.6
6.4
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
““‘w‘+‘w““‘
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
gmgmmj r Egg;
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
LAND PATTERN DATA PW (R7PDSOmGZO) PLAST‘C SMALL OUTLINE Exam ‘9 Board LG I“ F W Based on o stencii thickness oi .127mm (.oosinen). -—iiiiii‘fli*m -—iiiifi°fi°’i”ii ——U/,'Efli‘iiiiii -—HHHH1QXQBQHJH« A , Pad Geometry “\ 0,07 /’ ‘ ‘AH Arourig/ 421128475/6 08/15 NOTES: A. AH iineor dimensions are in miiiimeters. B. Inis drawing is subject to change without notice. c. Publication iPcr735i is recommended for aitemate design. D Laser cutting apertures witn trapezoidoi wuHs and oiso rounding earners wiii oiier aetter paste reieose. Customers should contact tneir board assembiy site (or stencii design recommendations. Reier to iPc—7525 (or otner stencii recommendations. E. Cusmmers shuuid Contact ‘heir hoard fubr‘icufiun site for solder musk tolerances beLween and nruund signal pads. {I} Tums INSTRUMENTS www.li.com
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