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VIN
S5
GND
S3
VDDQSNS
VLDOIN
PGND
VTT
TPS51100DGQ
C2
0.1 µF
5 6VTTREFVTTSNS
C1
2 x 10 µF
S3
VTTREF
5V_IN
S5
Capacitor
C1
C2
Manuf
TDK
TDK
Part Number
C2012JB0J106K
C1608JB1H104K
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TPS51100
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
TPS51100 3-A Sink / Source DDR Termination Regulator
1 Features 3 Description
The TPS51100 is a 3-A, sink/source tracking
1• Input Voltage Range: 4.75 V to 5.25 V termination regulator. The device is specifically
• VLDOIN Voltage Range: 1.2 V to 3.6 V designed for low-cost and low-external component
• 3-A Sink/Source Termination Regulator Includes count systems where space is a premium.
Droop Compensation The TPS51100 maintains fast transient response,
• Requires Only 20-μF Ceramic Output Capacitance only requiring 20 μF (2 × 10 μF) of ceramic output
• Supports Hi-Z in S3 and Soft-Off in S5 capacitance. The TPS51100 supports remote sensing
functions and all features required to power the DDR
• 1.2-V Input (VLDOIN) Helps Reduce Total Power and DDR2 VTT bus termination according to the
Dissipation JEDEC specification. The part also supports DDR3
• Integrated Divider Tracks 0.5 VDDQSNS for VTT VTT termination with VDDQ at 1.5 V (typical). In
and VTTREF addition, the TPS51100 includes integrated sleep-
state controls, placing VTT in Hi-Z in S3 (suspend to
• Remote Sensing (VTTSNS) RAM) and soft-off for VTT and VTTREF in S5
• ±20-mV Accuracy for VTT and VTTREF (suspend to disk). The TPS51100 is available in the
• 10-mA Buffered Reference (VTTREF) thermally efficient 10-pin MSOP PowerPAD™
• Built-In Soft-Start, UVLO, and OCL package and is specified from –40°C to 85°C.
• Thermal Shutdown Device Information(1)
• Supports JEDEC Specifications PART NUMBER PACKAGE BODY SIZE (NOM)
TPS51100 HVSSOP (10) 3.00 mm x 3.00 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• DDR, DDR2, DDR3 Memory Termination the end of the datasheet.
• SSTL-2, SSTL-18, and HSTL Termination
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLUS600E –APRIL 2004–REVISED DECEMBER 2014
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Table of Contents
7.4 Device Functional Modes........................................ 12
1 Features.................................................................. 18 Application and Implementation ........................ 13
2 Applications ........................................................... 18.1 Application Information............................................ 13
3 Description ............................................................. 18.2 Typical Application ................................................. 13
4 Revision History..................................................... 29 Power Supply Recommendations...................... 16
5 Pin Configuration and Functions......................... 310 Layout................................................................... 16
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 16
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 17
6.2 Recommended Operating Conditions....................... 410.3 Thermal Considerations........................................ 17
6.3 Thermal Information.................................................. 411 Device and Documentation Support ................. 19
6.4 Electrical Characteristics........................................... 511.1 Device Support...................................................... 19
6.5 Typical Characteristics.............................................. 711.2 Trademarks........................................................... 19
7 Detailed Description............................................ 11 11.3 Electrostatic Discharge Caution............................ 19
7.1 Overview ................................................................. 11 11.4 Glossary................................................................ 19
7.2 Functional Block Diagram....................................... 11 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 11 Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2012) to Revision E Page
• Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes,Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision C (June 2008) to Revision D Page
• Added updated Thermal data................................................................................................................................................. 4
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ActualSize
3,05mmx4,98mm
1
2
3
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VDDQSNS
VLDOIN
VTT
PGND
VTTSNS
VIN
S5
GND
S3
VTTREF
DGQPackage
(TopView)
P0083-01
TPS51100
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SLUS600E –APRIL 2004–REVISED DECEMBER 2014
5 Pin Configuration and Functions
NOTE: For more information on the DGQ package, see the PowerPAD Thermally Enhanced Package application report
(SLMA002).
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
GND 8 – Signal ground. Connect to negative terminal of the output capacitor
PGND 4 – Power ground output for the VTT LDO
S3 7 I S3 signal input
S5 9 I S5 signal input
VDDQSNS 1 I VDDQ sense input
VIN 10 I 5-V power supply
VLDOIN 2 I Power supply for the VTT LDO and VTTREF output stage
VTT 3 O Power output for the VTT LDO
VTTREF 6 O VTT reference output. Connect to GND through 0.1-μF ceramic capacitor.
VTTSNS 5 I Voltage sense input for the VTT LDO. Connect to plus terminal of the output capacitor.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5 –0.3 6
Input voltage(2) V
PGND –0.3 0.3
Output voltage(2) VTT, VTTREF –0.3 6 V
TAOperating ambient temperature –40 85 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply voltage 4.75 5.25 V
S3, S5 –0.10 5.25
VLDOIN, VDDQSNS, VTT, VTTSNS –0.1 3.6
Voltage range V
VTTREF –0.1 1.8
PGND –0.1 0.1
TAOperating free-air temperature –40 85 °C
6.3 Thermal Information
TPS51100
THERMAL METRIC(1) DGQ UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance 60.3
RθJC(top) Junction-to-case (top) thermal resistance 63.5
RθJB Junction-to-board thermal resistance 51.6 °C/W
ψJT Junction-to-top characterization parameter 1.5
ψJB Junction-to-board characterization parameter 22.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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VDDQSNS
V
2
VDDQSNS
TT A
V
V 1.25 V, T = 25 C
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TT A
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V 1.25 V, T = 25 C
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VDDQSNS
TT
V
V 0.95, PGOOD = High
2
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TPS51100
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SLUS600E –APRIL 2004–REVISED DECEMBER 2014
6.4 Electrical Characteristics
TA= –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN Supply current, VIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V 0.25 0.5 1 mA
IVINSTB Standby currrent, VIN TA= 25°C, VVIN = 5 V, no load, VS3 = 0 V, VS5 = 5 V 25 50 80 μA
TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V, VVLDOIN
IVINSDN Shutdown current, VIN 0.3 1 μA
= VVDDQSNS = 0 V
IVLDOIN Supply current, VLDOIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V 0.7 1.2 2 mA
IVLDOINSTB Standby currrent, VLDOIN TA= 25°C, VVIN = 5 V, no load,VS3 = 0 V, VS5 = 5 V 6 10 μA
IVLDOINSDN Shutdown current, VLDOIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V 0.3 1 μA
INPUT CURRENT
IVDDQSNS Input current, VDDQSNS VVIN = 5 V, VS3 = VS5 = 5 V 1 3 5 μA
IVTTSNS Input current, VTTSNS VVIN = 5 V, VS3 = VS5 = 5 V –1 –0.25 1 μA
VTT OUTPUT
VVLDOIN = VVDDQSNS = 2.5 V 1.25
VVTTSNS Output voltage, VTT VVLDOIN = VVDDQSNS = 1.8 V 0.9 V
VVLDOIN = VVDDQSNS = 1.5 V 0.75
VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 0 A –20 20
VVTTTOL25 VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 1.5 A –30 30
VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 3 A –40 40
VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 0 A –20 20
Output votlage tolerance to VTTREF, VTT mV
VVTTTOL18 VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 1 A –30 30
VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 2 A –40 40
VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 0 A –20 20
VVTTTOL15 VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 1 A –30 30
3 3.8 6
IVTTOCLSRC Source current limit, VTT A
VVTT = 0 V 1.5 2.2 3
3 3.6 6
IVTTOCLSNK Sink current limit, VTT A
VVTT = VVDDQ 1.5 2.2 3
IVTTLK Leakage current, VTT –1 0.5 10 μA
VS3 = 0 V, VS5 = 5 V
IVTTSNSLK Leakage current, VTTSNS –1 0.01 1 μA
TA= 25°C, VS3 = VS5 = 0 V,
IDSCHRG Discharge current, VTT 10 17 mA
VVDDQSNS = 0 V, VVTT = 0.5 V
VTTREF OUTPUT
VVTTREF Output voltage, VTTREF V
VVTTREFTOL25 VVLDOIN = VVDDQSNS = 2.5 V, IVTTREF < 10 mA –20 20
Output voltage tolerance to VDDQSNS/2,
VVTTREFTOL18 VVLDOIN = VVDDQSNS = 1.8 V, IVTTREF < 10 mA –17 17 mV
VTTREF
VVTTREFTOL15 VVLDOIN = VVDDQSNS = 1.5 V, IVTTREF < 10 mA –15 15
IVTTREFOCL Source current limit, VTTREF VVTTREF = 0 V 10 20 30 mA
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Electrical Characteristics (continued)
TA= –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO/LOGIC THRESHOLD
Wake up 3.4 3.7 4
VVINUV UVLO threshold voltage, VIN V
Hysteresis 0.15 0.25 0.35
VIH High-level input voltage S3, S5 1.6 V
VIL Low-level input voltage S3, S5 0.3 V
VIHYST Hysteresis voltage S3, S5 0.2 V
IILEAK Logic input leakage current S2, S5, TA= 25°C –1 1 μA
THERMAL SHUTDOWN
Shutdown temperature 160
TSDN Thermal shutdown threshold °C
Hysteresis 10
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TJ− Junction Temperature − °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
−50 0 50 100 150
IVLDOINSDN − VLDOINSDN Supply Current − mA
G005
TJ− Junction Temperature − °C
10
15
20
25
30
−50 0 50 100 150
IDSCHRG − VTT Discharge Current − mA
G006
IVTT − VTT Load Current − A
0
1
2
3
4
5
6
7
8
9
10
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0
IVIN − VIN Supply Current − mA
G003
DDR2
VVTT = 1.8 V
TJ− Junction Temperature − °C
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
−50 0 50 100 150
IVLDOIN − VLDOIN Supply Current − mA
G004
TJ− Junction Temperature − °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−50 0 50 100 150
IVIN − VIN Supply Current − mA
G001
TJ− Junction Temperature − °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
−50 0 50 100 150
IVINSDN − VINSDN Supply Current − mA
G002
TPS51100
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SLUS600E –APRIL 2004–REVISED DECEMBER 2014
6.5 Typical Characteristics
Figure 1. VIN Supply Current vs Temperature Figure 2. VIN Shutdown Current vs Temperature
Figure 3. VIN Supply Current vs VTT Load Current Figure 4. VLDOIN Supply Current vs Temperature
Figure 5. VLDOIN Shutdown Current vs Temperature Figure 6. Discharge Current vs Temperature
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IVTTREF − VTTREF Load Current − mA
898
899
900
901
902
0 2 4 6 8 10
VVTTREF − VTTREF V
oltage − mV
G011
IVTTREF − VTTREF Load Current − mA
748
749
750
751
752
0 2 4 6 8 10
VVTTREF − VTTREF V
oltage − mV
G012
VVLDOIN = 1.5 V
IVTT − VTT Load Current − A
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
−3 −2 −1 0 1 2 3
VVTT − VTT Voltage − V
G009
VVLDOIN = 1.5 V
IVTTREF − VTTREF Load Current − mA
1.248
1.249
1.250
1.251
1.252
0 2 4 6 8 10
VVTTREF − VTTREF V
oltage − V
G010
IVTT − VTT Load Current − A
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
−4 −3 −2 −1 0 1 2 3 4
VVTT − VTT Voltage − V
G007
VVLDOIN = 2.5 V
VVLDOIN = 1.8 V
IVTT − VTT Load Current − A
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
−4 −3 −2 −1 0 1 2 3 4
VVTT − VTT Voltage − V
G008
VVLDOIN = 1.8 V
VVLDOIN = 1.5 V
VVLDOIN = 1.2 V
TPS51100
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Typical Characteristics (continued)
Figure 7. VTT Voltage Load Regulation vs VTT Load Current Figure 8. VTT Voltage Load Regulation vs VTT Load Current
(DDR) (DDR2)
Figure 9. VTT Voltage Load Regulation vs VTT Load Current Figure 10. VTTREF Voltage Load Regulation vs VTTREF
(DDR3) Load Current (DDR)
Figure 11. VTTREF Voltage Load Regulation vs VTTREF Figure 12. VTTREF Voltage Load Regulation vs VTTREF
Load Current (DDR2) Load Current (DDR3)
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G017
t − Time − 1 ms/div
VS5
(5 V/div)
VS3
(5 V/div)
VVTT
(0.5 V/div)
IVTT = IVTTREF = 0 A
VTTREF
(0.5 V/div)
f − Frequency − Hz
−40
−20
0
20
40
60
80
Gain − dB
Phase − °
10k 100k 1M 10M
180
135
90
45
0
−45
−90
G018
Phase
(−1 A)
Phase
(−0.1 A)
Gain
(−1 A)
Gain
(−0.1 A)
C1 = 2 × 10 mF
G015
t − Time − 10 ms/div
VVTT
(0.5 V/div)
VS3
(5 V/div)
VS5
(5 V/div)
VS5 = 5 V
IVTT = IVTTREF = 0 A
VTTREF
G016
t − Time − 1 ms/div
VVTTREF
(0.5 V/div)
VVTT
(0.5 V/div)
VS5
(5 V/div)
VS3
(5 V/div)
VS5 = 5 V
IVTT = IVTTREF = 0 A
G013
t − Time − 20 ms/div
VVTT (20 mV/div)
Offset 0.9 V
VVTTREF
(20 mV/div)
Offset 0.9 V
IVTT
(2 A/div)
VVLDOIN (50 mV/div)
Offset: 1.8 V
G014
t − Time − 10 ms/div
VVTTREF
(0.5 V/div)
VS3
(5 V/div)
VS5
(5 V/div)
VVTT (0.5 V/div)
VS3 = 0 V
IVTT = IVTTREF = 0 A
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Typical Characteristics (continued)
Figure 13. VTT Voltage Load Transient Response Figure 14. Startup Waveforms S5 Low-to-High
Figure 16. Shutdown Waveforms S3 High-to-Low
Figure 15. Startup Waveforms S3 Low-to-High
Figure 18. Bode Plot DDR Source
Figure 17. Shutdown Waveforms S3 and S5 High-to-Low
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l TEXAS INSTRUMENTS phase v phase v .. \ w x ‘ I X phase
f − Frequency − Hz
−40
−20
0
20
40
60
80
Gain − dB
Phase − °
10k 100k 1M 10M
180
135
90
45
0
−45
−90
G021
C1 = 2 × 10 mF
Phase
(1 A)
Phase
(0.1 A)
Gain
(1 A)
Gain
(0.1 A)
f − Frequency − Hz
−40
−20
0
20
40
60
80
Gain − dB
Phase − °
10k 100k 1M 10M
180
135
90
45
0
−45
−90
G019
C1 = 2 × 10 mF
Phase
(1 A)
Phase
(0.1 A)
Gain
(1 A)
Gain
(0.1 A)
f − Frequency − Hz
−40
−20
0
20
40
60
80
Gain − dB
Phase − °
10k 100k 1M 10M
180
135
90
45
0
−45
−90
G020
C1 = 2 × 10 mF
Phase
(−1 A)
Phase
(−0.1 A)
Gain
(−1 A)
Gain
(−0.1 A)
TPS51100
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
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Typical Characteristics (continued)
Figure 19. Bode Plot DDR Sink Figure 20. Bode Plot DDR2 Source
Figure 21. Bode Plot DDR2 Sink
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B0319-01
2
8
10
9
6
3
4
VIN
S5
GND
VDDQSNS VLDOIN
PGND
VTT
TPS51100DGQ
5
VTTREF
VTTSNS
7
S3
+
+
+
+
+
+
+
+
ENVTT
3.7V/3.5V
HalfDDQ
VinOK
5V/10%
–5V/10%
PGOOD
1
ENREF
ENVTT
ENREF
–
–
–
–
–
–
TPS51100
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SLUS600E –APRIL 2004–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The TPS51100 is a sink / source double date rate (DDR) termination regulator with VTTREF buffered reference
output.
7.2 Functional Block Diagram
Figure 22. Simplified Block Diagram
7.3 Feature Description
7.3.1 VTT Sink/Source Regulator
The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low-external-
components systems where space is at premium, such as notebook PC applications. The TPS51100 integrates a
high-performance, low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This
VTT linear regulator employs an ultimate fast-response feedback loop so that small ceramic capacitors are
enough to keep tracking to the VTTREF within ±40 mV under all conditions, including fast load transient. To
achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be
connected to the positive node of the VTT output capacitor(s) as a separate trace from the high-current line from
VTT.
7.3.2 VTTREF Regulator
The VTTREF block consists of an on-chip 1/2 divider, low-pass filter (LPF), and buffer. This regulator can source
current up to 10 mA. Bypass VTTREF to GND using a 0.1-μF ceramic capacitor to ensure stable operation.
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Feature Description (continued)
7.3.3 Soft-Start
The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged
with low and constant current that gives linear ramp-up of the output voltage. The current-limit threshold is
changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the
current limit level is 2.2 A. When VTT rises above (VTTREF – 5%) or falls below (VTTREF + 5%), the current
limit level switches to 3.8 A. The thresholds are typically VTTREF ±5% (from outside regulation to inside) and
±10% (when it falls outside). The soft-start function is completely symmetrical, and it works not only from GND to
VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high-impedance state
during the S3 state (S3 = low, S5 = high), and its voltage can be up to VDDQ voltage, depending on the external
condition. Note that VTT does not start under a full-load condition.
7.3.4 VTT Current Protection
The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output
voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage.
7.3.5 VIN UVLO Protection
For VIN undervoltage lockout (UVLO) protection, the TPS51100 monitors VIN voltage. When the VIN voltage is
lower than UVLO threshold voltage, the VTT regulator is shut off. This is a non-latch protection.
7.3.6 Thermal Shutdown
TPS51100 monitors its temperature. If the temperature exceeds the threshold value, typically 160°C, the VTT
and VTTREF regulators are shut off. This is also a non-latch protection.
7.4 Device Functional Modes
7.4.1 S5 Control and Soft-Off
The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals, respectively. Both VTTREF and
VTT are turned on at the S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left
high-impedance in the S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and
discharged to ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low).
Table 1. S3 and S5 Control Table
STATE S3 S5 VTTREF VTT
S0 H H 1 1
S3(1) L H 1 0 (Hi-Z)
S4/S5(1) L L 0 (discharge) 0 (discharge)
(1) In case S3 is forced to H and S5 to L, VTTREF is discharged and VTT is at Hi-Z state. This condition
is not recommended.
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1
2
3
4
10
9
8
7
VIN
S5
GND
S3
VDDQSNS
VLDOIN
PGND
VTT
TPS51100DGQ
C2
0.1 µF
5 6VTTREFVTTSNS
C1
2 x 10 µF
S3
VTTREF
5V_IN
S5
Capacitor
C1
C2
Manuf
TDK
TDK
Part Number
C2012JB0J106K
C1608JB1H104K
TPS51100
www.ti.com
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51100 is typically used as a sink / source tracking termination regulator, witch converter a voltage from
VTT.
8.2 Typical Application
Figure 23. TPS51100 5-V Input / 1.8-V Output Reference Design
8.2.1 Design Requirements
Table 2. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUE
VIN 4.75 V to 5.25 V
VDDQSNS, VLDOIN 1.8 V
Output Current ±3 A
8.2.2 Detailed Design Procedure
Table 3. Design Specifications
REFERENCE SPECIFICATION MANUFACTURER PART NUMBER
DESIGNATOR
C1 10-μf, 6.3-V, X5R, 2012 (0805) TDK C2012JB0J106K
C2 0.1-μf, 50-V, X5R, 1608 (0603) TDK C1608JB1H104K
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS51100
l TEXAS INSTRUMENTS
G015
t − Time − 10 ms/div
VVTT
(0.5 V/div)
VS3
(5 V/div)
VS5
(5 V/div)
VS5 = 5 V
IVTT = IVTTREF = 0 A
VTTREF
G014
t − Time − 10 ms/div
VVTTREF
(0.5 V/div)
VS3
(5 V/div)
VS5
(5 V/div)
VVTT (0.5 V/div)
VS3 = 0 V
IVTT = IVTTREF = 0 A
OUT VTT
SS
VTTOCL
C V
t
I
æ ö
´
=ç ÷
è ø
TPS51100
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
www.ti.com
8.2.2.1 Output Capacitor
For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. Attach
two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ,
insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time
constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR.
Soft-start duration, tSS, is also a function of this output capacitance. Where ITTOCL = 2.2 A (typ), tSS can be
calculated as,
(1)
8.2.2.2 Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the part, transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or more) ceramic
capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at
VTT. In general, use 1/2 COUT for the input.
8.2.2.3 VIN Capacitor
Add a ceramic capacitor with a value between 1 μF and 4.7 μF placed close to the VIN pin, to stabilize 5 V from
any parasitic impedance from the supply.
8.2.3 Application Curves
Figure 24. Start-Up Waveforms S5 Low-to-High Figure 25. Start-Up Waveforms S3 Low-to-High
14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: TPS51100
l TEXAS INSTRUMENTS
G016
t − Time − 1 ms/div
VVTTREF
(0.5 V/div)
VVTT
(0.5 V/div)
VS5
(5 V/div)
VS3
(5 V/div)
VS5 = 5 V
IVTT = IVTTREF = 0 A
TPS51100
www.ti.com
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
Figure 26. Shutdown Waveforms S3 High-to-Low
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS51100
l TEXAS INSTRUMENTS
TPS51100
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
www.ti.com
9 Power Supply Recommendations
TPS51100 is designed for a sink / source double date rate (DDR) termination regulator with VTTREF buffered
reference output. Supply input voltage (VIN) support voltage from 4.75 V to 5.25 V; VLDOIN input voltage
supports from 1.2 V to 3.6 V.
10 Layout
10.1 Layout Guidelines
Consider the following points before the layout of TPS51100 design begins.
• The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with a short and
wide connection.
• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of the ground trace between the GND
pin and the output capacitor(s).
• Consider adding an LPF at VTTSNS in case the ESR of the VTT output capacitor(s) is larger than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
• The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together,
avoiding common impedance to the high-current path of the VTT source/sink current.
• The GND (signal GND) pin node represents the reference potential for the VTTREF and VTT outputs.
Connect GND to the negative nodes of the VTT capacitor(s), VTTREF capacitor, and VDDQ capacitor(s) with
care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single
point connection between them.
• In order to remove heat from the package effectively, prepare the thermal land and solder to the package
thermal pad. The wide trace of the component-side copper, connected to this thermal land, helps heat
spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder-side
ground plane(s) should be used to help dissipation.
16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: TPS51100
i Tans INSTRUMENTS Routing (under 2nd layer) Power GND plane ‘ TPS511OO (2"d layer) 85 $3 Connection to internal Power GND plane Mnmam .IA
( )
J(max) A(max)
PKG
JA
T T
W-
=q
DSNK VTT VTT
W V I= ´
( )
DSRC VLDOIN VTT VTT
W V V I= - ´
TPS51100
www.ti.com
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
10.2 Layout Example
NOTES: 1. The positive terminal of each output capacitor should be directly connected to VTT of the IC; do not use a VIA.
2. The negative terminal of each output capacitor should be directly connected to GND of the IC; do not use a VIA.
3. VIAs
VIA between 1st and 2nd layers
VIA between 1st and other layers under 2nd
4. Rs and Cs with dotted outlines are options.
Figure 27. TPS51100 PCB Layout Guideline
10.3 Thermal Considerations
As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generates power
dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT times VTT
current becomes the power dissipation, WDSRC.
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be
decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and
WDSNK, is calculated by:
(3)
Because the device does not sink and source the current at the same time and IVTT varies rapidly with time, the
actual power dissipation that must be considered for thermal design is an average over the thermal relaxation
duration of the system. Another power consumption is the current used for internal control circuitry from the VIN
supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This
power must be effectively dissipated from the package. Maximum power dissipation allowed to the package is
calculated by,
(4)
where
TJ(max) is 125°C
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS51100
l TEXAS INSTRUMENTS
TPS51100
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
www.ti.com
Thermal Considerations (continued)
TA(max) is the maximum ambient temperature in the system
θJA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced
PowerPAD package that has an exposed die pad underneath the body. For improved thermal performance, this
die pad must be attached to the ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with
two vias without air flow. It can be improved by using larger thermal land and/or increasing the number of vias.
For example, assuming a 3 mm × 3 mm thermal land with four vias without air flow, it is 45.4°C/W. Further
information about the PowerPAD package and its recommended board layout is described in the PowerPAD
Thermally Enhanced Package application report (SLMA002). This document is available at www.ti.com.
18 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: TPS51100
l TEXAS INSTRUMENTS
TPS51100
www.ti.com
SLUS600E –APRIL 2004–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS51100
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS51100DGQ ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 51100
TPS51100DGQG4 ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 51100
TPS51100DGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 51100
TPS51100DGQRG4 ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 51100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS51100DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51100DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS51100DGQ DGQ HVSSOP 10 80 330 6.55 500 2.88
TPS51100DGQG4 DGQ HVSSOP 10 80 330 6.55 500 2.88
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
HVSSOP - 1.1 mm max height
TM
PowerPADDGQ 10
PLASTIC SMALL OUTLINE
3 x 3, 0.5 mm pitch
4224775/A
www.ti.com
PACKAGE OUTLINE
C
5.05
4.75 TYP
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.23
0.13 TYP
0 - 8
0.15
0.05
1.83
1.63
1.89
1.69
0.25
GAGE PLANE
0.7
0.4
A
3.1
2.9
NOTE 3
B3.1
2.9
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
PowerPAD is a trademark of Texas Instruments.
TM
110
0.08 C A B
6
5
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.700
EXPOSED
THERMAL PAD
4
1
5
8
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(2.2)
NOTE 9
(3.1)
NOTE 9
(1.83)
(1.89)
SOLDER MASK
OPENING
( 0.2) TYP
VIA
(1.3) TYP
(1.3)
TYP
(R0.05) TYP
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:15X
1
56
10
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
TM
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
10X (1.45)
10X (0.3)
8X (0.5)
(4.4)
(1.83)
(1.89)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
1.55 X 1.600.175
1.67 X 1.730.150
1.83 X 1.89 (SHOWN)0.125
2.05 X 2.110.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
SYMM
SYMM
1
56
10
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
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