Fiche technique pour ZCU106 User Guide de AMD

(I XILINX.
ZCU106 Evaluation Board
User Guide
UG1244 (v1.4) October 23, 2019
(I XILINXa Send Feed back
ZCU106 Board User Guide 2
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Section Revision Summary
10/23/2019 Version 1.4
Table 2 - 1 Updated the part number for PS-side DDR4 SODIMM
socket.
PS-Side: DDR4 SODIMM Socket Corrected the part number and revised the description.
09/16/2019 Version 1.3
General updates • Corrected UTIL_3V3 net name.
• Removed mention of USB cable being in kit.
• Updated HDMI block diagram.
• Deleted obsolete board ID encoding description.
11/08/2018 Version 1.2
General updates Revised PS-side DDR4 SODIMM bit width value
throughout.
10/03/2018 Version 1.1
Electrostatic Discharge Caution Revised electrostatic discharge caution.
Figure 2-2 Revised to reflect current board revision.
Table 2 - 2 Revised to reflect current board revision.
PS-Side: DDR4 SODIMM Socket Added reference to Zynq UltraScale+ MPSoC Data
Sheet: DC and AC Switching Characteristics (DS925).
PL-Side: DDR4 Component Memory
Added information on the memory components and a
reference to Zynq UltraScale+ MPSoC Data Sheet: DC
and AC Switching Characteristics (DS925).
Table 3 - 3 2 Revised table note.
Table 3 - 3 5 Replaced pin AP8 with AE15.
Table 3 - 3 8 Revised pin names.
PCI Express Endpoint Connectivity Revised third paragraph.
Appendix B, Xilinx Constraints File Revised appendix title and removed constraints file
listing.
Appendix C, Regulatory and Compliance Information Added answer record information.
03/28/2018 Version 1.0
Initial Xilinx release.
(I XILINXa Send Feed back
ZCU106 Board User Guide 3
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chapter 2: Board Setup and Configuration
Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrostatic Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Default Jumper and Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Installing the ZCU106 Board in a PC Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MPSoC Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Quad SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Chapter 3: Board Component Descriptions
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Zynq UltraScale+ XCZU7EV MPSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PS-Side: DDR4 SODIMM Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PL-Side: DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PSMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Quad SPI Flash Memory (MIO 0–12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
USB 3.0 Transceiver and USB 2.0 ULPI PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
EMIO Arm Trace Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
GEM3 Ethernet (MIO 64-77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
(I XILINXa Send Feed back
ZCU106 Board User Guide 4
UG1244 (v1.4) October 23, 2019 www.xilinx.com
10/100/1000 MHz Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Ethernet PHY Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
CP2108 USB UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
GPIO (MIO 13, 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
I2C0 (MIO 14-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
I2C1 (MIO 16-17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
UART0 (MIO 18-19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
UART1 (MIO 20-21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
GPIO (MIO 22-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
CAN1 (MIO 24-25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Platform Management Unit GPI (MIO 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
DisplayPort DPAUX (MIO 27-30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PMU GPO (MIO 32-37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
HDMI Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SDI Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AES3 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
SFP/SFP+ Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
SFP/SFP+ Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Prototype Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
User I2C0 Receptacle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Power and Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
GTH Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
PS GTR Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
FPGA Mezzanine Card Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
FMC HPC0 Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
FMC HPC1 Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Cooling Fan Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
VADJ_FMC Power Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
TI MSP430 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Appendix A: VITA 57.1 FMC Connector Pinouts
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Appendix B: Xilinx Constraints File
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix C: Regulatory and Compliance Information
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
(I XILINXa Send Feed back
ZCU106 Board User Guide 5
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
(I X|L|NX.
ZCU106 Board User Guide 6
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1
Introduction
Overview
The ZCU106 is a general purpose evaluation board for rapid-prototyping based on the
ZU7EV silicon part and package in the 16 nm FinFET Zynq® UltraScale+™ MPSoC. The
ZU7EV device integrates a quad core Arm® Cortex™-A53 processing system (PS) and a dual
core Arm Cortex-R5F real-time processor, which provides application developers an
unprecedented level of heterogeneous multiprocessing. The ZCU106 evaluation board
provides a flexible prototyping platform with high-speed DDR4 memory interfaces, FMC
expansion ports, multi-gigabit per second serial transceivers, video codec unit (VCU),
several peripheral interfaces, and FPGA fabric for customized designs.
Additional Resources
See Appendix D, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the ZCU106 evaluation board.
(I XILINX¢ pmmtm u, mm) m. 1mm .. ‘ mm 6910 m cm". nu mum “ m m: m I me I m asp] 5n n ‘ ‘ ‘ ‘ 1mm ‘ , 'm/wn/mnu mm m 227 ‘ m m , mama", mm m- m 5n; (XCZU7EV-2PPVC1155) 5121 m- 7 m-pliypnxt mu- m m. .m 225 a?» m. r .m in! .m i‘ .m u an): 55 m. k... x. .m 224 mama". m 223 m m. \ \ x \ \ \ \ \ x , Bultmu , m m 1 [in mm: x‘l’ Send Feed back
ZCU106 Board User Guide 7
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1: Introduction
Block Diagram
The ZCU106 board block diagram is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Figure 1-1: ZCU106 Evaluation Board Block Diagram
Bank 503
PS DDR4 x64
X19000-110218
(I X|L|NXm Send Feed back
ZCU106 Board User Guide 8
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1: Introduction
Board Features
The ZCU106 evaluation board features are listed here. Detailed information for each feature
is provided in Component Descriptions in Chapter 3.
• XCZU7EV-2, FFVC1156 package
•PL V
CCINT for range in data sheet
• Form factor for PCIe® Gen[1-3]x4 endpoint (PL GTH transceiver), Micro-ATX chassis
footprint
• Configuration from Quad SPI
• Configuration from SD card
• Configuration over JTAG with platform cable USB header
• Configuration over JTAG with Arm 20-pin header
• Configuration over USB-to-JTAG bridge
•Clocks
°USER_MGT_SI570
°PL_74.25M, PL_125M, PL_300M
°USER_SMA_MGT
°GTR_DP, GTR_USB3, GTR_SATA
°PS_REF_CLK
•PS DDR4 64-bit SODIMM
• PL DDR4 64-bit component (4x16-bit)
•PS-GTR assignment
°DisplayPort (two GTRs)
°USB3 (one GTR)
°SATA (one GTR)
• PL GTH transceiver assignment (20 total)
°High-definition multimedia interface (HDMI®) (three GTH transceivers)
°FMC HPC1 DP (one GTH transceiver)
°PCIe (four GTH transceivers)
°SDI (one GTH transceiver)
°SMA (one GTH transceiver)
(I XILINXE Send Feed back
ZCU106 Board User Guide 9
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1: Introduction
°SFP+ (two GTH transceivers)
°FMC HPC0 DP (eight GTH transceivers)
• PL FMC HPC0 connectivity - full LA bus
• PL FMC HPC1 connectivity - partial LA bus
•PS MIO: dual Quad SPI
• PS MIO: two channels of quad-UART bridge
•PS MIO: CAN
• PS MIO: I2C shared across PS and PL
•PS MIO: SD
• PS MIO: DisplayPort
• PS MIO: system controller I/F
•PS MIO: Ethernet
•PS MIO: USB3
• PS-side user LED (one)
• PS-side user pushbutton (one)
• PL-side user LEDs (eight)
• PL-side user DIP switch (8-position)
• PL-side user pushbuttons (five)
• PL-side CPU reset pushbutton
•PL-side PMOD headers
• PL-side bank 0 PROG_B pushbutton
• Security - PSBATT button battery backup
• SYSMON (previously XADC), prototype header
• Operational switches (power on/off, PROG_B, boot mode DIP switch)
• Operational status LEDs (power status, INIT, DONE, PG, JTAG status, DDR power good)
• Power management
(I XILINXE Send Feed back
ZCU106 Board User Guide 10
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1: Introduction
The ZCU106 provides designers a rapid prototyping platform using the
XCZU7EV-2FFVC1156 device. The ZU7EV contains many PS hard block peripherals exposed
through the multi-use I/O (MIO) interface and several FPGA programmable logic (PL),
high-density (HD), and high-performance (HP) banks. Tabl e 1- 1 lists a summary of the
resources available within the ZU7EV. A feature set overview, description, and ordering
information is provided in the Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891)
[Ref 1].
Board Specifications
Dimensions
Height: 7.323 inch (18.60 cm)
Length: 9.5 inch (24.13 cm)
Thickness: 0.062 inch ±0.005 inch (0.157 cm ±0.0127 cm)
Note: A 3D model of this board is not available.
IMPORTANT: The ZCU106 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI
Express® card.
See ZCU106 board documentation for XDC listing, schematics, layout files, board outline
drawings, etc.
Table 1-1: Zynq UltraScale+ MPSoC ZU7EV Features and Resources
Feature Resource Count
HD banks Two banks, total of 48 pins
HP banks Six banks, total of 312 pins
MIO banks Three banks, total of 78 pins
PS-GTR transceivers (6 Gb/s) Four PS-GTR transceivers
GTH transceivers (16.3 Gb/s) 20 GTH transceivers
VCU One
PCIe hard block Gen1/2/3/4 x4 Two
Logic cells 504K
CLB flip-flops 460.8K
Distributed RAM 6.2 Mb
Total block RAM 11 Mb
UltraRAM 27 Mb
DSP slices 1728
(I XILINXE Send Feed back
ZCU106 Board User Guide 11
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 1: Introduction
Environmental
Temperature
Operating: 0°C to +45°C
Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
(I X|L|NX. Send Feed back
ZCU106 Board User Guide 12
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2
Board Setup and Configuration
Board Component Location
Figure 2-1 shows the ZCU106 board component locations. Each numbered component
shown in the figure is keyed to Tab le 2- 1. Ta ble 2 -1 identifies the components, references
the respective schematic (0381770) page numbers, and links to a detailed functional
description of the components and board features in Chapter 3.
IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the
board.
IMPORTANT: There could be multiple revisions of this board. The specific details concerning the
differences between revisions are not captured in this document. This document is not intended to be
a reference design guide and the information herein should not be used as such. Always refer to the
schematic, layout, and XDC files of the specific ZCU106 version of interest for such details.
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result
in total or intermittent failures. Always follow ESD-prevention procedures when removing and
replacing components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the
equipment end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components
from ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit
board or the connectors.
• Put the adapter down only on an antistatic surface such as the bag supplied in your kit.
(I XILINXa Send Feedback
ZCU106 Board User Guide 13
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
• If you are returning the adapter to Xilinx Product Support, place it back in its antistatic
bag immediately.
X-Ref Target - Figure 2-1
Figure 2-1: ZCU106 Evaluation Board Components
1
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
2
35
6
7
10
8
9
11
12
16
17
19
35
13
14
15
18
20
21
27
48
14
12
28
29
30
26
31
32
34
35
46
37
40
44
45
39
43
42
38
49
47
23
24
33
25
41
28
4
36
22
X19001-022218
(I XILINXa Send Feed back
ZCU106 Board User Guide 14
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Table 2-1: ZCU106 Board Component Locations
Callout
Number Ref. Des. Feature ([B] = bottom of board) Notes Schematic
Page
1U1
Zynq UltraScale+ XCZU7EV MPSoC,
GTH Transceivers, PS GTR Transceivers XCZU7EV-2FFVC1156
2J1
PS-Side: DDR4 SODIMM Socket, with
DDR4 SODIMM
LOTES ADDR0067-P001A,
Micron MTA4ATF51264HZ-2G6E1 24
3U2,
U99-U101
PL-Side: DDR4 Component Memory,
(4 Gb) Micron MT40A256M16GE-075E 26-29
4U119,
U120 Quad SPI Flash Memory (MIO 0–12) [B] Micron MT25QU512ABB8ESF-0SIT 53
5 U116, J96 USB 3.0 Transceiver and USB 2.0 ULPI
PHY (USB 3.0 A connector)
SMSC USB3320-EZK, KYCON
KMMX-AB10-SMT1SB30TR 58
6 J100 SD Card Interface Hirose DMIAA-SF-PET(21) 54
7 U152, J2 Programmable Logic JTAG
Programming Options
FTDI FT232HL-REEL,
Hirose ZX62D-AB-5P8 22
8U69
SI5341B 10 Independent Output
Any-Frequency Clock Generator [B] Silicon Labs SI5341B-B05071-GM 44
9U42Programmable User Clock [B] Silicon Labs SI570BAB001614DG 45
10 U56 Programmable User MGT Clock,
Cooling Fan Connector Silicon Labs SI570BAB000544DG 45
11 U20 SFP/SFP+ Clock Recovery [B] Silicon Labs SI5328B-C-GMR 46
12 U98, P12
GEM3 Ethernet (MIO 64-77),
10/100/1000 MHz Tri-Speed Ethernet
PHY
TI DP83867IRPAP,
Halo HFJ11-1G01E-L12RL 59
13 U40, J83 CP2108 USB UART Interface Silicon Labs CP2108-B02-GM,
Hirose ZX62D-AB-5P8 47
14 U94, P7 HDMI Video Output [B] TI SN65DP159RGZ, TE Connectivity
1888811-1 40
15 U19, P7 HDMI Video Output TI TMDS181IRGZT,
TE Connectivity 1888811-1 41
16 U60, U61,
U97
I2C0 (MIO 14-15), I2C0 bus switch and
two expanders [B]
TI PCA9544ARGYR,
Two each TI TCA6416APWR 64
17 U34, U135 I2C1 (MIO 16-17), I2C1 bus switches
[B] Two each TI TCA9548APWR 65
18 P1, P2 SFP/SFP+ Connectors Molex 74441-0010 38-39
19 U41 TI MSP430 System Controller [B] TI MSP430F5342 43
20 J87 User PMOD GPIO Headers SULLINS PBC36DAAN 62
21 J160, J55 User PMOD GPIO Headers SULLINS PPPC062LJBN-RC 56
22 DS37-DS44 User I/O, Power and Status LEDs GPIO LEDs, GREEN 0603 60
23 SW13 User I/O DIP switch C&K SDA08H1SBD 60
(I XILINXa Send Feed back
ZCU106 Board User Guide 15
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
24 SW14-
SW18 User I/O pushbuttons E-switch TL3301EP100QG placed in
N,S,W,E,C pattern 60
25 SW20 User I/O reset pushbutton switch E-switch TL3301EP100QG 60
26 SW8 Switches system controller DIP 5-pole C&K SDA05H1SBD 43
27 SW3, SW4 System Reset Pushbuttons E-switch TL3301EP100QG 12
28 U122, J98 CAN1 (MIO 24-25) [B],
2X4 male header
TI SN65HVD232,
SULLINS PBC36DAAN 57
29 SW1 Power On/Off Slide Switch C&K 1201M2S3AQE2 66
30 J52 Power On/Off Slide Switch MOLEX 39-30-1060 66
31 SW5 Program_B Pushbutton E-switch TL3301EP100QG 12
32 J5 FPGA Mezzanine Card Interface,
FMC HPC0 Connector J5 Samtec ASP_134486_01 30-33
33 J4 FPGA Mezzanine Card Interface,
FMC HPC1 Connector J4 Samtec ASP_134486_01 34-37
34 P6 EMIO Arm Trace Port MICTOR 2-5767004-2 61
35 – Board Power System Maxim regulators 67-92
36 P3 PCI Express Endpoint Connectivity FCI 10061913-101CLF 48
37 P11 DisplayPort DPAUX (MIO 27-30) MOLEX 0472720001 51-52
38 J84 Monitoring Voltage and Current ASSMANN AWHW16G-0202-T-R 64
39 J92 Programmable Logic JTAG
Programming Options TYCO 5103308-2 43
40 J6 Programmable Logic JTAG
Programming Options ASSMANN AWHW20G-0202-T-R 23
41 U108 HDMI Clock Recovery [B] Silicon Labs SI5324C-C-GMR 42
42 J3 Prototype Header SULLINS PBC36DAAN 63
43 J74/J73,
J72/J42
SMA, MGTH interface RX,
TX SMA connectors ROSENBERGER 32K10K-400L5 45
44 J69, J70 AES3 Audio Samtec HDBNC–J–P–GN–RA–BH2 50
45 J10, J68 SDI Video Samtec HDBNC–J–P–GN–RA–BH2 49
46 SW6 Switches MPSoC PS mode DIP 4-pole C&K SDA04H1SBD 12
47 SW9 Ethernet PHY Reset E-switch TL3301EP100QG 59
48 J79/J80 User SMA MGT Clock ROSENBERGER 32K10K-400L5 45
49 J93 SYSMON 2X6 vertical male pin header SULLINS PBC36DAAN 3
Table 2-1: ZCU106 Board Component Locations (Cont’d)
Callout
Number Ref. Des. Feature ([B] = bottom of board) Notes Schematic
Page
(I XILINXa Send Feedback
ZCU106 Board User Guide 16
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Default Jumper and Switch Settings
Figure 2-2 shows the ZCU106 board jumper header and DIP switch locations. Each
numbered component shown in the figure is keyed to Table 2 -2 or Tabl e 2- 3 (for default
switch settings). Both tables reference the respective schematic (0381770) page numbers.
X-Ref Target - Figure 2-2
Figure 2-2: Board Jumper Header and DIP Switch Locations
28
5
67
27
30
10
9
31
3
12
11
2
1
4
14
32
13
16
15
17
18
19
21
20
22
24
26
33
29
X19002-083118
(I XILINXa Send Feed back
ZCU106 Board User Guide 17
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Jumpers
Table 2-2: Default Jumper Settings
Number Ref. Des. Function Default Schematic Page
1J85
POR_OVERRIDE
• 1-2: Enable
•2-3: Disable
2-3 3
2J12
SYSMON I2C address
• Open: SYSMON_VP_R floating
• 1-2: SYSMON_VP_P pulled down
1-2 3
3J13
SYSMON I2C address
• Open: SYSMON_VN_R floating
• 1-2: SYSMON_VP_N pulled down
1-2 3
4J90
SYSMON VREFP
• 1-2:1.25V VREFP connected to FPGA
•2-3: VREFP connected to GND
1-2 3
5J20
Reset sequencer PS_POR_B
• Open: Sequencer does not control PS_POR_B
• 1-2: Sequencer can control PS_POR_B
1-2 12
6J21
Reset sequencer PS_SRST_B
• Open: Sequencer does not control PS_SRST_B
• 1-2: Sequencer can control PS_SRST_B
1-2 12
7J22
Reset sequencer inhibit
• Open: Sequencer normal operation
• 1-2: Sequencer inhibit (resets stay asserted)
Open 12
9J14
Arm® debug VTREF
• Open: VTREF floating
• 1-2: VTREF = VCCOPS3 (1.8V)
1-2 22
10 J15
Arm debug VSUPPLY
• Open: VSUPPLY floating
• 1-2: VSUPPLY = VCCOPS3 (1.8V)
Open 22
11 J56
VCCO_PSDDR_504 select
• 1-2: Switched DDR4 VDDQ
• 3-4: Direct DDR4 VDDQ
1-2 24
12 J159
DDR4 reset suspend enable
• 1-2: Suspend disabled (gate bypass)
• 2-3: Suspend enabled
1-2 24
13 J16 SFP0 enable 1-2 37
(I XILINXa Send Feed back
ZCU106 Board User Guide 18
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
14 J62
SFP0 TX bandwidth
• 1-2: Full bandwidth
• 2-3: Low bandwidth
2-3 37
15 J63
SFP0 TX bandwidth
• 1-2: Full bandwidth
• 2-3: Low bandwidth
2-3 37
16 J17 SFP1 enable 1-2 38
17 J64
SFP1 TX bandwidth
• 1-2: Full bandwidth
• 2-3: Low bandwidth
2-3 38
18 J65
SFP1 TX bandwidth
• 1-2: Full bandwidth
• 2-3: Low bandwidth
2-3 38
19 J76
MSP430 programming
•1-2: Reset to GPIO
• 3-4: Test to GPIO
Open 42
20 J162
PCIe PRSNT select
•1-2: x1
•3-4: x4
•5-6: GND
• Open: card defined
Open 47
21 J108
SD level shifter internal reference
• 1-2: 3.3V reference
•2-3: GND
1-2 53
22 J110
CVBUS select
• Jumper off: device mode
• Jumper on: host mode
Open 57
24 J112
Shield GND select
•1-2: Capacitor
•2-3: GND
1-2 57
26 J113
Device/host or OTG select
•1-2: Device or host
•2-3: OTG
1-2 57
27 J88
Arm trace VTREF
• 1-2: 3.3V
•Open: 0V
Open 60
Table 2-2: Default Jumper Settings (Cont’d)
Number Ref. Des. Function Default Schematic Page
(I XILINXa Send Feed back
ZCU106 Board User Guide 19
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Switches
28 J38
Arm trace power
• 1-2: 3.3V
•Open: 0V
1-2 60
29 J153
Power inhibit
• Open: Rails power on normally
• 1-2: All rails (except UTIL) OFF
Open 65
Table 2-2: Default Jumper Settings (Cont’d)
Number Ref. Des. Function Default Schematic Page
Table 2-3: Default Switch Settings
Number Ref. Des. Function Default Schematic
Page
30
SW6
Note: For this DIP switch, in relation
to the arrow, moving the switch
toward the label ON is a 0. DIP switch
labels 1 through 4 are equivalent to
mode pins 0 through 3.
Switch PS_MODE select
12
(ON = pull down, OFF = pull up)
1: PS_MODE0 On
2: PS_MODE1 On
3: PS_MODE2 On
4: PS_MODE3 On
31
SW8
Note: For this DIP switch, in relation
to the arrow, moving the switch
toward the label ON is a 0. 1 through
5 are tied to MSP430 U41 GPIO[1:5].
MSP430 GPIO
42
1: SW0 Off
2: SW1 Off
3: SW2 Off
4: SW3 Off
5: SW4 Off
32 SW13 GPIO All Off 59
33 SW1 Main power switch Off 65
(I X|L|NXm Send Feed back
ZCU106 Board User Guide 20
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Installing the ZCU106 Board in a PC Chassis
Installation of the ZCU106 board inside a computer chassis is required when developing or
testing PCI Express® functionality. When the ZCU106 board is installed in the PCIe® slot,
power is provided from the ATX power supply 4-pin peripheral connector through the ATX
adapter cable (Figure 2-3), which is plugged into J52 on the ZCU106 board. The Xilinx® part
number for this cable is 2600304. See [Ref 25] for ordering information.
To install the ZCU106 board in a PC chassis:
1. On the ZCU106 board, remove the seven screws retaining the six rubber feet with their
standoffs, and the PCIe bracket. Reinstall the PCIe bracket using two of the previously
removed screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instructions provided with the PC.
4. Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the
chassis) by removing the screws on the top and bottom of the cover.
IMPORTANT: The ZCU106 board height exceeds the standard PCIe board dimension, so the PC chassis
top cover should remain off while using the ZCU106.
5. Plug the ZCU106 board into an open PCIe expansion slot.
6. Install the top mounting bracket screw into the PC expansion cover retainer bracket to
secure the ZCU106 board in its slot.
7. Connect the ATX power supply to the ZCU106 board using the ATX power supply
adapter cable shown in Figure 2-3.
a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J52 on the ZCU106
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the
4-pin adapter cable connector.
X-Ref Target - Figure 2-3
Figure 2-3: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral
Power Connector
To J52 on ZCU106 Board
•••••••••••••
(I XILINXa Send Feed back
ZCU106 Board User Guide 21
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the ZCU106 board power
connector J52. The ATX 6-pin connector has a different pin out than J52. Connecting an ATX 6-pin
connector into J52 damages the ZCU106 evaluation board and voids the board warranty.
8. Slide the ZCU106 board power switch SW1 to the ON position. The PC can now be
powered on.
MPSoC Device Configuration
Zynq UltraScale+ XCZU7EV MPSoC devices use a multi-stage boot process as described in
the “Boot and Configuration” chapter of the Zynq UltraScale+ MPSoC Technical Reference
Manual (UG1085) [Ref 3]. Switch SW6 configuration option settings are listed in Ta bl e 2-4.
JTAG
Vivado® Design Suite, SDK, or third-party tools can establish a JTAG connection to the Zynq
UltraScale+ MPSoC device through one of these provided JTAG interfaces:
• Xilinx platform USB or cable PC4 connector (J8)
• Arm 20-pin JTAG connector (J6)
• FTDI FT232HL USB-to-JTAG bridge U152 with micro-USB connector (J2)
Table 2-4: Switch SW6 Configuration Option Settings
Boot Mode Mode Pins [3:0] Mode SW6 [4:1]
JTAG 0000 ON,ON,ON,ON
QSPI32 0010(1) ON,ON,OFF,ON
SD 1110 OFF,OFF,OFF,ON
Notes:
1. Default switch setting.
2. For DIP SW6, in relation to the arrow, moving the switch toward the label ON is a 0. DIP switch labels 1 through
4 are equivalent to mode pins 0 through 3.
(I XILINXa Send Feed back
ZCU106 Board User Guide 22
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 2: Board Setup and Configuration
Quad SPI
To boot from the dual Quad SPI nonvolatile configuration memory:
1. Store a valid Zynq UltraScale+ MPSoC boot image in the Quad SPI flash devices
connected to the MIO Quad SPI interface.
2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Ta ble 2-4 for Quad
SPI32.
3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in
Figure 2-1.
SD
To boot from an SD card:
1. Store a valid Zynq UltraScale+ MPSoC boot image file on to an SD card (plugged into SD
socket J100) connected to the MIO SD interface.
2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Ta ble 2-4 for SD.
3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in
Figure 2-1.
See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more
information about Zynq UltraScale+ MPSoC configuration options.
(I X|L|NX.
ZCU106 Board User Guide 23
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed functional description of the board’s components and
features. Table 2 -1 identifies the components, references the respective schematic page
numbers, and links to the corresponding detailed functional description in this chapter.
Component locations are shown in Tabl e 2- 1.
Component Descriptions
Zynq UltraScale+ XCZU7EV MPSoC
[Figure 2-1, callout 1]
The ZCU106 board is populated with the Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC,
which combines a powerful processing system (PS) and programmable logic (PL) in the
same device. The PS in a Zynq UltraScale+ MPSoC features the Arm® flagship Cortex®-A53
64-bit quad-core processor and Cortex-R5F dual-core real-time processor.
Production ZCU106 evaluation boards will ship with -2 speed grade devices. Support of
multiple speed grades requires voltage adjustments.
The VCCINT supplies are user adjustable via the PMBus with the voltage ranges listed in
Tab le 3- 1 to support multiple Zynq UltraScale+ MPSoC speed grades.
(I XILINXa Send Feed back
ZCU106 Board User Guide 24
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-1: Recommended Operating Conditions
Symbol Description Min Typ Max Units
Processing System
VCC_PSINTFP
PS full-power domain supply voltage. 0.808 0.850 0.892 V
For -1LI and -2LE (VCCINT = 0.72V) devices:
PS full-power domain supply voltage. 0.808 0.850 0.892 V
For -3E devices:
PS full-power domain supply voltage. 0.873 0.900 0.927 V
VCC_PSINTLP
PS low-power domain supply voltage. 0.808 0.850 0.892 V
For -1LI and -2LE (VCCINT = 0.72V) devices:
PS low-power domain supply voltage. 0.808 0.850 0.892 V
For -3E devices:
PS low-power domain supply voltage. 0.873 0.900 0.927 V
Programmable Logic
VCCINT
PL internal supply voltage. 0.825 0.850 0.876 V
For -1LI and -2LE (VCCINT = 0.72V) devices:
PL internal supply voltage. 0.698 0.720 0.742 V
For -3E devices: PL internal supply voltage. 0.873 0.900 0.927 V
(I XILINXG NAND x8 ONF‘ 3 1 2 x SD3 u/ eMMCA 51 QuadrSPl x a X cenml Swltch LPDVDMA Send Feed back
ZCU106 Board User Guide 25
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The top-level block diagram is shown in Figure 3-1.
X-Ref Target - Figure 3-1
Figure 3-1: Top-Level Block Diagram
RPU
256 KB
OCM
LPD-DMA
CSU
PMU
Processing System
Cortex-R5
32 KB I/D
128 KB TCM
Cortex-R5
32 KB I/D
128 KB TCM
4 x 1GE
APU
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
GIC
SCU
ACP 1 MB L2
GPU
Mali-400 MP2
64 KB L2
2 x USB 3.0
NAND x8
ONFI 3.1
2 x SD3.0/
eMMC4.51
Quad-SPI
x 8
2 x SPI
2 x CAN
2 x I2C
2 x UART
GPIOs
SYSMON
MIO
Central
Switch
FPD-DMA
PCIe
Gen4
DisplayPort
v1.2 x1, x2
2 x SATA
v3.1
PCIe Gen2
x1, x2, or x4
SHA3
AES-GCM
RSA
Processor
System BPU
DDRC (DDR4/3/3L, LPDDR3/4)
Programmable
Logic
128 KB RAM
PL_LPD HP
GIC
RGMII
ULPI
PS-GTR
SMMU/CCI
GFC
USB 3.0
SGMII
Low Power Switch
To ACP
Low Power Full Power
Battery
Power
32-bit/64-bit
64-bit
MS
128-bit
MS
LPD_PL HPCHPM
GTY
Quad
GTH
Quad
Interlaken 100G
Ethernet
ACE
DisplayPort
Video and
Audio Interface
Low-latency
Peripheral Port
Low-latency
Peripheral Port
X16387-050517
(I XILINXa Send Feed back
ZCU106 Board User Guide 26
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The Zynq UltraScale+ MPSoC PS block has three major processing units:
• Cortex-A53 application processing unit (APU)-Arm v8 architecture-based 64-bit
quad-core multiprocessing CPU.
• Cortex-R5F real-time processing unit (RPU)-Arm v7 architecture-based 32-bit dual
real-time processing unit with dedicated tightly coupled memory (TCM).
• Mali-400 graphics processing unit (GPU)-graphics processing unit with pixel and
geometry processor and 64 KB L2 cache.
The Zynq UltraScale+ MPSoC PS has four high-speed serial I/O (HSSIO) interfaces
supporting these protocols:
• Integrated block for PCI Express® interface-PCIe™ base specification version 2.1
compliant.
• SATA 3.1 specification compliant interface.
• DisplayPort interface-implements a DisplayPort source-only interface with video
resolution up to 4K x 2K-30 (300 MHz pixel rate).
• USB 3.0 interface-compliant to USB 3.0 specification implementing a 5 Gb/s line rate.
• Serial GMII interface-supports a 1 Gb/s SGMII interface.
The PS and PL can be coupled with multiple interfaces and other signals to effectively
integrate user-created hardware accelerators and other functions in the PL logic that are
accessible to the processors. They can also access memory resources in the PS. The PS I/O
peripherals, including the static/flash memory interfaces share a multiplexed I/O (MIO) of
up to 78 MIO pins. Zynq UltraScale+ MPSoCs can also use the I/O in the PL domain for
many of the PS I/O peripherals. This is done through an extended multiplexed I/O interface
(EMIO) and boots at power-up or reset.
For additional information on Zynq UltraScale+ MPSoC devices, see the Zynq UltraScale+
MPSoC Data Sheet: Overview (DS891) [Ref 1]. See the Zynq UltraScale+ MPSoC Technical
Reference Manual (UG1085) [Ref 3] for more information about Zynq UltraScale+ MPSoC
configuration options.
(I X|L|NXm mu Jva vcc Pann- Send Feed back
ZCU106 Board User Guide 27
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Encryption Key Battery Backup Circuit
The XCZU7EV MPSoC U1 implements bit stream encryption key technology. The ZCU106
board provides the encryption key backup battery circuit shown in Figure 3-2.
The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the
board with the positive output connected to the XCZU7EV MPSoC U1 VCC_PSBATT pin Y23.
The battery supply current IBATT specification is 150 nA maximum when board power is off.
B1 is charged from the UTIL_1V8 1.8V rail through a series diode with a typical forward
voltage drop of 0.38V and 4.7 ΩK current limit resistor. The nominal charging voltage is
1.42V.
On MPSoC devices, the encryption key battery is also used for the battery-backed RAM and
the real-time clock (RTC) supply voltage. See the Zynq UltraScale+ MPSoC Data Sheet: DC
and AC Switching Characteristics (DS925) [Ref 2].
X-Ref Target - Figure 3-2
Figure 3-2: Encryption Key Backup Circuit
(I XILINXa Send Feed back
ZCU106 Board User Guide 28
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
I/O Voltage Rails
The XCZU7EV MPSoC PL I/O bank voltages on the ZCU106 board are listed in Figure 3-2.
PS-Side: DDR4 SODIMM Socket
[Figure 2-1, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ DDRC bank 504 hard memory
controller. The PS-side memory interface supports a 260-pin DDR4 SODIMM socket J1. The
ZCU106 is shipped with a DDR4 SODIMM installed:
• Manufacturer: Micron
• Part Number: Previous P/N MTA8ATF51264HZ- 2G6B1 (now EOL); New P/N
MTA4ATF51264HZ-2G6E1 (in production)
•Description:
°4 GB DDR4 SODIMM, 260-pin
°Single rank, x16 b components
°512 Mb x 64-bit
°Up to DDR-2666
Table 3-2: I/O Voltage Rails
XCZU7EV Power Net Name Voltage Connected To
PL Bank 28 VADJ_FMC(1) 1.8V FMC_HPC1 LA BUS, PMOD0
PL Bank 64 VCC1V2 1.2V DDR4 DQ[0:31]
PL Bank 65 VCC1V2 1.2V DDR4 DQ[32:63]
PL Bank 66 VCC1V2 1.2V DDR4 ADDR/CTRL, GPIO LED, GPIO SW, PMOD1
PL Bank 67 VADJ_FMC(1) 1.8V FMC_HPC0 LA BUS, GPIO DIP SW
PL Bank 68 VADJ_FMC(1) 1.8V FMC_HPC0 LA BUS, SFP REC CLOCK
PL Bank 87 VCC3V3 3.3V HDMI, MSP430 GPIO
PL Bank 88 VCC3V3 3.3V TRACE DEBUG CONNECTOR
PS Bank 500 VCCOPS 1.8V CAN, UART0/1, I2C0/1, QSPI LWR/UPR
PS Bank 501 VCCOPS 1.8V SDIO, PMU_GPO[0:5], DP
PS Bank 502 VCCOPS 1.8V ENET, USB_DATA[0:7], USB_CTRL
PS Bank 503 VCCOPS3 1.8V PS CONFIG I/F
PS Bank 504 VCCO_PSDDR_504 1.2V DDR4 SODIMM I/F
Notes:
1. The ZCU106 board is shipped with VADJ_FMC set to 1.8V by the MSP430 system controller.
(I XILINXa Send Feed back
ZCU106 Board User Guide 29
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 XCZU7EV FFVC MPSoC PS DDR interface performance is documented in the
Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].
The ZCU106 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM socket J1
connections are listed in Tab le 3- 3.
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504
XCZU7EV (U1) Pin Net Name DDR4 SODIMM Memory J1
Pin Number Pin Name
AN34 DDR4_SODIMM_A0 144 A0
AM34 DDR4_SODIMM_A1 133 A1
AM33 DDR4_SODIMM_A2 132 A2
AL34 DDR4_SODIMM_A3 131 A3
AL33 DDR4_SODIMM_A4 128 A4
AK33 DDR4_SODIMM_A5 126 A5
AK30 DDR4_SODIMM_A6 127 A6
AJ30 DDR4_SODIMM_A7 122 A7
AJ31 DDR4_SODIMM_A8 125 A8
AH31 DDR4_SODIMM_A9 121 A9
AG31 DDR4_SODIMM_A10 146 A10/AP
AF31 DDR4_SODIMM_A11 120 A11
AG30 DDR4_SODIMM_A12 119 A12
AF30 DDR4_SODIMM_A13 158 A13
AE27 DDR4_SODIMM_BA0 150 BA0
AE28 DDR4_SODIMM_BA1 145 BA1
AD27 DDR4_SODIMM_BG0 115 BG0
AF27 DDR4_SODIMM_BG1 113 BG1
AP27 DDR4_SODIMM_DQ0 8 DQ0
AP25 DDR4_SODIMM_DQ1 7 DQ1
AP26 DDR4_SODIMM_DQ2 20 DQ2
AM26 DDR4_SODIMM_DQ3 21 DQ3
AP24 DDR4_SODIMM_DQ4 4 DQ4
AL25 DDR4_SODIMM_DQ5 3 DQ5
AM25 DDR4_SODIMM_DQ6 16 DQ6
AM24 DDR4_SODIMM_DQ7 17 DQ7
AM28 DDR4_SODIMM_DQ8 28 DQ8
(I XILINXa Send Feed back
ZCU106 Board User Guide 30
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
AN28 DDR4_SODIMM_DQ9 29 DQ9
AP29 DDR4_SODIMM_DQ10 41 DQ10
AP28 DDR4_SODIMM_DQ11 42 DQ11
AM31 DDR4_SODIMM_DQ12 24 DQ12
AP31 DDR4_SODIMM_DQ13 25 DQ13
AN31 DDR4_SODIMM_DQ14 38 DQ14
AM30 DDR4_SODIMM_DQ15 37 DQ15
AF25 DDR4_SODIMM_DQ16 50 DQ16
AG25 DDR4_SODIMM_DQ17 49 DQ17
AG26 DDR4_SODIMM_DQ18 62 DQ18
A J25 DDR4_SODIMM_DQ19 63 DQ19
AG24 DDR4_SODIMM_DQ20 46 DQ20
AK25 DDR4_SODIMM_DQ21 45 DQ21
A J24 DDR4_SODIMM_DQ22 58 DQ22
AK24 DDR4_SODIMM_DQ23 59 DQ23
AH28 DDR4_SODIMM_DQ24 70 DQ24
AH27 DDR4_SODIMM_DQ25 71 DQ25
A J27 DDR4_SODIMM_DQ26 83 DQ26
AK27 DDR4_SODIMM_DQ27 84 DQ27
AL26 DDR4_SODIMM_DQ28 66 DQ28
AL27 DDR4_SODIMM_DQ29 67 DQ29
AH29 DDR4_SODIMM_DQ30 79 DQ30
AL28 DDR4_SODIMM_DQ31 80 DQ31
AB29 DDR4_SODIMM_DQ32 174 DQ32
AB30 DDR4_SODIMM_DQ33 173 DQ33
AC29 DDR4_SODIMM_DQ34 187 DQ34
AD32 DDR4_SODIMM_DQ35 186 DQ35
AC31 DDR4_SODIMM_DQ36 170 DQ36
AE30 DDR4_SODIMM_DQ37 169 DQ37
AC28 DDR4_SODIMM_DQ38 183 DQ38
AE29 DDR4_SODIMM_DQ39 182 DQ39
AC27 DDR4_SODIMM_DQ40 195 DQ40
AA27 DDR4_SODIMM_DQ41 194 DQ41
AA28 DDR4_SODIMM_DQ42 207 DQ42
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)
XCZU7EV (U1) Pin Net Name DDR4 SODIMM Memory J1
Pin Number Pin Name
(I XILINXa Send Feed back
ZCU106 Board User Guide 31
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
AB28 DDR4_SODIMM_DQ43 208 DQ43
W27 DDR4_SODIMM_DQ44 191 DQ44
W29 DDR4_SODIMM_DQ45 190 DQ45
W28 DDR4_SODIMM_DQ46 203 DQ46
V27 DDR4_SODIMM_DQ47 204 DQ47
AA32 DDR4_SODIMM_DQ48 216 DQ48
AA33 DDR4_SODIMM_DQ49 215 DQ49
AA34 DDR4_SODIMM_DQ50 228 DQ50
AE34 DDR4_SODIMM_DQ51 229 DQ51
AD34 DDR4_SODIMM_DQ52 211 DQ52
AB31 DDR4_SODIMM_DQ53 212 DQ53
AC34 DDR4_SODIMM_DQ54 224 DQ54
AC33 DDR4_SODIMM_DQ55 225 DQ55
AA30 DDR4_SODIMM_DQ56 237 DQ56
Y30 DDR4_SODIMM_DQ57 236 DQ57
AA31 DDR4_SODIMM_DQ58 249 DQ58
W30 DDR4_SODIMM_DQ59 250 DQ59
Y33 DDR4_SODIMM_DQ60 232 DQ60
W33 DDR4_SODIMM_DQ61 233 DQ61
W34 DDR4_SODIMM_DQ62 245 DQ62
Y34 DDR4_SODIMM_DQ63 246 DQ63
AF32 DDR4_SODIMM_CB0 92 CB0/NC
AE32 DDR4_SODIMM_CB1 91 CB1/NC
AH33 DDR4_SODIMM_CB2 101 CB2/NC
AE33 DDR4_SODIMM_CB3 105 CB3/NC
AF33 DDR4_SODIMM_CB4 88 CB4/NC
AH34 DDR4_SODIMM_CB5 87 CB5/NC
AJ34 DDR4_SODIMM_CB6 100 CB6/NC
AK34 DDR4_SODIMM_CB7 104 CB7/NC
AN24 DDR 4_SODIM M _DM0_B 12 DM0 _ N/DBI0 _ N
AM29 DDR 4_SODIM M _DM1_B 33 DM1 _ N/DBI1 _ N
AH24 DDR4_SO DIMM_DM2_B 54 DM2_N/D BI2_N
A J29 DDR4_ SODIMM_D M3_B 75 DM3_ N/DBI3_ N
AD2 9 DDR4_SO DIMM_DM4_B 178 DM4 _ N/DBI4 _ N
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)
XCZU7EV (U1) Pin Net Name DDR4 SODIMM Memory J1
Pin Number Pin Name
(I XILINXa Send Feed back
ZCU106 Board User Guide 32
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Y29 DDR4_ SODIMM_D M5_B 199 DM5_N/DBI 5_N
AC32 DDR4 _ SODIMM_ DM6_B 220 DM6_N/DB I6_N
Y32 DDR4_ SODIMM_D M7_B 241 DM7_N/DBI 7_N
AF 34 DDR 4_SODIM M _DM8_B 96 DM8 _ N/DBI8 _N/NC
AN26 DDR4_SODIMM_DQS0_T 13 DQS0_T
AN27 DDR4_SODIMM_DQS0_C 11 DQS0_C
AN29 DDR4_SODIMM_DQS1_T 34 DQS1_T
AP30 DDR4_SODIMM_DQS1_C 32 DQS1_C
AH26 DDR4_SODIMM_DQS2_T 55 DQS2_T
AJ26 DDR4_SODIMM_DQS2_C 53 DQS2_C
AK28 DDR4_SODIMM_DQS3_T 76 DQS3_T
AK29 DDR4_SODIMM_DQS3_C 74 DQS3_C
AD30 DDR4_SODIMM_DQS4_T 179 DQS4_T
AD31 DDR4_SODIMM_DQS4_C 177 DQS4_C
Y27 DDR4_SODIMM_DQS5_T 200 DQS5_T
Y28 DDR4_SODIMM_DQS5_C 198 DQS5_C
AB33 DDR4_SODIMM_DQS6_T 221 DQS6_T
AB34 DDR4_SODIMM_DQS6_C 219 DQS6_C
W31 DDR4_SODIMM_DQS7_T 242 DQS7_T
W32 DDR4_SODIMM_DQS7_C 240 DQS7_C
AG33 DDR4_SODIMM_DQS8_T 97 DQS8_T
AG34 DDR4_SODIMM_DQS8_C 95 DQS8_C
AL31 DDR4_SODIMM_CK0_C 139 CK0_C
AN32 DDR4_SODIMM_CK0_T 137 CK0_T
AL30 DDR4_SODIMM_CK1_C 140 CK1_C/NF
AL32 DDR4_SODIMM_CK1_T 138 CK1_T/NF
AN33 DDR4_SODIMM_CKE0 109 CKE0
AH32 DDR4_SODIMM_CKE1 110 CKE1
AP32 DDR4_SODIMM_ODT0 155 ODT0
A J32 DDR4_SODIMM_ODT1 161 ODT1
AF28 DDR4_SODIMM_RAS_B 152 RAS_N/A16
AG28 DDR4_SODIMM_CAS_B 156 CAS_N/A15
AG29 DDR4_SODIMM_WE_B 151 WE_N/A14
AE25 DDR4_SODIMM_ACT_B 114 ACT_N
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)
XCZU7EV (U1) Pin Net Name DDR4 SODIMM Memory J1
Pin Number Pin Name
(I XILINXa Send Feed back
ZCU106 Board User Guide 33
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the “PCB Guidelines for DDR4” section of the UltraScale Architecture PCB Design Guide
(UG583) [Ref 4]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other
memory interface details are also available in the UltraScale Architecture FPGAs Memory
Interface Solutions Guide (PG150) [Ref 5].
PL-Side: DDR4 Component Memory
[Figure 2-1, callout 2]
The 2 GB 64-bit wide DDR4 memory system is comprised of four 256 Mb x 16 SDRAMs, U2,
and 99–101.
• Manufacturer: Micron
• Part Number: MT40A256M16GE-075E
•Description:
°4 Gb (256 Mb x 16)
°1.2V 96-ball TFBGA
°DDR4-2666
The ZCU106 XCZU7EV FFVC MPSoC PL DDR interface performance is documented in the
Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].
This memory system is connected to the XCZU7EV device banks 64, 65, and 66. The DDR4
0.6V VTT termination voltage is sourced from the TI TPS51200DR linear regulator U35. The
connections between the DDR4 component memory and the XCZU7EV device are listed in
Tab le 3- 4.
AB26 DDR4_SODIMM_ALERT_B 116 ALERT_N
AA26 DDR4_SODIMM_PARITY 143 PARITY
AP33 DDR4_SODIMM_CS0_B 149 CS0_N
AK32 DDR4_SODIMM_CS1_B 157 CS1_N
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont’d)
XCZU7EV (U1) Pin Net Name DDR4 SODIMM Memory J1
Pin Number Pin Name
(I XILINXa Send Feed back
ZCU106 Board User Guide 34
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC
XCZU7EV
(U1) Pin Net Name I/O Standard DDR4 Component Memory
Pin # Pin Name Ref. Des.
AF16 DDR4_DQ0 POD12_DCI G2 DQL0 U101
AF18 DDR4_DQ1 POD12_DCI F7 DQL1 U101
AG15 DDR4_DQ2 POD12_DCI H3 DQL2 U101
AF17 DDR4_DQ3 POD12_DCI H7 DQL3 U101
AF15 DDR4_DQ4 POD12_DCI H2 DQL4 U101
AG18 DDR4_DQ5 POD12_DCI H8 DQL5 U101
AG14 DDR4_DQ6 POD12_DCI J3 DQL6 U101
AE17 DDR4_DQ7 POD12_DCI J7 DQL7 U101
AA14 DDR4_DQ8 POD12_DCI A3 DQU0 U101
AC16 DDR4_DQ9 POD12_DCI B8 DQU1 U101
AB15 DDR4_DQ10 POD12_DCI C3 DQU2 U101
AD16 DDR4_DQ11 POD12_DCI C7 DQU3 U101
AB16 DDR4_DQ12 POD12_DCI C2 DQU4 U101
AC17 DDR4_DQ13 POD12_DCI C8 DQU5 U101
AB14 DDR4_DQ14 POD12_DCI D3 DQU6 U101
AD17 DDR4_DQ15 POD12_DCI D7 DQU7 U101
AH14 DDR4_DQS0_T DIFF_POD12_DCI G3 DQSL_T U101
AJ14 DDR4_DQS0_C DIFF_POD12_DCI F3 DQSL_C U101
AA16 DDR4_DQS1_T DIFF_POD12_DCI B7 DQSU_T U101
AA15 DDR4_DQS1_C DIFF_POD12_DCI A7 DQSU_C U101
AH18 DDR4_DM0 POD12_DCI E7 DML_B/DBIL_B U101
AD15 DDR4_DM1 POD12_DCI E2 DMU_B/DBIU_B U101
AJ16 DDR4_DQ16 POD12_DCI G2 DQL0 U99
AJ17 DDR4_DQ17 POD12_DCI F7 DQL1 U99
AL15 DDR4_DQ18 POD12_DCI H3 DQL2 U99
AK17 DDR4_DQ19 POD12_DCI H7 DQL3 U99
AJ15 DDR4_DQ20 POD12_DCI H2 DQL4 U99
AK18 DDR4_DQ21 POD12_DCI H8 DQL5 U99
AL16 DDR4_DQ22 POD12_DCI J3 DQL6 U99
AL18 DDR4_DQ23 POD12_DCI J7 DQL7 U99
AP13 DDR4_DQ24 POD12_DCI A3 DQU0 U99
AP16 DDR4_DQ25 POD12_DCI B8 DQU1 U99
AP15 DDR4_DQ26 POD12_DCI C3 DQU2 U99
(I XILINXa Send Feed back
ZCU106 Board User Guide 35
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
AN16 DDR4_DQ27 POD12_DCI C7 DQU3 U99
AN13 DDR4_DQ28 POD12_DCI C2 DQU4 U99
AM18 DDR4_DQ29 POD12_DCI C8 DQU5 U99
AN17 DDR4_DQ30 POD12_DCI D3 DQU6 U99
AN18 DDR4_DQ31 POD12_DCI D7 DQU7 U99
AK15 DDR4_DQS2_T DIFF_POD12_DCI G3 DQSL_T U99
AK14 DDR4_DQS2_C DIFF_POD12_DCI F3 DQSL_C U99
AM14 DDR4_DQS3_T DIFF_POD12_DCI B7 DQSU_T U99
AN14 DDR4_DQS3_C DIFF_POD12_DCI A7 DQSU_C U99
AM16 DDR4_DM2 POD12_DCI E7 DML_B/DBIL_B U99
AP18 DDR4_DM3 POD12_DCI E2 DMU_B/DBIU_B U99
AB19 DDR4_DQ32 POD12_DCI G2 DQL0 U100
AD19 DDR4_DQ33 POD12_DCI F7 DQL1 U100
AC18 DDR4_DQ34 POD12_DCI H3 DQL2 U100
AC19 DDR4_DQ35 POD12_DCI H7 DQL3 U100
AA20 DDR4_DQ36 POD12_DCI H2 DQL4 U100
AE20 DDR4_DQ37 POD12_DCI H8 DQL5 U100
AA19 DDR4_DQ38 POD12_DCI J3 DQL6 U100
AD20 DDR4_DQ39 POD12_DCI J7 DQL7 U100
AF22 DDR4_DQ40 POD12_DCI A3 DQU0 U100
AH21 DDR4_DQ41 POD12_DCI B8 DQU1 U100
AG19 DDR4_DQ42 POD12_DCI C3 DQU2 U100
AG21 DDR4_DQ43 POD12_DCI C7 DQU3 U100
AE24 DDR4_DQ44 POD12_DCI C2 DQU4 U100
AG20 DDR4_DQ45 POD12_DCI C8 DQU5 U100
AE23 DDR4_DQ46 POD12_DCI D3 DQU6 U100
AF21 DDR4_DQ47 POD12_DCI D7 DQU7 U100
AA18 DDR4_DQS4_T DIFF_POD12_DCI G3 DQSL_T U100
AB18 DDR4_DQS4_C DIFF_POD12_DCI F3 DQSL_C U100
AF23 DDR4_DQS5_T DIFF_POD12_DCI B7 DQSU_T U100
AG23 DDR4_DQS5_C DIFF_POD12_DCI A7 DQSU_C U100
AE18 DDR4_DM4 POD12_DCI E7 DML_B/DBIL_B U100
AH22 DDR4_DM5 POD12_DCI E2 DMU_B/DBIU_B U100
AL22 DDR4_DQ48 POD12_DCI G2 DQL0 U100
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC (Cont’d)
XCZU7EV
(U1) Pin Net Name I/O Standard DDR4 Component Memory
Pin # Pin Name Ref. Des.
(I XILINXa Send Feed back
ZCU106 Board User Guide 36
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
AJ22 DDR4_DQ49 POD12_DCI F7 DQL1 U2
AL23 DDR4_DQ50 POD12_DCI H3 DQL2 U2
AJ21 DDR4_DQ51 POD12_DCI H7 DQL3 U2
AK20 DDR4_DQ52 POD12_DCI H2 DQL4 U2
AJ19 DDR4_DQ53 POD12_DCI H8 DQL5 U2
AK19 DDR4_DQ54 POD12_DCI J3 DQL6 U2
AJ20 DDR4_DQ55 POD12_DCI J7 DQL7 U2
AP22 DDR4_DQ56 POD12_DCI A3 DQU0 U2
AN22 DDR4_DQ57 POD12_DCI B8 DQU1 U2
AP21 DDR4_DQ58 POD12_DCI C3 DQU2 U2
AP23 DDR4_DQ59 POD12_DCI C7 DQU3 U2
AM19 DDR4_DQ60 POD12_DCI C2 DQU4 U2
AM23 DDR4_DQ61 POD12_DCI C8 DQU5 U2
AN19 DDR4_DQ62 POD12_DCI D3 DQU6 U2
AN23 DDR4_DQ63 POD12_DCI D7 DQU7 U2
AK22 DDR4_DQS6_T DIFF_POD12_DCI G3 DQSL_T U2
AK23 DDR4_DQS6_C DIFF_POD12_DCI F3 DQSL_C U2
AM21 DDR4_DQS7_T DIFF_POD12_DCI B7 DQSU_T U2
AN21 DDR4_DQS7_C DIFF_POD12_DCI A7 DQSU_C U2
AL20 DDR4_DM6 POD12_DCI E7 DML_B/DBIL_B U2
AP19 DDR4_DM7 POD12_DCI E2 DMU_B/DBIU_B U2
AK9 DDR4_A0 SSTL12_DCI P3 A0 U2,U99-U101
AG11 DDR4_A1 SSTL12_DCI P7 A1 U2,U99-U101
AJ10 DDR4_A2 SSTL12_DCI R3 A2 U2,U99-U101
AL8 DDR4_A3 SSTL12_DCI N7 A3 U2,U99-U101
AK10 DDR4_A4 SSTL12_DCI N3 A4 U2,U99-U101
AH8 DDR4_A5 SSTL12_DCI P8 A5 U2,U99-U101
AJ9 DDR4_A6 SSTL12_DCI P2 A6 U2,U99-U101
AG8 DDR4_A7 SSTL12_DCI R8 A7 U2,U99-U101
AH9 DDR4_A8 SSTL12_DCI R2 A8 U2,U99-U101
AG10 DDR4_A9 SSTL12_DCI R7 A9 U2,U99-U101
AH13 DDR4_A10 SSTL12_DCI M3 A10/AP U2,U99-U101
AG9 DDR4_A11 SSTL12_DCI T2 A11 U2,U99-U101
AM13 DDR4_A12 SSTL12_DCI M7 A12/BC_B U2,U99-U101
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC (Cont’d)
XCZU7EV
(U1) Pin Net Name I/O Standard DDR4 Component Memory
Pin # Pin Name Ref. Des.
(I XILINXa Send Feed back
ZCU106 Board User Guide 37
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 board DDR4 64-bit component memory interface adheres to the constraints
guidelines documented in the “PCB Guidelines for DDR4” section of UltraScale Architecture
PCB Design User Guide (UG583)[Ref 4]. The ZCU106 DDR4 component interface is a 40Ω
impedance implementations. Other memory interface details are also available in the
UltraScale Architecture FPGAs Memory Interface Solutions Product Guide (PG150) [Ref 5]. For
more details, see the Micron MT40A256M16GE-075E data sheet at the Micron website
[Ref 15].
AF8 DDR4_A13 SSTL12_DCI T8 A13 U2,U99-U101
AK8 DDR4_BA0 SSTL12_DCI N2 BA0 U2,U99-U101
AL12 DDR4_BA1 SSTL12_DCI N8 BA1 U2,U99-U101
AE14 DDR4_BG0 SSTL12_DCI M2 BG0 U2,U99-U101
AC12 DDR4_A14_WE_B SSTL12_DCI L2 WE_B/A14 U2,U99-U101
AF11 DDR4_A16_RAS_B SSTL12_DCI L8 RAS_B/A16 U2,U99-U101
AE12 DDR4_A15_CAS_B SSTL12_DCI M8 CAS_B_A15 U2,U99-U101
AH11 DDR4_CK_T DIFF_SSTL12_DCI K7 CK_T U2,U99-U101
AJ11 DDR4_CK_C DIFF_SSTL12_DCI K8 CK_C U2,U99-U101
AB13 DDR4_CKE SSTL12_DCI K2 CKE U2,U99-U101
AD14 DDR4_ACT_B SSTL12_DCI L3 ACT_B U2,U99-U101
R156 P/D DDR4_TEN SSTL12_DCI N9 TEN U2,U99-U101
R499 P/U DDR4_ALERT_B SSTL12_DCI P9 ALERT_B U2,U99-U101
AC13 DDR4_PAR SSTL12_DCI T3 PAR U2,U99-U101
AF12 DDR4_RESET_B LVCMOS12 P1 RESET_B U2,U99-U101
AF10 DDR4_ODT SSTL12_DCI K3 ODT U2,U99-U101
AD12 DDR4_CS_B SSTL12_DCI L7 CS_B U2,U99-U101
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC (Cont’d)
XCZU7EV
(U1) Pin Net Name I/O Standard DDR4 Component Memory
Pin # Pin Name Ref. Des.
(I XILINXa Send Feed back
ZCU106 Board User Guide 38
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
PSMIO
Tab le 3- 5 provides PS MIO peripheral mapping implemented on the ZCU106 board. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more information
on PS MIO peripheral mapping.
Table 3-5: MIO Peripheral Mapping
MIO[0:25] Bank 500 MIO[26:51] Bank 501 MIO[52:77] Bank 502
0QSPI26PMU IN52USB0
1QSPI27DPAUX53USB0
2QSPI28DPAUX54USB0
3QSPI29DPAUX55USB0
4QSPI30DPAUX56USB0
5 QSPI 31 Not assigned/no connect 57 USB0
6 Not assigned/no connect 32 PMU OUT 58 USB0
7QSPI33PMU OUT59USB0
8QSPI34PMU OUT60USB0
9QSPI35PMU OUT61USB0
10 QSPI 36 PMU OUT 62 USB0
11 QSPI 37 PMU OUT 63 USB0
12 QSPI 38 GPIO 64 GEM3
13 GPIO 39 SD1 65 GEM3
14 I2C0 40 SD1 66 GEM3
15 I2C0 41 SD1 67 GEM3
16 I2C1 42 SD1 68 GEM3
17 I2C1 43 69 GEM3
18 UART0 44 SD1 70 GEM3
19 UART0 45 SD1 71 GEM3
20 UART1 46 SD1 72 GEM3
21 UART1 47 SD1 73 GEM3
22 GPIO 48 SD1 74 GEM3
23 GPIO 49 SD1 75 GEM3
24 CAN1 50 SD1 76 GEM3
25 CAN1 51 SD1 77 GEM3
(I XILINXa Send Feed back
ZCU106 Board User Guide 39
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Quad SPI Flash Memory (MIO 0–12)
[Figure 2-1, callout 3]
The Micron dual MT25QU512ABB8ESF serial NOR flash Quad SPI (QSPI) flash memories can
hold the boot image for the MPSoC system. To achieve higher performance, two QSPI flash
memory devices are connected in parallel and provide an 8-bit data bus for boot and
configuration. This interface is used to support QSPI32 boot mode as defined in the Zynq
UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3].
The dual QSPI flash memory located at U119/U120 provides 1 Gb of non-volatile storage
that can be used for configuration and data storage.
• Part number: MT25QU512ABB8ESF-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 8-bit
• Data rate: various depending on single, dual, or quad mode
The connections between the SPI flash memory and the XCZU7EV MPSoC are listed in
Tab le 3- 6.
The configuration and Quad SPI flash memory section of the Zynq UltraScale+ MPSoC
Technical Reference Manual (UG1085) [Ref 3] provides details on using the memory. For
more QSPI details, see the Micron MT25QU512ABB8ESF-0SIT data sheet at the Micron
website [Ref 15].
Table 3-6: Quad SPI Flash Memory Component Connections to MPSoC U1
XCZU7EV (U1) Pin Net Name Quad-SPI U119 (LWR), U120 (UPR)
Pin # Pin Name
A25 MIO4_QSPI_LWR_DQ0 15 DQ0
C24 MIO1_QSPI_LWR_DQ1 8 DQ1
B24 MIO2_QSPI_LWR_DQ2 9 DQ2_WP_B
E25 MIO3_QSPI_LWR_DQ3 1 DQ3_RST_HOLD_B
A24 MIO0_QSPI_LWR_CLK 16 C
D25 MIO5_QSPI_LWR_CS_B 7 S_B
D26 MIO8_QSPI_UPR_DQ0 15 DQ0
C26 MIO9_QSPI_UPR_DQ1 8 DQ1
F26 MIO10_QSPI_UPR_DQ2 9 DQ2_WP_B
B26 MIO11_QSPI_UPR_DQ3 1 DQ3_RST_HOLD_B
C27 MIO12_QSPI_UPR_CLK 16 C
B25 MIO7_QSPI_UPR_CS_B 7 S_B
(I XILINXa Send Feed back
ZCU106 Board User Guide 40
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
USB0 (MIO 52-63)
The USB interface on the PS-side serves multiple roles as a host or device controller. The
USB 3.0 interface is supported by the MPSoC GTR interface while the USB 2.0 capabilities of
the SMSC USB3320C controller are shared on a common USB 3.0 USB type A connector
(J96).
USB 3.0 Transceiver and USB 2.0 ULPI PHY
[Figure 2-1, callout 5]
The ZCU106 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI
transceiver at U116 to support a USB connection to the host computer (see Figure 3-3). The
USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI)
interface standard. The ULPI standard defines the interface between the USB controller IP
and the PHY device, which drives the physical USB bus. Use of the ULPI standard reduces the
interface pin count between the USB controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. See the Standard Microsystems Corporation
(SMSC) USB3320 data sheet for clocking mode details [Ref 16]. The interface to the
USB3320 PHY is implemented through the IP in the XCZU7EV MPSoC PS.
X-Ref Target - Figure 3-3
Figure 3-3: USB Interface
SM3320
USB2.0
USB
MIO
ULPI
USB3
Connector
USB
PS-GTR
PS-GTR TX, RX
X19172-100218
(I XILINXa Send Feed back
ZCU106 Board User Guide 41
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Tab le 3- 7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default shunt positions for USB 2.0 high speed on-the-go (OTG) mode.
The connections between the USB 2.0 PHY at U116 and the XCZU7EV MPSoC are listed in
Tab le 3- 8.
Note: The shield for the USB 3.0 A connector (J96) can be tied to GND by a jumper on header J112
pins 2-3 (default). The USB shield can optionally be connected through a capacitor to GND by
installing a capacitor (body size 0402) at location C887 and jumping pins 1-2 on header J112.
Table 3-7: USB Jumper Settings
Header Function Shunt Position Notes
J110 CVBUS select
ON = Device mode (1 µF)
OFF = Host mode (120 µF) and source of bus
power
VBUS load capacitance
J96 USB 3.0 A Position 1-2 = Shield floating (DNP C887 pads)
Position 2-3 = Shield connected to GND
Table 3-8: USB 2.0 ULPI Transceiver Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin Net Name USB3320 U116
Pin # Pin Name
U117.4 ULPI0_RST_B(1) 27 RESET_B
H31 MIO58_USB_STP(2) 29 STP
G30 MIO53_USB_DIR 31 DIR
G29 MIO52_USB_CLK 1 CLKOUT
G33 MIO55_USB_NXT 2 NXT
G34 MIO56_USB_DATA0(2) 3 DATA0
H29 MIO57_USB_DATA1(2) 4 DATA1
G31 MIO54_USB_DATA2(2) 5 DATA2
H32 MIO59_USB_DATA3(2) 6 DATA3
H33 MIO60_USB_DATA4(2) 7 DATA4
H34 MIO61_USB_DATA5(2) 9 DATA5
J29 MIO62_USB_DATA6(2) 10 DATA6
J30 MIO63_USB_DATA7(2) 13 DATA7
Notes:
1. PS_POR_B (U1.M24) or PS_MODE1 (DIP SW6.2) or PB SW2 drive U116 RST_B via OR gate U117.
2. These nets are 30Ω series resistor coupled.
(I XILINX¢ Send Feed back
ZCU106 Board User Guide 42
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The USB3320 ULPI U116 transceiver circuit (see Figure 3-4) has a Micrel MIC2544 high-side
programmable current limit switch (U121). This switch has an open-drain output fault flag
on pin 2, which turns on LED DS51 if over current or thermal shutdown conditions are
detected. DS51 is located in the U116 circuit area near pushbutton SW2 (Figure 2-1, callout
5).
SD1 (MIO 39-51)
A PS-side interface to an SD card connector is provided for booting and file system storage.
This interface is used for the SD boot mode and supports SD3.0 access post boot.
SD Card Interface
[Figure 2-1, callout 6]
The ZCU106 board includes a secure digital input/output (SDIO) interface to provide access
to general purpose non-volatile SDIO memory cards and peripherals. See the SanDisk
Corporation [Ref 17] or SD Association [Ref 18] websites for more information on the SD
I/O card specification. The ZCU106 SD card interface supports the SD1_LS configuration
boot mode documented in the Zynq UltraScale+ MPSoC Technical Reference Manual
(UG1085) [Ref 3].
The SDIO signals are connected to XCZU7EV MPSoC PS bank 501, which has its VCCMIO set to
1.8V. Each of the six MIO[46-51]_SDIO_* nets has a series 30Ω resistor at the source. An NXP
IP4856CX25 SD 3.0-compliant voltage level-translator U133 is present between the
XCZU7EV MPSoC and the SD card connector (J100). The NXP IP4856CX25 U133 device
provides SD3.0 capability with SDR104 performance.
X-Ref Target - Figure 3-4
Figure 3-4: ULPI U116 Transceiver Circuit
X19004-050117
(I XILINXa :5 as a My, '6 2 E 25 t E, “‘15—"! no: cafi fl 5‘ « mm m g :3 my.“ WI ,_ns77, :35: f‘ Li W m. . :2 m a, szmsiszzfi ; , C1045 '” ’ m’n v =11 m 2:33.531 293.9. .3 ;n W mfg?! m g 32 Egg; fig :3; mu 3: zx $3 _3 :31”... ,:2 $337; 3% g; 2! mm) nun: .M W mg; g: g 3:; $3 $.51 '—mm| - a; 2;“, m 2 m“ m m: XmasxmsL mm a; , ,6” ; “Maw 3. m Send Feed back
ZCU106 Board User Guide 43
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-5 shows the connections of the SD card interface on the ZCU106 board.
The NXP SD3.0 level shifter is mounted on an Aries adapter board that has the pin mapping
listed in Tab le 3-9.
X-Ref Target - Figure 3-5
Figure 3-5: SD Card Interface
X19005-050117
Table 3-9: U133 IP4856CX25 Adapter Pin-Out
Aries Adapter Pin
Number
IP4856CX25 U133
Pin Number IP4856CX25 U133 Pin Name
1 C1 CLK_IN
2 C3 GND
3 D3 CD
4 D2 CMD_H
5 E2 CLK_FB
6 E4 WP
7 B4 VLDO
8 C4 V
SD_REF
9 A3 DIR_0
10 A4 VSUPPLY
11 B3 VCCA
12 A2 DIR_CMD
13 D1 DATA0_H
14 B2 SEL
(I XILINXa Send Feed back
ZCU106 Board User Guide 44
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Tab le 3- 10 lists the SD card interface connections to the XCZU7EV MPSoC.
15 B1 DATA3_H
16 E1 DATA1_H
17 E3 DIR_1_3
18 A1 DATA2_H
19 E5 DATA1_SD
20 D5 DATA0_SD
21 C5 CLK_SD
22 D4 CMD_SD
23 B5 DATA3_SD
24 A5 DATA2_SD
25 C2 ENABLE
Table 3-10: SD Interface Connections to the XCZU7EV MPSoC
XCZU7EV
(U1) Pin Net Name
U133 IP4856CX25
Adapter
Pin # Pin Name
D30 MIO39_SDIO_SEL 14 SEL
D31 MIO40_SDIO_DIR_CMD 12 DIR_CMD
D32 MIO41_SDIO_DIR_DAT0 9 DIR_0
D34 MIO42_SDIO_DIR_DAT1_3 17 DIR_1_3
E34 MIO46_SDIO_DAT0 13 DATA0_H
F30 MIO47_SDIO_DAT1 16 DATA1_H
F31 MIO48_SDIO_DAT2 18 DATA2_H
F32 MIO49_SDIO_DAT3 15 DATA3_H
F33 MIO50_SDIO_CMD 4 CMD_H
F34 MIO51_SDIO_CLK 1 CLK_IN
E32 MIO44_SDIO_PROTECT 6 WP
E33 MIO45_SDIO_DETECT 3 CD
Table 3-9: U133 IP4856CX25 Adapter Pin-Out (Cont’d)
Aries Adapter Pin
Number
IP4856CX25 U133
Pin Number IP4856CX25 U133 Pin Name
(I XILINXa 4 —> 4 —> E |_1°—’° < —=""> <—> > > > > Send Feed back
ZCU106 Board User Guide 45
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Programmable Logic JTAG Programming Options
[Figure 2-1, callouts 7 and 39]
ZCU106 JTAG chain:
• J2 USB micro AB connector connected to U152 FTDI USB JTAG bridge
• J8 2x7 2 mm shrouded, keyed JTAG pod flat cable connector
• J6 2x10 Arm JTAG male pin header
The ZCU106 board JTAG chain is shown in Figure 3-6.
For more details on the FTDI FT232HL USB UART, see [Ref 26].
X-Ref Target - Figure 3-6
Figure 3-6: JTAG Chain Block Diagram
JTAG
Header
TDO
TDI
JTAG
Module
TDO
TDI
JTAG
Header
TDO
TDI
JTAG
IF
TDI
TDO
J6
U152
J8
U1
J6: 2x10 ARM JTAG male pin header
U152: FTDI USB JTAG bridge
J8: 2x7 2 mm shrouded, keyed JTAG
pod flat cable connector
U1: XCZU7EV MPSoC
JTAG
TDO
BUF
FMC HPC0
Connector
TDI TDO
FMC HPC1
Connector
TDI TDO
SPST Bus Switch SPST Bus Switch
N.C. N.C.
J5 J4
U48
U27 U24
JTAG
TDO
BUF
U11
X19173-022218
(I XILINX¢ “mm“...m 19‘ _n 0 mm H x = x - xcmmmuss 5333:5955 fififi sum mm Trace/Debug mas: Raw 55:: fi '5“ i % ... "a Send Feed back
ZCU106 Board User Guide 46
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
FMC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is attached to J5 or J4, it is automatically added to the
JTAG chain through electronically controlled single-pole single-throw (SPST) switches U27
and U24. The SPST switches are normally closed and transition to an open state when an
FMC is attached. Switch U27 adds an attached FMC to the JTAG chain as determined by the
FMC_HPC0_PRSNT_M2C_B signal. Switch U24 adds an attached FMC to the JTAG chain as
determined by the FMC_HPC1_PRSNT_M2C_B signal. The attached FMC card must
implement a TDI-to-TDO connection using a device or bypass jumper to ensure that the
JTAG chain connects to the U1 XCZU7EV MPSoC.
EMIO Arm Trace Port
[Figure 2-1, callout 34]
The ZCU106 evaluation board provides a trace/debug 38-pin Mictor connector, P6.
Figure 3-7 shows connector P6 with its MPSoC bank 87/88 connections.
X-Ref Target - Figure 3-7
Figure 3-7: EMIO Arm Trace Port Interface
X19006-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 47
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The P6 connector to MPSoC connections are listed in Table 3 -11.
For more information about managing the Zynq MPSoC extended MIO (EMIO) trace port
connections, see the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3].
Table 3-11: Trace/Debug Conn. P6 Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin Net Name I/O Standard Trace/Debug P6 Pin
H6 TRACEDATA0 LVCMOS33 38
G6 TRACEDATA1 LVCMOS33 28
H7 TRACEDATA2 LVCMOS33 26
E1 TRACEDATA3 LVCMOS33 24
D1 TRACEDATA4 LVCMOS33 22
C1 TRACEDATA5 LVCMOS33 20
B1 TRACEDATA6 LVCMOS33 18
A3 TRACEDATA7 LVCMOS33 16
D2 TRACEDATA8 LVCMOS33 37
C2 TRACEDATA9 LVCMOS33 35
C3 TRACEDATA1 LVCMOS33 33
B3 TRACEDATA11 LVCMOS33 31
C4 TRACEDATA12 LVCMOS33 29
B4 TRACEDATA13 LVCMOS33 27
E4 TRACEDATA14 LVCMOS33 25
D4 TRACEDATA15 LVCMOS33 23
E2 TRACECLKA LVCMOS33 6
D6 TRACERTCK LVCMOS33 13
E5 TRACEDBGRQ LVCMOS33 7
E3 TRACEDBGACK LVCMOS33 8
K8 TRACECTL LVCMOS33 36
A2 TRACEEXTTRIG LVCMOS33 10
A5 TRACETCK LVCMOS33 15
F4 TRACETDI LVCMOS33 19
D5 TRACETDO LVCMOS33 11
B5 TRACETMS LVCMOS33 17
F5 TRACETRST_B LVCMOS33 21
F6 TRACESRST_B LVCMOS33 9
(I XILINXa Send Feed back
ZCU106 Board User Guide 48
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Clock Generation
The ZCU106 board provides fixed and variable clock sources for the XCZU7EV MPSoC.
Tab le 3- 12 lists the source devices for each clock.
Tab le 3- 13 lists the source devices for each clock.
Table 3-12: Clock Sources
Clock (Net) Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz
U69 SI5341B clock generator
CLK_74_25 74.25 MHz
CLK_125 125 MHz
GTR_REF_CLK_SATA 125 MHz
GTR_REF_CLK_USB3 26 MHz
GTR_REF_CLK_DP 27 MHz
Programmable Frequency Clocks
USER_SI570 300 MHz (default) U42 SI570 I2C PROG. OSC.
USER_MGT_SI570 156.25 MHz (default) U56 SI570 I2C PROG. OSC.
USER_MGT_SMA User-Provided source J79 (P)/J80 (N) SMA CONN.
HDMI_SI5324_OUT Variable U108 SI5319C clock recovery
SFP_SI5328_OUT Variable U20 SI5328B clock recovery
Table 3-13: Clock Connections, Source to XCZU7EV MPSoC
Clock Source Ref.
Des. and Pin Net Name I/O Standard XCZU7EV (U1) Pin
U69.59 PS_REF_CLK (1) R24
U69.45 CLK_125_P LVDS_25 H9
U69.44 CLK_125_N LVDS_25 G9
U69.51 CLK_74_25_P LVDS_25 D15
U69.50 CLK_74_25_N LVDS_25 D14
U69.35 GTR_REF_CLK_SATA_P (2) P27
U69.34 GTR_REF_CLK_SATA_N (2) P28
U69.31 GTR_REF_CLK_USB3_P (2) M27
U69.30 GTR_REF_CLK_USB3_N (2) M28
U69.24 GTR_REF_CLK_DP_P (2) M31
U69.23 GTR_REF_CLK_DP_N (2) M32
U42.4 USER_SI570_P DIFF_SSTL12 AH12
U42.5 USER_SI570_N DIFF_SSTL12 AJ12
(I XILINXa Send Feed back
ZCU106 Board User Guide 49
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
U56.4 USER_MGT_SI570_P (2) (1-to-2 CLOCK BUFFER) U51.6
U56.5 USER_MGT_SI570_N (2) (1-to-2 CLOCK BUFFER) U51.7
U51.11 USER_MGT_SI570_CLOCK1_P (2) U10
U51.12 USER_MGT_SI570_CLOCK1_N (2) U9
U51.13 USER_MGT_SI570_CLOCK2_P (2) R10
U51.14 USER_MGT_SI570_CLOCK2_N (2) R9
J79.1 USER_SMA_MGT_CLOCK_P (2) AA10
J80.1 USER_SMA_MGT_CLOCK_N (2) AA9
U108.28 HDMI_SI5324_OUT_P (2) AD8
U108.29 HDMI_SI5324_OUT_N (2) AD7
U20.28 SFP_SI5328_OUT_P (2) W10
U20.29 SFP_SI5328_OUT_N (2) W9
Notes:
1. U1 XCU7EV Bank 503 supports LVCMOS level inputs.
2. U1 MGT (I/O standards do not apply).
Table 3-13: Clock Connections, Source to XCZU7EV MPSoC (Cont’d)
Clock Source Ref.
Des. and Pin Net Name I/O Standard XCZU7EV (U1) Pin
(I X|L|NXm ind c127 , c2; c125 zév z‘Ezsvzi 2§v V69 :2 vnm mm m m mu , mm . ",9.” m. 1...; u z: , m“; m m my cum . ‘ nu 1 an; y 7 an 1W. ,5 m . m ‘ n ., w. , x, WE'LM ‘7 7 x) ”m 17 ‘ m 12 an 125 a .4 m . mm W mm. w “- m w“ m :2 2:13;: -—fi—n¢ . m- n7: 1 .m <' w="" n="" 9m);="" m:-="" ,2="" vim;="" send="" feed="" back="">
ZCU106 Board User Guide 50
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
SI5341B 10 Independent Output Any-Frequency Clock Generator
[Figure 2-1, callout 8]
• Clock generator: Silicon Labs SI5341B-B05071-GM
• Jitter: <100 fs RMS typical
• Differential and single-ended outputs
The SI5341B (U69) is a one-time programmable clock source. For more details, see the
SI5341B data sheet [Ref 19]. The clock circuit is shown in Figure 3-8.
X-Ref Target - Figure 3-8
Figure 3-8: SI5341B Clock Generator
X19007-050117
{I XILINX, mu 3v; 1 R229 ".101 1/1“! 2 n .0521 51510 5m um ”510 m1 Inn. IV: 1 C244 many 2 25v x52 sopr- 3 0 014112 LVDS man-us Inn 81570 I nun sxs'ln Send Feedback
ZCU106 Board User Guide 51
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Programmable User Clock
[Figure 2-1, callout 9]
The ZCU106 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential
oscillator (U42) connected to the GC inputs of PL bank 66. This USER_SI570_P and
USER_SI570_N clock signals are connected to XCZU7EV MPSoC U1 pins AH12 and AJ12,
respectively. On power up, the user clock defaults to an output frequency of 300.000 MHz.
User applications can change the output frequency within the range of 10 MHz to 810 MHz
through an I2C interface. Power cycling the ZCU106 board reverts this user clock to the
default frequency of 300.000 MHz.
This oscillator can be reprogrammed from MSP430 system controller U41 (see TI MSP430
System Controller, page 116 for more information).
• Programmable oscillator: Silicon Labs Si570BAB001614DG (10 MHz-810 MHz, 300 MHz
default)
•LVDS differential output
• Total stability: 61.5 ppm
X-Ref Target - Figure 3-9
Figure 3-9: Programmable User Clock
X16526-052417
(I XILINX¢ am an mu m Inc-- m can in mm 10 um n5 . . N ,EW Imam'h ‘ , w. .c u" uni-14.” .c P D, 7 ‘ um «I um m1 Inn m 515711 5:. .Ir_‘.m . 917.”:1‘m '1 :15" mm “2 .n um .x 515'": Ewen u m “27.1 vs:- m 5570 m7 v, 45—3; mgfl .. urns u xxx- Send Feed back
ZCU106 Board User Guide 52
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Programmable User MGT Clock
[Figure 2-1, callout 10]
The ZCU106 board has a programmable low-jitter 3.3V LVDS SI570 differential oscillator
(U56) connected to a 1-to-2 SI53340 clock driver (U51). On power up, the user clock
defaults to an output frequency of 156.250 MHz. User applications can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling
the ZCU106 board reverts this user clock to the default frequency of 156.250 MHz.
This oscillator can be reprogrammed from MSP430 system controller U41 (see TI MSP430
System Controller, page 116 for more information).
• Programmable oscillator: Silicon Labs Si570BAB000544DG (10 MHz-810 MHz,
156.250 MHz default)
•LVDS differential output
• Total stability: 61.5 ppm
The user clock MGT circuit is shown in Figure 3-10. The Silicon Labs Si570 and Si53340 data
sheets are available on the Silicon Labs website [Ref 19].
X-Ref Target - Figure 3-10
Figure 3-10: Programmable User MGT Clock
X16379-050117
(I XILINX¢ Marx-lama 224 351 ——I““‘ “‘“‘ M“ “ mksrcnxofzzfna ABE—PERM. us-mspcnxou’zzfn7 “57 "15 c“ " 7 7 Ann USER sun new cnocx c i. MGTRBPCLKJP 224 M10 7 7 7 7 7 menu-1' unkspcnxfi 22; “9 M9 USER 5m HGT cnocx c — — AD10 MGTRRBF 224" M“ MGTRRBPJJDIO m—fix‘lv' 1/10,, HGTAVTTRCALikiADS fl 0 ,, o H H .-u N m socinssilmimon J7 9 sum 2 P GNDZ 3 '3 g 115:: Sin HGT cmcx p 1 5m .4 H 0,5; m can; ‘ U o u I" g 2 3 > can 5 .uszn sun m1- cnocx c P E) .2 gunman“ H u USER sun new cnocx c N -———j b J80 cum 2 GND2 3 vssx_sm_nc1_cmcx_n1 5m elm: 4 cm; 5 32K10K-400L5 am: Send Feed back
ZCU106 Board User Guide 53
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
User SMA MGT Clock
[Figure 2-1, callout 48]
The ZCU106 board provides a pair of SMAs for differential AC coupled user MGT clock input
into FPGA U1 MGTH bank 224. This differential signal pair is series-capacitor coupled. The
P-side SMA J79 signal USER_SMA_MGT_CLOCK_P is connected to U1 MGTREFCLK1P pin
AA10. The N-side SMA J80 signal USER_SMA_MGT_CLOCK_N connected to U1
MGTREFCLK1N pin AA9. The user SMA MGT clock circuit is shown in Figure 3-11.
X-Ref Target - Figure 3-11
Figure 3-11: User SMA MGT Clock
X19187-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 54
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
GEM3 Ethernet (MIO 64-77)
[Figure 2-1, callout 12]
The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet
interface (see Figure 3-12), which connects to a TI DP83867IRPAP Ethernet RGMII PHY
before being routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot
strapped to PHY address 5'b01100 (0x0C) and Auto Negotiation is set to Enable.
Communication with the device is covered in the DP83867 RGMII PHY data sheet [Ref 20].
10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 2-1, callout 12]
The ZCU106 board uses the TIDP83867IRPAP Ethernet RGMII PHY [Ref 20] (U98) for
Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII
mode only. The PHY connection to a user-provided Ethernet cable is through a Wurth
7499111221A RJ-45 connector (P12) with built-in magnetics.
The Ethernet connections from XCZU7EV MPSoC U1 to the DP83867IRPAP PHY device at
U98 are listed in Tab le 3 -14 .
X-Ref Target - Figure 3-12
Figure 3-12: Ethernet Block Diagram
Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC
XCZU7EV
(U1) Pin Net Name DP83867 PHY U98
Pin # Pin Name
J31 MIO64_ENET_TX_CLK 40 GTX_CLK
J32 MIO65_ENET_TX_D0 38 TX_DO
J34 MIO66_ENET_TX_D1 37 TX_D1
K28 MIO67_ENET_TX_D2 36 TX_D2
7,
'3,5
*(0
0,2
5*0,,
0',2
5-DQG
0DJQHWLFV
X16527-050117
(I X|L|NXm um. 1v; vccops nus vccogsiavs R183 - —I “LOX m a 53:15 i my PS P01 8 VCC 1 ‘II cm I" Inn n f :3 3 m1 mm a 59 ms" 3 3 5m an; ‘ ENE-1' RESET U59 snuwcmm U99 1 2 é“ L 11* Send Feed back
ZCU106 Board User Guide 55
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Ethernet PHY Reset
The DP83867IRPAP PHY U98 reset circuit is shown in Figure 3-13. The DP83867IRPAP can be
reset by the SW9 pushbutton (U59.6), the MAX16025 U22 MPSoC PS-side POR reset device
(U59.1), or the I2C0 connected U97 TCA6416A I/O expander port P06 pin 10 (U59.3).
K29 MIO68_ENET_TX_D3 35 TX_D3
K30 MIO69_ENET_TX_CTRL 52 TX_EN_TX_CTRL
K31 MIO70_ENET_RX_CLK 43 RX_CLK
K32 MIO71_ENET_RX_D0 44 RX_DO
K33 MIO72_ENET_RX_D1 45 RX_D1
K34 MIO73_ENET_RX_D2 46 RX_D2
L29 MIO74_ENET_RX_D3 47 RX_D3
L30 MIO75_ENET_RX_CTRL 53 RX_DV_RX_CTRL
L33 MIO76_ENET_MDC 20 MDC
L34 MIO77_ENET_MDIO 21 MDIO
Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC (Cont’d)
XCZU7EV
(U1) Pin Net Name DP83867 PHY U98
Pin # Pin Name
X-Ref Target - Figure 3-13
Figure 3-13: Ethernet PHY Reset Circuit
X19174-052417
(I XILINXa Send Feed back
ZCU106 Board User Guide 56
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Ethernet PHY LED Interface
[Figure 2-1, callout 12]
The DP83867IRPAP PHY U98 LED interface (LED_0, LED_2) uses the two LEDs embedded in
the P12 RJ45 connector bezel. LED_1 is LED DS27, which is located on the top of the board
just above the P12 Ethernet RJ45 connector (item 12 in Tabl e 2- 1).The LED functional
description is listed in Table 3- 15 .
The LED functions can be re-purposed with a LEDCR1 register write available via the PHY's
management data interface, MDIO/MDC. LED_2 is assigned to the activity indicator (ACT)
and LED_0 indicates link established. For more Ethernet PHY details, see the TI DS83867
data sheet [Ref 20].
Table 3-15: Ethernet PHY LED Functional Description
Pin Type Description
Name Number
LED_2 61 S, I/O, PD
By default, this pin indicates receive or transmit
activity. Additional functionality is configurable using
LEDCR1[11:8] register bits.
Note: This pin is a strap configuration pin for RGZ devices
only.
LED_1 62 S, I/O, PD
By default, this pin indicates that 100BASE-T link is
established. Additional functionality is configurable
using LEDCR1[7:4] register bits.
LED_0 63 S, I/O, PD
By default, this pin indicates that link is established.
Additional functionality is configurable using
LEDCR1[3:0] register bits.
(I XILINX, Send Feedback
ZCU106 Board User Guide 57
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
CP2108 USB UART Interface
[Figure 2-1, callout 13]
The CP2108 quad USB-UART on the ZCU106 board provides four level-shifted UART
connections through single micro-B USB connector J83. Channel 0 and 1 are PS-side MIO
connections described in the UART0 (MIO 18-19) section. Channel 2 is a PL-side connection
and Channel 3 is connected to MSP430 system controller U41. The USB UART interface
circuit is shown in Figure 3-14. The Silicon Labs CP2108 data sheet is available on the Silicon
Labs website [Ref 19].
X-Ref Target - Figure 3-14
Figure 3-14: USB UART Interface
X16529-050117
(I X|L|NXm vccavsinus C38 0.111! 2 25v menu U52 “I 1 Inn-2 nn 0 n “i: 2 mu m 0 "an m [mm um I 1 :2 n 2 nun-2 m I "an m umz us 0 1 u u ‘ Inn: 215 o a umz as 1 n M u 5 man as 1 a Inc: In ‘ “C ox am soxciu g a] Send Feed back
ZCU106 Board User Guide 58
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
CP2108 Channel 2 PL-Side UART Interface
The CP2108 channel 2 bank 64 PL-side UART interface circuit is shown in Figure 3-15. The
connections from XCZU7EV MPSoC U1 to CP2108 U40 via TSX0104E level shifter U52 are
listed in Tab le 3-16 .
X-Ref Target - Figure 3-15
Figure 3-15: PL-Side USB UART Interface
Table 3-16: XCZU7EV U1 to CP2108 U40 Connections via L/S U52
XCZU7EV (U1)
Pin Net Name CP2108 U40
Pin Name Pin #
AH17 UART2_TXD_O_FPGA_RXD TX_2 16
AL17 UART2_RXD_I_FPGA_TXD RX_2 15
AM15 UART2_RTS_O_B RTS_2 14
AP17 UART2_RTS_I_B CTS_2 13
X19177-050117
(I X|L|NXm “TIL 3V3 usaipounnanivxo C125 OJW 2w nsolon U53 2 HART! m o :3“ 2 VC: HART! m o KSP430 ucno Rm I mm: m I n u mu m I uspuo ucno 'L'xnl 33 A3 34 u ICZ ICl on Gun soxciu Send Feed back
ZCU106 Board User Guide 59
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
CP2108 Channel 3 MSP430 UART Interface
The CP2108 channel 3 MSP430 UART interface circuit is shown in Figure 3-16. The
connections from MSP430 U41 to CP2108 U40 via TSX0104E level shifter U53 are listed in
Tab le 3- 17 .
X-Ref Target - Figure 3-16
Figure 3-16: MSP430 USB UART Interface
Table 3-17: MSP430 U41 to CP2108 U40 Connections via L/S U53
MSP430 U41 Net Name CP2108 U40
Pin Name Pin # Pin Name Pin #
P3_3 26 UART3_TXD_O_MSP430_UCA0_RXD TX_3 4
P3_3 25 UART3_RXD_I_MSP430_UCA0_TXD RX_3 1
X19175-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 60
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
GPIO (MIO 13, 38)
These two GPIO bits are connected to the U41 MSP430 system controller for general
purpose signaling or communications between the Zynq UltraScale+ MPSoC device and the
MSP430 system controller. These signals are level-shifted by TSX0108E U141. The
connections between the U41 system controller and the XCZU7EV MPSoC are listed in
Tab le 3- 18 .
I2C0 (MIO 14-15)
I2C0 connects to MPSoC U1 PS bank 500 and PL bank 65, and to system controller U41, as
shown in Figure 3-18. I2C0 connects to two GPIO 16-bit port expanders (TCA6416A U61 and
U97) and an I2C multiplexer (PCA9544A U60) for controlling resets and power system
enable pins, and accepting various alarm inputs without requiring the PL-side to be
configured. TCA6416A U97 is pin-strapped to respond to I2C address 0x20, and U61 to
0x21. The PCA9544A U60 multiplexer is set to 0x75.
The I2C0 bus also provides access to the PMBus power controllers and PS-side and PL-side
INA226 power monitors via the U60 PCA9544A multiplexer. All PMBus controlled Maxim
regulators are tied to the MAXIM_PMBUS, while the INA226 power monitors are separated
on to PS_PMBUS and PL_PMBUS. Figure 3-17 shows the I2C0 bus topology. Tab le 3- 19 lists
the I2C0 port expander TCA6416A U61 connections and Table 3-2 0 lists the TCA6416A U97
connections. The devices on each bus of the I2C0 multiplexer U60 are identified in
Tab le 3- 21 and the multiplexer bus connections are listed in Tabl e 3-22.
Table 3-18: System Controller U41 GPIO Connections to XCZU7EV U1
XCZU7EV (U1) Pin Net Name MSP430 U41
Pin Name Pin #
AH17 MIO13_PS_GPIO2 20 P1_7
AL17 MIO38_PS_GPIO1 19 P1_6
(I XILINXa Send Feed back
ZCU106 Board User Guide 61
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-17
Figure 3-17: I2C0 Bus Topology
Bank 500
PS I2C0
MIO15/
MIO14
Bank 65
PL I2C0
AH23/AE19
MPS430
22 P3_0
23 P3_1
U1
U1
U41
TCA6416A
TCA6416A
U134
U55
I2C0_SDA/SCL SDA/
SCL
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P00
P01
P02
P03
P04
P05
P06
P10
P11
VCCPSPLL_EN
MGTRAVCC_EN
MGTRAVTT_EN
VCCPSDDRPLL_EN
MI026_PMU_INPUT_LS
SFP_SI5328_INT_ALM
HDMI_SI5324_INT_ALM
MAX6643_OT_B
MAX6643_OT_B
NC
IIC_MUX_RESET_B
GEM3_EXP_RESET_B
FMC_HPC0_PRSNT_M2C_B
U61
SDA/
SCL
U97
PCA9544A
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
PS_PMBUS_SDA/SCL
PL_PMBUS_SDA/SCL
MAXIM_PMBUS_SDA/SCL
SYSMON_SDA/SCL
SDA/
SCL
U60
FMC_HPC1_PRSNT_M2C_B
PL_PMBUS_ALERT
PS_PMBUS_ALERT
MAXIM_PMBUS_ALERT
PL_DDR4_VTERM_EN
PL_DDR4_VPP_2V5_EN
PS_DIMM_VDDQ_TO_PSVCCO_ON
PS_DIMM_SUSPEND_EN
PS_DDR4_VTERM_EN
PS_DDR4_VPP_2V5_EN
0x21
0x20
0x75
L/S
L/S
J160
Note: See the User I2C0 Receptacle
section for more details on J160.
X19176-083017
(I XILINXa Send Feed back
ZCU106 Board User Guide 62
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-19: I2C0 Port Expander TCA6416A U61 Connections
TCA6416A
U61 Schematic Net Name
Connected To
Pin
Name
Pin
No.
Pin
Name Pin No. Reference
Designator Device
SDA 23 I2C0_SDA See connections shown in Figure 3-17.
TCA6416A U61 Addr. 0x21
SCL 22 I2C0_SCL
P00 4 VCCPSPLL_EN 2 B U140 SN74LVC1G08
enable gate for
respective power
rail
P01 5 MGTRAVCC_EN 2 B U112
P02 6 MGTRAVTT_EN 2 B U130
P03 7 VCCPSDDRPLL_EN 2 B U142
P04 8 MIO26_PMU_INPUT_LS 4 B U147 SN74AVC1T45
P05 9 PL_PMBUS_ALERT 3 ALERT
U16,U65,U74,
U75,U79,U80,
U81,U84
INA226 OP AMPS
P06 10 PS_PMBUS_ALERT 3 ALERT
U15,U76,U77,U78,U
87,U85,U86,U88,
U92,U93
INA226 OP AMPS
P07 11 MAXIM_PMBUS_ALERT 9,11,13 ALERT
J84.7,U4,U8,U7
U9,U10,U13,U18,
U46,U47,U49,U63,
U95,U96
MAX15301:9,
MAX15303:11,
MAX20751:13
P10 13 PL_DDR4_VTERM_EN 7 EN U35 TPS51200
P11 14 PL_DDR4_VPP_2V5_EN 5 EN U38 MAX15027
P12 15 PS_DIMM_VDDQ_TO_PSVCCO_ON C2 ON U57 TPS22924
P13 16 PS_DIMM_SUSPEND_EN 1 A U26 OR-GATE
P14 17 PS_DDR4_VTERM_EN 7 EN U36 TPS51200
P15 18 PS_DDR4_VPP_2V5_EN 5 EN U39 MAX15027
(I XILINXa Send Feed back
ZCU106 Board User Guide 63
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Note: The PS_PMBUS and PL_PMBUS INA226 power monitor device I2C addresses are listed in
Tabl e 3 -22. The MAXIM_PMBUS power system device I2C addresses are listed in Ta ble 3-2 2 and
Tabl e 3 -53.
Table 3-20: I2C0 Port Expander TCA6416A U97 Connections
TCA6416A U97
Schematic Net Name
Connected To
Pin
Name Pin No. Pin # Pin Name Reference
Designator Device
SDA 23 I2C0_SDA See connections shown in Figure 3-17.
TCA6416A U97 Addr. 0x20
SCL 22 I2C0_SCL
P00 4 SFP_SI5328_INT_ALM 3 INT_C1B U20 SI5328B
P01 5 HDMI_SI5324_INT_ALM 3 INT_C1B U108 SI5319C
P02 6 MAX6643_OT_B 9 OT_B U128 MAX6643
P03 7 MAX6643_FANFAIL_B 4 FANFAIL_B U128 MAX6643
P05 9 IIC_MUX_RESET_B 3 RESET_B U34,U135 TCA9548A
P06 10 GEM3_EXP_RESET_B 3 2A U59 SN74LVC3G07
P10 13 FMC_HPC0_PRSNT_M2C_B 4 OE U27,J5.H2 NC7SZ66,FMC0
P11 14 FMC_HPC1_PRSNT_M2C_B 4 OE U24,J4.H2 NC7SZ66,FMC1
Table 3-21: I2C0 Multiplexer PCA9544A U60 Address 0x75 Connections
U60 I2C
Mux Port MUX'd I2C Bus Reference Designator Device
0 PS_PMBUS U76,U77,U78,U87,U85,U86,U93,U88,U15,U92 INA226 Power monitor
1 PL_PMBUS U79,U81,U80,U84,U16,U65,U74,U75 INA226 Power monitor
2MAXIM_PMBUS
J84.3,U47,U7,U6,U10,U9,U63,U95,U96,U46,U4,U18,
U13,U49,U8
PMBus connector,
voltage regulators
3 SYSMON U135,U1 I2C1 MUX, MPSoC
(I XILINXa Send Feed back
ZCU106 Board User Guide 64
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-22: I2C0 U60 Address 0x75 MUX Target Bus Connections
Reference
Designator Address Device
PS_PMBUS (U60 Port 0)
U76 0x40 INA226 VCCPSINTFP
U77 0x41 INA226 VCCPSINTLP
U78 0x42 INA226 VCCPSAUX
U87 0x43 INA226 VCCPSPLL
U85 0x44 INA226 MGTRAVCC
U86 0x45 INA226 MGTRAVTT
U93 0x46 INA226 VCCO_PSDDR_504
U88 0x47 INA226 VCCOPS
U15 0x4A INA226 VCCOPS3
U92 0x4B INA226 VCCPSDDRPLL
PL_PMBUS (U60 Port 1)
U79 0x40 INA226 VCCINT
U81 0x41 INA226 VCCBRAM
U80 0x42 INA226 VCCAUX
U84 0x43 INA226 VCC1V2
U16 0x44 INA226 VCC3V3
U65 0x45 INA226 VADJ_FMC
U74 0x46 INA226 MGTAVCC
U75 0x47 INA226 MGTAVTT
MAXIM_PMBUS (U60 Port 2)
J84 NA PMBUS CONN. SDA PIN 3/SCL PIN 1
U47 0x13 MAX15301 VCCINT
U7 0x14 MAX15303 VCCBRAM
U6 0x15 MAX15303 VCCAUX
U10 0x16 MAX15303 VCC1V2
U9 0x17 MAX15303 VCC3V3
U63 0x18 MAX15301 VADJ_FMC
U95 0x72 MAX20751 MGTAVCC
U96 0x73 MAX20751 MGTAVCC
U46 0x0A MAX15301 VCCPSINTFP
U4 0x0B MAX15303 VCCPSINTLP
U18 0x1D MAX15303 DDR4_DIMM_VDDQ
U13 0x10 MAX15303 VCCOPS
(I XILINXa Send Feed back
ZCU106 Board User Guide 65
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
I2C1 (MIO 16-17)
The PS-side I2C1 interface provides access to I2C peripherals through a set of I2C switches.
The I2C1 PS-side connection is shared with the PL-side and the system controller.
Figure 3-18 shows a high-level view of the I2C1 bus connectivity represented in Ta bl e 3-2 3
and Table 3- 24 . TCA9548A U34 is set to 0x74 and TCA9548A U135 is set to 0x75.
U49 0x1A MAX15301 UTIL_3V3
U8 0x1B MAX15303 UTIL_5V0
SYSMON_SDA/SCL (U60 Port 3) (level-shifted via U137)
U1 0x32 U1 BANK 28 B20/A22
Table 3-22: I2C0 U60 Address 0x75 MUX Target Bus Connections (Cont’d)
Reference
Designator Address Device
X-Ref Target - Figure 3-18
Figure 3-18: I2C1 Bus Topology
Bank 500
PS I2C1
Bank 65
MPS430
U1
U1
U41
TCA9548A
TCA9548A
U136
U45
I2C1_SDA/SCL SDA/
SCL
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC4
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC4
SD5/SC5
SD6/SC6
SD7/SC7
IIC_EEPROM_SDA/SCL 0x34
SI5341_SDA/SCL
USER_S1570_SDA/SCL 0x5D
USER_MGT_SI570_SDA/SCL 0x5D
S15328_SDA/SCL
FMC_HPC0_IIC_SDA/SCL
FMC_HPC1_IIC_SDA/SCL
SYSMON_SDA/SCL
DDR4_SODIMM_SDA/SCL
Not Connected
Not Connected
SFP1_IIC_SDA/SCL
SFP0_IIC_SDA/SCL
U34
SDA/
SCL
U135
0x74
0x75
L/S
L/S
MIO17/
MIO16
PL I2C1
AL21/AH19
28 P4_1
29 P4_2
X19319-052417
(I XILINXa Send Feed back
ZCU106 Board User Guide 66
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-23: I2C1 TCA9548A U34 Multiplexer Connections
U34 I2C1 Mux
(Addr 0x74) Port I2C1 Bus Device Target Device Address
0 EEPROM U23 0X34
1 Si5341 clock U69 0X36
2 USER Si570 clock U42 0X5D
3 USER MGT Si570 clock U56 0X5D
4 Si5328 (clock recovery) U20 0X68
5 No connection NA
6 No connection NA
7 No connection NA
Table 3-24: I2C1 TCA9548A U135 Multiplexer Connections
U135 I2C1 Mux
(Addr 0x75) Port I2C1 Bus Device Target Device Address
0FMC HPC0 J5 0X##
1FMC HPC1 J4 0X##
2 SYSMON U1 bank 28 0X32
3 DDR4 SODIMM SKT. J1 0X51
4 No connection NA
5 No connection NA
6SFP1 P2 0X50
7SFP0 P1 0X50
(I X|L|NXm usaipmnmivxo C3 7 1 w. R473 25v 10.01 “54 < mm="" mm.="" 2="" 1="" m.="" 2="" m.="" $32="" if;="" 3="" 1’="" “i="" .1="" $23="" 3:32="" mm="" .="" mm="" m="" a="" .="" g:="" :g="" m;="" m.)="" m="" .="" m.="" m="" i="" ,="" ..="" m="" imza="" m.)="" m="" i:="" k2="" "c1="" “c="" a.="" m="" u="" l="" send="" feed="" back="">
ZCU106 Board User Guide 67
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
UART0 (MIO 18-19)
This is the primary Zynq UltraScale+ MPSoC PS-side UART interface and is connected to the
U40 CP2108 USB-to-Quad-UART bridge with port assignments as listed in Ta ble 3 - 25.
PS-side UART0 is accessed through the U40 CP2108 USB-to-Quad-UART bridge port 0. The
CP2108 channel 0 PS-side UART interface circuit is shown in Figure 3-19. The connections
from XCZU7EV U1 to CP2108 U40 via L/S U54 are listed in Ta ble 3 - 26.
IMPORTANT: Use SiLabs CP210X VCP driver version 6.7.0 or later for proper USB enumeration as
identified in Table 3-27.
UART1 (MIO 20-21)
PS-side UART1 is accessed through the U40 CP2108 USB-to-Quad-UART bridge port 1. The
CP2108 channel 1 PS-side UART interface circuit is shown in Figure 3-19. The connections
from XCZU7EV U1 to CP2108 U40 via L/S U54 are listed in Ta ble 3 - 26.
Table 3-25: CP2108 UART Assignments
CP2108 U40 Zynq UltraScale+ MPSoC
UART0 PS_UART0 (MIO 18-19)
UART1 PS_UART1 (MIO 20-21)
UART2 PL-UART (HD bank 64)
UART3 U41 system controller UART
X-Ref Target - Figure 3-19
Figure 3-19: CP2108 Channels 0 and 1 PS-Side UART Interface
X16374-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 68
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
GPIO (MIO 22-23)
PS-side pushbutton SW19 is connected to MIO22 (pin U1.F28). PS-side LED DS50, physically
placed adjacent to the pushbutton, is connected to MIO23 (pin U1.B29).
CAN1 (MIO 24-25)
The PS-side CAN bus TX and RX MIO nets are wired through TXS0104E level-translator U33
and TI SN65HVD232 CAN-bus transceiver U122 to the 0.1 in pitch 8-pin male header J98
(see Figure 3-20 and Figure 3-21).
Table 3-26: XCZU7EV U1 PS-Side to CP2108 U40 Connections via L/S U54
XCZU7EV U1 Net Name CP2108 U40
Pin Name Pin # Net Name Pin Name Pin #
PS_MIO18 F27 MIO18_UART0_RXD TX_0 57
PS_MIO19 B28 MIO19_UART0_TXD RX_0 56
PS_MIO21 C28 MIO21_UART1_RXD TX_1 49
PS_MIO20 E29 MIO20_UART1_TXD RX_1 48
X-Ref Target - Figure 3-20
Figure 3-20: PS-Side CAN Bus Interface Diagram
TXS0104E SN65HVD232
CANH
CANL
CAN_TX
CAN_RX
X16533-050117
(I XILINXa GOO! O Send Feed back
ZCU106 Board User Guide 69
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Platform Management Unit GPI (MIO 26)
PS-side MIO 26 is reserved as an input to the platform management unit (PMU) for
indicating a warm boot. PS bank 501 MIO26 (U1.A29) is connected to the I2C0 U61
TCA6416APWR bus expander (port P04 U61.8) through L/S U147 SN74AVC1T45. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more details on
the PMU interface.
DisplayPort DPAUX (MIO 27-30)
The Zynq UltraScale+ MPSoC provides a VESA DisplayPort 1.2 source-only controller that
supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The
DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb/s data
rate, which is translated from single-ended MIO signals to the differential DisplayPort AUX
channel, DPAUX (see Tabl e 3- 27). The DisplayPort circuit is shown in Figure 3-22.
X-Ref Target - Figure 3-21
Figure 3-21: PS-Side CAN Bus Interface Connector
Table 3-27: DPAUX/MIO Connections
XCZU7EV (U1) Pin Net Name Level Shifter U114
Pin Name Pin #
A33 MIO30_DP_AUX_IN 2A1 8
A32 MIO29_DP_OE 1A2 7
A31 MIO28_DP_HPD 2A2 9
A30 MIO27_DP_AUX_OUT 1A1 6
60Ω 60Ω
4700 pF
CANH_TERM CANL_TERM
CANL_TERM
CANH_TERM
CANHCANL
GNDGND
X16534-052417
J98
ZCU106 Board User Guide 70
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-22
Figure 3-22: DisplayPort Circuit
X16547-0501
(I XILINXa Send Feed back
ZCU106 Board User Guide 71
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
PMU GPO (MIO 32-37)
The PMU within the Zynq UltraScale+ MPSoC signals power domain changes using the PMU
output pins for deep-sleep mode. The Zynq UltraScale+ MPSoC PMU GPO pins are
connected to inputs of the MSP430 system controller via TXS0108E level-shifter U141. The
connections from MPSoC U1 bank 501 to MSP430 U41 are listed in Ta ble 3-2 8.
Through the I2C0 bus MPSoC MIO pins, the PMU has access to the board power controllers
and power monitors. See Figure 3-17, page 61 for more details.
See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more
details about the PMU interface.
HDMI Video Output
[Figure 2-1, callout 14]
The ZCU106 board provides an HDMI® video output using a TI SN65DP159RGZ re-timer at
U94. The output is provided on a TE Connectivity 1888811-1 right-angle dual-stacked HDMI
type-A receptacle at P7. The SN65DP159RGZ device is a dual mode DisplayPort to
transition-minimized differential signal (TMDS) re-timer supporting digital video interface
(DVI) 1.0, HDMI 1.4b, and 2.0 output signals.
The SN65DP159RGZ device supports the dual mode standard version 1.1 type 1 and type 2
through the digital down converter (DDC) link or AUX channel. The SN65DP159RGZ device
supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K/60 Hz) 8-bits
per color high-resolution video and HDTV with 16-bit color depth at 1080p
(1920 x 1080/60 Hz). The SN65DP159RGZ device can automatically configure itself as a
re-driver at data rates <1 Gb/s, or as a re-timer at more than this data rate. This feature can
be turned off with I2C programming.
Table 3-28: XCZU7EV U1 to MSP430 Connections
XCZU7EV (U1) Pin Net Name MSP430 U41
Pin Name Pin #
C33 MIO37_PMU_GPO5 P1_0 13
C32 MIO36_PMU_GPO4 P1_1 14
C31 MIO35_PMU_GPO3 P1_2 15
B34 MIO34_PMU_GPO2 P1_3 16
B33 MIO33_PMU_GPO1 P1_4 17
B31 MIO32_PMU_GPO0 P1_5 18
(I XILINXa IH $H LLLL Send Feed back
ZCU106 Board User Guide 72
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The HDMI block diagram, the TX interface circuit, and the RX interface circuit are shown in
Figure 3-23, Figure 3-24, and Figure 3-25, respectively. The XCZU7EV MPSoC U1 to HDMI
circuit connections are listed in Table 3-2 9.
X-Ref Target - Figure 3-23
Figure 3-23: HDMI Interface Block Diagram
+8,8<
&%2/+'
407MHI
,(1-
-4
&%2/
,(1-C-'
&%2/
,(1-
6)'C'03'/
+8,
6)*'0/
+8,6<
+8,
6)*'0/
&%2/
,(1-C-'
,(1-C8<C
,(1-C8<C
,(1-C8<C
8<C'0/C0:(7
-'C76'
72(4
(VMZIV
81(7C
81(7C
81(7C
81(7C'0/
,(1-C398
48ST
)(-(
))4631
-'C,(1-C'80
7-'
'PSGO
6IGSZIV]
8<C+8,C6)*C'0/
,(1-C6<C
,(1-C6<C
,(1-C6<C
81(7
6IXMQIV ,(1-C-2
4&SXXSQ
81(7C
81(7C
81(7C
6<C+8,C6)*'0/
'0/&YJJIV
81(7C'0/
-'C72/
-'C,(1-C6<C72/
<
Send Feedback
ZCU106 Board User Guide 73
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-24
Figure 3-24: HDMI TX Interface Circuit
X16535-050117
(I X|L|NXm S E WE £115 £11: an: m : W,- ' Send Feed back
ZCU106 Board User Guide 74
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-25
Figure 3-25: HDMI RX Interface Circuit
X19189-022218
Table 3-29: HDMI Connections to FPGA U1
XCZU7EV
(U1) Pin Schematic Net Name I/O Standard Connected Component
Pin Name Device
AN6 HDMI_TX0_P (1) 8IN_D0P
SN65DP159
(U94)
AN5 HDMI_TX0_N (1) 9IN_D0N
AM4 HDMI_TX1_P (1) 5IN_D1P
AM3 HDMI_TX1_N (1) 6IN_D1N
AL6 HDMI_TX2_P (1) 2IN_D2P
AL5 HDMI_TX2_N (1) 3IN_D2N
G21 HDMI_TX_LVDS_OUT_P LVDS 11 IN_CLKP
F21 HDMI_TX_LVDS_OUT_N LVDS 12 IN_CLKN
N8 HDMI_TX_SRC_SCL LVCMOS33 46 SCL_SRC
N9 HDMI_TX_SRC_SDA LVCMOS33 47 SDA_SRC
N11 HDMI_TX_EN LVCMOS33 42 OE
M12 HDMI_TX_CEC LVCMOS33 24 CEC_A TPD12S016RK
(U70)
N13 HDMI_TX_HPD LVCMOS33 3 HPD_A
(I XILINXa Send Feed back
ZCU106 Board User Guide 75
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
G8 HDMI_SI5324_LOL LVCMOS33 18 LOL
SI5324C (U108)
H8 HDMI_SI5324_RST LVCMOS33 1 RST_B
G14 HDMI_REC_CLOCK_C_P LVDS 16 CKIN1_P
F13 HDMI_REC_CLOCK_C_N LVDS 17 CKIN1_N
AD8 HDMI_SI5324_OUT_C_P (1) 28 CKOUT1_P
AD7 HDMI_SI5324_OUT_C_N (1) 29 CKOUT1_N
AP4 HDMI_RX0_C_P (1) B7 TMDS_DATA0_P
HDMI bottom
port (P7)
AP3 HDMI_RX0_C_N (1) B9 TMDS_DATA0_N
AN2 HDMI_RX1_C_P (1) B4 TMDS_DATA1_P
AN1 HDMI_RX1_C_N (1) B6 TMDS_DATA1_N
AL2 HDMI_RX2_C_P (1) B1 TMDS_DATA2_P
AL1 HDMI_RX2_C_N (1) B3 TMDS_DATA2_N
AC10 HDMI_RX_CLK_C_P (1) B10 TMDS_CLK_P
AC9 HDMI_RX_CLK_C_N (1) B12 TMDS_CLK_N
M8 HDMI_RX_PWR_DET LVCMOS33 3 D Q46
M10 HDMI_RX_HPD LVCMOS33 1 G Q41
N12 HDMI_CTL_SCL LVCMOS33 15 SCL_CTL (2)
P12 HDMI_CTL_SDA LVCMOS33 16 SDA_CTL
M9 HDMI_RX_SNK_SCL LVCMOS33 4 SCL_A TCA9406DCUR
(U158)
M11 HDMI_RX_SNK_SDA LVCMOS33 5 SDA_A
Notes:
1. U1 MGT (I/O standards do not apply).
2. TMDS181IRG (U19), SN65DP159 (U94), M24C64-W (U109), and SI5324C (U108).
Table 3-29: HDMI Connections to FPGA U1 (Cont’d)
XCZU7EV
(U1) Pin Schematic Net Name I/O Standard Connected Component
Pin Name Device
(I X|L|NXm m mm Ina smu m: vctzrn M Hall 515324 run n m‘"’"" , u n mm mm mm H WWW" 1 C66 (2565 C661 51020 2 m1 um um mm? mm mm! “52 1 c670 2 25v) 25v 2 25v 2 In :umr 1T m M Earn a; cin um “53" nssaycrcr- , .6ng u) . 1 R590 2 IE % 0‘ 3 >1 In W "h: :2 8* 7 m 31 u: a“ n '5' fi“ ’5 misxsizlim c n .. —. m as am . x m F 1 72; mm mm on " muccwul . “H, mm," amusxsnlamr , ,5 .C a n “Luminary 5 mm }—. I In “JG—x m 23 c 3 éE "7 1 mu on son In“. “- : 2 .m m u: . . Inna mm m . 2 .2,5 mm us)“ m g m . 15v 25v “ all) 1 11.117! 0 m h an“, m. Send Feed back
ZCU106 Board User Guide 76
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
HDMI Clock Recovery
[Figure 2-1, callout 41]
The ZCU106 board includes a Silicon Labs Si5319C jitter attenuator U108 (2 kHz – 945 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 67
(HDMI_REC_CLOCK_C_P, pin G14 and HDMI_REC_CLOCK_C_N, pin F13) for jitter attenuation.
The jitter attenuated clock (HDMI_SI5324_OUT_C_P (U108 pin 28), HDMI_SI5324_OUT_C_N
(U108 pin 29) is then routed as a series capacitor coupled reference clock to GTH Quad 223
inputs MGTREFCLK0P (U1 pin AD8) and MGTREFCLK0N (U1 pin AD7).
The Si5319C jitter attenuator is used to generate the reference clock for the HDMI
transmitter subsystem. When the HDMI transmitter is used in standalone mode, the
Si5319C operates in free-running mode and uses an external oscillator as the reference.
When the HDMI transmitter is used in pass-through mode, the Si5319C generates a
jitter-attenuated reference clock to drive the HDMI transmitter subsystem with a
phase-aligned version of the HDMI RX subsystem HMDI RX TMDS clock, so that they are
phase aligned. The SI5319C clock and jitter enable functions are controlled by HDMI IP.
Communication with the SI5319C is available over the HDMI_CTL_SDA/SCL bus connected
to the XCZU7EV MPSoC U1 PL bank 87. The jitter attenuated clock circuit is shown in
Figure 3-26.
IMPORTANT: The Silicon Labs Si5319C U108 pin 1 reset net HDMI_SI5324_RST must be driven High to
enable the device. U108 pin 1 net HDMI_SI5324_RST is connected to FPGA U1 bank 87 pin H8.
X-Ref Target - Figure 3-26
Figure 3-26: HDMI Interface Clock Recovery
X19190-050117
(I XILINX¢ Wu an :29: a: , n7 n7 11:: m. .m. mu.» 1.. . ' “ n- "" 3%.: 7 m.“ ”Magi: E . m. m- : , 45...- i sol VIDEO our 3; 57,4913: “" W. _ LchmLcanL gun 3: " In I cijxcuo I—‘T" 5:. m?“ .m I «a ‘ " - 2715 at: ”g; “—1 F—‘ 3}; .. asks ’ 1' --“ wow so: vmsow 7;: cm KL! cm ii 55!!! 55 i ii: ; mama g a ‘1‘: W- uxu4 Send Feed back
ZCU106 Board User Guide 77
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
SDI Video
[Figure 2-1, callout 45]
12G-SDI and SMPTE ST-2082-1 define a bit-serial data interface for the transport of 12 Gb/s
[nominal] component digital signals or packetized data along with the mapping of various
source image formats to the bit-serial data structure. The SDI video circuit is shown in
Figure 3-27.
X-Ref Target - Figure 3-27
Figure 3-27: SDI Video
X19191-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 78
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The SDI video circuit connections to the XCZU7EV MPSoC U1 are listed in Tab le 3-30 .
Table 3-30: SDI Video Connections to MPSoC U1
XCZU7EV
(U1) Pin
Schematic Net
Name I/O Standard Connected Component
Pin Name Device
H23 SDI_MISO(4) LVCMOS18
19 MF1 U139 M23145G
8 MF2 U138 M23428G
24 MF1 U144 M23544G
B21 SDI_SCLK(3) LVCMOS18
21 MF2 U139 M23145G
14 MF3 U138 M23428G
28 MF2 U144 M23544G
L21 SDI_MOSI(3) LVCMOS18
22 MF3 U139 M23145G
6 MF1 U138 M23428G
29 MF3 U144 M23544G
C14 SDI_XALARM_TX(4) LVCMOS18 8 MF4
U139 M23145G
A9 SDI_CS_RCLKR(3) LVCMOS18 13 XCS
AC5 SDI_MGT_TX_N(2) (1) 4SDI_N
AC6 SDI_MGT_TX_P(2) (1) 3SDI_P
J19 SDI_CS_DRVR(3) LVCMOS18 4 MF0 U138 M23428G
J20 SDI_CS_RCVR(3) LVCMOS18 18 XCS_N
U144 M23544G
E13 SDI_XALARM_RX(4) LVCMOS18 9 MF4
AC1 SDI_MGT_RX_N(2) (1) 19 SDO0_N
AC2 SDI_MGT_RX_P(2) (1) 20 SDO0_P
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. Level-shifted VADJ_FMC to PS_DDR4_VPP_2V5 (1.8V-to-2.5V) at U146 SN74AVC8T245.
4. Level-shifted VADJ_FMC to PS_DDR4_VPP_2V5 (1.8V-to-2.5V) at U145 SN74AVC4T245.
(I XILINX¢ « E5, 9. g . 0.: 21$: .\ a AESAUDIO OUT -“ «:2. a .mwn-JL maul-c _NW\" ”aw" E ‘m:‘ . .. .. .3. , 1 C678 R758 _ 1-1 mtg—J. ,— 33" g mm. H H 1.45 3 g - .n 220- E“:: " _ -m. m m 1212:; 2 , in mung» J70 AESAUDIO IN .1, I _,, , i ‘ mm . . .. .. _‘ 5 T2 m_2--=-:—- 19377021: N :2 :vi 3 1 R753 . U149 mwmm —__ ... I" r ms , 1/1“" m u 1 an Iz127 2 v mu...» Send Feed back
ZCU106 Board User Guide 79
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
AES3 Audio
[Figure 2-1, callout 44]
AES3 (also referred to as AES/EBU) is a standard for the exchange of digital audio signals
between professional audio devices. AES3 was jointly developed by the Audio Engineering
Society (AES) and the European Broadcasting Union (EBU). An AES3 signal can carry two
channels of PCM audio over several transmission media including balanced lines,
unbalanced lines, and optical fiber. AES3 has been incorporated into the International
Electrotechnical Commission's standard IEC 60958. Ref_1_IEC 60958-1 2008,
Ref_2_IEC_60958-1_2ndEd_2004-03. The AES3 audio circuit is shown in Figure 3-28 and the
connections are listed in Tab le 3- 31.
X-Ref Target - Figure 3-28
Figure 3-28: AES Audio
X19192-050117
(I XILINXa iv "m 2m: EFF? I .am A5 5 p: Send Feed back
ZCU106 Board User Guide 80
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
SFP/SFP+ Connectors
[Figure 2-1, callout 18]
The ZCU106 board contains a small form-factor pluggable (SFP+) 1x2 dual-connector
(P1, P2) and cage assembly that accepts SFP or SFP+ modules. Figure 3-29 shows a typical
SFP+ module connector circuitry implementation. Ta ble 3-3 2 lists the connections between
the dual connectors and the XCZU7EV MPSoC.
Note: The SFPx_TX_DISABLE_TRANS default 2-pin jumper is On, which means the
SFPx_TX_DISABLE_TRANS net is pulled Low, enabling the TX output of the SFP module.
Table 3-31: AES3 Audio Connections to MPSoC U1
XCZU7EV
(U1) Pin
Schematic Net
Name I/O Standard Connected Component
Pin Name Device
G7 AES_IN LVCMOS33 1 R U149
SN65HVD11DR
AE13 AES_OUT_P(1) (3) 8 T1 SC937-02LF
AF13 AES_OUT_N(2) (3) 5
Notes:
1. Series resistor, inductor, and capacitor coupled.
2. Series resistor and inductor coupled.
3. Transformer coupled by T1 SC937-02LF.
X-Ref Target - Figure 3-29
Figure 3-29: Typical SFP Interface
X19193-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 81
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
SFP/SFP+ Clock Recovery
[Figure 2-1, callout 11]
The ZCU106 board includes a Silicon Labs Si5328B jitter attenuator U20 (8 kHz – 808 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 68
(SFP_REC_CLOCK_C_P, pin H11 and SFP_REC_CLOCK_C_N, pin G11) for jitter attenuation. The
jitter attenuated clock (SFP_SI5328_OUT_C_P (U20 pin 28), SFP_SI5328_OUT_C_N (U20 pin
29)) is then routed as a series capacitor coupled reference clock to GTH Quad 225 inputs
MGTREFCLK1P (U1 pin W10) and MGTREFCLK1N (U1 pin W9).
The primary purpose of this clock is to support synchronous protocols such as CPRI or
OBSAI to perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter
attenuated recovered clock to drive the reference clock inputs of a GTH transceiver. The
system controller configures the SI5328B in free-run mode (see TI MSP430 System
Controller, page 116). The jitter attenuated clock circuit is shown in Figure 3-30.
Table 3-32: ZCU106 FPGA U1 to SFP0 and SFP1 Module Connections
XCZU7EV (U1) Pin Net Name Pin No. Pin Name SFP/SFP+ Module
Y4 SFP0_TX_P 18 TD_P
P1
Y3 SFP0_TX_N 19 TD_N
AA2 SFP0_RX_P 13 RD_P
AA1 SFP0_RX_N 12 RD_N
AE22 SFP0_TX_DISABLE_B 3 TX_DISABLE
W6 SFP1_TX_P 18 TD_P
P2
W5 SFP1_TX_N 19 TD_N
W2 SFP1_RX_P 13 RD_P
W1 SFP1_RX_N 12 RD_N
AF20 SFP1_TX_DISABLE_B 3 TX_DISABLE
Notes:
1. SFPx_TX_DISABLE_B nets implement the LVCMOS12 standard.
(I X|L|NXm , CHE (218 :21: c1015 1'" x5 E m1 ,1 m if m ; 2:? w mm” :h W$ : a; . . 11:02 :5 on: m If 17 A 711: a «.a lnmmcr mmm . "53‘5“ ’ i9" 0"" ’4‘. 112727 A m nun am 9. ”at...” ’ " "‘F . , m, 5“ \ «w mum.” . ‘ a. mi ‘ m. \ \ mum”... 2E2 . SEE 0., m n my". : “7 my: 3 1;; z: 3 g. "33: 35h. lgun %- m ;_; €575 €514 ,m “r L 2 an I_‘ e m L Send Feed back
ZCU106 Board User Guide 82
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-30
Figure 3-30: SFP/SFP+ Clock Recovery
X19194-050117
(I XILINXa L. U1 U1 L. to \I I mono o 1 O 0 2 mono 4 I I mom 0 1 C O 2 mom 4 I I mono 1 3 O O 4 new 5 I I mom 1 3 f) O 4 mom 5 I I mono 2 5 O C 6 WOW 6 I I won] 2 5 C T) 6 mom 6 I I Puono 3 7 C‘ (7 a noun 7 I I mom 3 7 O O a mom 7 I 90010 9” 010 110012 110 on 31311736793: annizxs a?» mgivl a?» _3v3 g” Send Feed back
ZCU106 Board User Guide 83
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
User PMOD GPIO Headers
[Figure 2-1, callout 20, 21]
The ZCU106 evaluation board supports two PMOD GPIO headers J55 (right-angle female)
and J87 (vertical male). The 3.3V PMOD nets are level-shifted and wired to the XCZU7EV
device U1 banks 28, 66, and 68. Figure 3-31 shows the GPIO PMOD headers J55 and J87.
Tab le 3- 33 lists the connections between the XCZU7EV MPSoC and the PMOD connectors.
Maximum PMOD interface speed is 110 Mb/s.
X-Ref Target - Figure 3-31
Figure 3-31: PMOD Connectors
X19195-050117
Table 3-33: XCZU7EV U1 to PMOD Connections
XCZU7EV (U1) Pin Net Name I/O Standard PMOD Pin
B23 PMOD0_0 LVCMOS18 J55.1
A23 PMOD0_1 LVCMOS18 J55.3
F25 PMOD0_2 LVCMOS18 J55.5
E20 PMOD0_3 LVCMOS18 J55.7
K24 PMOD0_4 LVCMOS18 J55.2
L23 PMOD0_5 LVCMOS18 J55.4
L22 PMOD0_6 LVCMOS18 J55.6
D7 PMOD0_7 LVCMOS18 J55.8
AN8 PMOD1_0 LVCMOS18 J87.1
AN9 PMOD1_1 LVCMOS18 J87.3
AP11 PMOD1_2 LVCMOS18 J87.5
AN11 PMOD1_3 LVCMOS18 J87.7
AP9 PMOD1_4 LVCMOS18 J87.2
(I X|L|NXm BANK 68 XCZU7EVFFVC1156 107L6fl7T0l17N1171D6N7687113 Io LGP 1-00 mo map 68 L14 Io:nsu:-rou:u9jm«Cain; 107LSP7T0ILN971D14P7687114 minmjouiminncimmis87.111 tofupirouimimacimwisaixu Io L3]! 10;. us nus" 68 L11 10:13p:1-on:m:m15p:as:n12 BANK 28 XCZU7EVFFVC1156 107L141LTZL7N37667287G24 107L14P712L7N276€7287G23 624 mm mac 65 u I 623 L141: use 55 p I J3 ‘o<)’ 300‘="" 5="" o="" o="" s="" lg‘i="" mm="" 54="" 1.="" k13="" lei!="" ade]!="" 54="" ii="" i="" 7="" ()="" ()="" 11="" l6!="" ads?="" 64="" ‘="" lull="" l5?="" adep="" 54="" p="" 9="" 10="" l5.="" ”14"="" 5‘="" an="" 1.5“="" mm:="" 54="" n="" i="" o="" o="" i'="" k14="" 1-5?="" “141’="" 54="" p="" i="" 1)="" ,\="" n="" 12="" l51:="" 10141)="" 54;="" 311="" 1:4“="" mm="" 54="" ii="" i="" ‘1="" \4="" k12="" l4?="" “71’="" 64="" f="" i="" 13="" ()="" l)="" 14="" ml="" alz'm="" i54="" ‘="" w.="" 5="" 5="" a="" 7="" 54="" 1.12="" mpmnspup="" i="" 1="" 001="" ”’m"="" e="" 17="" o="" o="" u="" m-="" mlsu="" sq="" 19="" o="" o="" 20="" 1.3.-="" mm="" au-="" 2)="" o="" o="" 22="" mums”="" 23="" o="" o="" 24="" lupmxscss‘v="" mgxn="" send="" feed="" back="">
ZCU106 Board User Guide 84
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Prototype Header
[Figure 2-1, callout 42]
The ZCU106 evaluation board provides a 2x12 male pin prototype header J3 that makes ten
GPIO connections available. Figure 3-32 shows connector J3 with its MPSoC (U1)
connections.
AP10 PMOD1_5 LVCMOS18 J87.4
AP12 PMOD1_6 LVCMOS18 J87.6
AN12 PMOD1_7 LVCMOS18 J77.8
Table 3-33: XCZU7EV U1 to PMOD Connections (Cont’d)
XCZU7EV (U1) Pin Net Name I/O Standard PMOD Pin
X-Ref Target - Figure 3-32
Figure 3-32: Prototype Header J3
X19196-050117
(I XILINXa R.A. Female 2x6 PMOD receptacle J 16 0 NC 1 ‘7 \ 2 NC NC “ 4 NC I 12cc SCL 12cc sex. I I met) 5m 12cc 5m I 11 ‘/ 3121272379721; Gin mggvz GED O pins 5/6, 7/8 duplicated Send Feed back
ZCU106 Board User Guide 85
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Tab le 3- 34 lists the connections between the XCZU7EV MPSoC and the prototype header.
User I2C0 Receptacle
[Figure 2-1, callout 21]
The ZCU106 evaluation board supports a PMOD 2X6 receptacle (right-angle female) J160.
Figure 3-33 shows the I2C0 PMOD receptacle J160. The I2C0 nets are a branch of the I2C0
main bus (see Figure 3-17 and I2C0 (MIO 14-15) for more details).
Table 3-34: Prototype Header J3 Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin Net Name I/O Standard Prototype Header J3 Pin
L14 L6P_AD6P_64_P LVCMOS18 8
K13 L6N_AD6N_64_N LVCMOS18 6
K14 L5P_AD14P_64_P LVCMOS18 12
J14 L5N_AD14N_64_N LVCMOS18 10
K12 L4P_AD7P_64_P LVCMOS18 16
J11 L4N_AD7N_64_N LVCMOS18 14
L12 L3P_AD15P_64_P LVCMOS18 20
L11 L3N_AD15N_64_N LVCMOS18 18
G23 L14P_HDGC_65_P LVCMOS18 24
G24 L14N_HDGC_65_N LVCMOS18 22
X-Ref Target - Figure 3-33
Figure 3-33: J160 PMOD I2C0 Right-Angle Receptacle
•••••••••••••
zu n h n n " l390 m w- o. m I: " [387 I :3 " R385 a. 382 n \ . \n “ I an n 378 .. . :3 " l .. 356 {I XILINX, ' \ . \q "l m u- :1: Send Feedback
ZCU106 Board User Guide 86
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
User I/O
[Figure 2-1, callouts 22-25]
The ZCU106 board provides these user and general purpose I/Os:
• Eight user LEDs (callout 22)
°GPIO_LED[7-0]: DS38, DS37, DS39, DS40, DS41, DS42, DS43, DS44
• Five user pushbuttons and CPU reset switch (callouts 24 and 25)
°GPIO_SW_[NESWC]: SW18, SW17, SW16, SW14, SW15
°CPU_RESET: SW20
• 8-position user DIP switch (callout 23)
°GPIO_DIP_SW[7:0]: SW13
Figure 3-34 through Figure 3-36 show the GPIO circuits. Tabl e 3- 35 lists the GPIO to
XCZU9EG U1 connections.
X-Ref Target - Figure 3-34
Figure 3-34: GPIO LEDs
X16539-050117
{I XILINX¢ vcmvz 172237 'ann 11m 1‘ mmm nmumm . 1 ‘ , 2 cm s... , , VH . 1 R350 SW18 L“! 31/101 2 H mm “H" i V!!! [11292 1 11285 1 R295 2 1m: 2 ma 1 ma > 1/1”! > lllfll > 1/)“ z n z n a 1‘ mmm mmm hum-um nmxlnn on nunuuonnc nnoznw w: 1‘“ 11‘“ ”A“ m... a 1*“ mm n th. mo... ,, 7H. 7 1 R341 7 1 11342 ‘1 R348 SW14 J; ”a SW15 .L M“ SW17 J >111“ 1/1“ in vumvz 1 I- T [11283 T 7 mg m 217"“. z 1‘ mm“ “mum uaaunn on muumm 1 1 ‘ z 1 1 ‘ p 2 mm 31?}, . mom n rh. SW: 0 SW16 ‘L f3”? } . «w. 2 I. Send Feedback
ZCU106 Board User Guide 87
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-35
Figure 3-35: GPIO Pushbutton Switches
X16541-052417
(I XILINXa sum-lulu I an: an: 5-1 . —< a,="" fan)="" on="" m="" 2="" a;="" _="" an)="" m="" 5-:="" )="" at="" um:="" m="" m="" .="" :3="" in:="" nu:="" 5-:="" 5="" ed="" 2:="" sun="" my="" 5.2="" ;="" cd="" a:="" an:="" m="" m="" ~="" ‘1‘:="" )0="" sun="" m="" 5m="" .="" 3="" sun="" r335="" '="" 1="" nu!="" ma:="" send="" feed="" back="">
ZCU106 Board User Guide 88
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-36
Figure 3-36: GPIO 8-Pole DIP Switch
VADJ_FMC
X16542-052417
Table 3-35: XCZU7EV U1 to GPIO Connections
XCZU7EV (U1) Pin Net Name I/O Standard Device
GPIO LEDs (active-High)(1)
AL11 GPIO_LED_0 LVCMOS12 DS38.2
AL13 GPIO_LED_1 LVCMOS12 DS37.2
AK13 GPIO_LED_2 LVCMOS12 DS39.2
AE15 GPIO_LED_3 LVCMOS12 DS40.2
AM8 GPIO_LED_4 LVCMOS12 DS41.2
AM9 GPIO_LED_5 LVCMOS12 DS42.2
AM10 GPIO_LED_6 LVCMOS12 DS43.2
AM11 GPIO_LED_7 LVCMOS12 DS44.2
Directional Pushbuttons (active-High)
AG13 GPIO_SW_N LVCMOS12 SW18.3
AC14 GPIO_SW_E LVCMOS12 SW17.3
AK12 GPIO_SW_W LVCMOS12 SW14.3
AP20 GPIO_SW_S LVCMOS12 SW16.3
AL10 GPIO_SW_C LVCMOS12 SW15.3
CPU Reset Pushbutton (active-High)
G13 CPU_RESET LVCMOS18 SW20.3
GPIO DIP SW (active-High)
A17 GPIO_DIP_SW0 LVCMOS18 SW13.8
A16 GPIO_DIP_SW1 LVCMOS18 SW13.7
(I XILINXa Send Feed back
ZCU106 Board User Guide 89
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Power and Status LEDs
[Figure 2-1, area of callout 22]
Tab le 3- 36 defines the power and status LEDs. For user-controlled LEDs, see User I/O,
page 86.
B16 GPIO_DIP_SW2 LVCMOS18 SW13.6
B15 GPIO_DIP_SW3 LVCMOS18 SW13.5
A15 GPIO_DIP_SW4 LVCMOS18 SW13.4
A14 GPIO_DIP_SW5 LVCMOS18 SW13.3
B14 GPIO_DIP_SW6 LVCMOS18 SW13.2
B13 GPIO_DIP_SW7 LVCMOS18 SW13.1
Notes:
1. LEDs are driven through U106 level-shifter (1.2V-to-3.3V).
Table 3-35: XCZU7EV U1 to GPIO Connections (Cont’d)
XCZU7EV (U1) Pin Net Name I/O Standard Device
Table 3-36: Power and Status LEDs
Ref. Des. Net Name LED Color Description
DS1 FPGA_INIT_B Green/Red Green: FPGA initialization was successful
Red: FPGA initialization is in progress
DS2 VCC12_SW Green 12 VDC power on
DS3 VCCAUX_PGOOD Green VCCAUX 1.8 VDC power on
DS4 VCC3V3_PGOOD Green VCC3V3 3.3 VDC power on
DS5 VCCINT_PGOOD Green VCCINT 0.85 VDC power on
DS6 VADJ_FMC_PGOOD Green VADJ_FMC 1.8 VDC (nominal) power on
DS7 VCC1V2_PGOOD Green VCC1V2 1.2 VDC power on
DS8 VCCBRAM_PGOOD Green VCCBRAM 0.85 VDC power on
DS9 MGTAVTT_PGOOD Green MGTAVTT 1.2 VDC power on
DS10 MGTAVCC_PGOOD Green MGTAVCC 0.9 VDC power on
DS11 VCCPSINTFP_PGOOD Green VCCPSINTFP 0.85 VDC power on
DS12 MGTRAVCC_PGOOD Green MGTRAVCC 0.85 VDC power on
DS13 MGTVCCAUX_PGOOD Green MGTVCCAUX 1.81 VDC power on
DS14 VCCPSAUX_PGOOD Green VCCPSAUX 1.81 VDC power on
DS15 VCCPSPLL_PGOOD Green VCCPSPLL 1.2 VDC power on
DS16 VCCPSINTLP_PGOOD Green VCCPSINTLP 0.85 VDC power on
DS17 DDR4_DIMM_VDDQ_PGOOD Green DDR4_DIMM_VDDQ 1.2 VDC power on
DS18 MGTRAVTT_PGOOD Green MGTRAVTT 1.81 VDC power on
(I XILINXa Send Feed back
ZCU106 Board User Guide 90
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
DS19 PS_DDR4_VPP_2V5 Green PS_DDR4_VPP_2V5 2.5 VDC power on
DS20 PL_DDR4_VPP_2V6 Green PL_DDR4_VPP_2V5 2.5 VDC power on
DS21 VCCOPS_PGOOD Green VCCOPS 1.80 VDC power on
DS22 UTIL_5V0_PGOOD Green UTIL_5V0 5 VDC power on
DS24 VCCPSDDRPLL_PGOOD Green VCCPSDDRPLL 1.81 VDC power on
DS25 UTIL_3V3_PGOOD Green UTIL_3V3 3.3 VDC power on
DS26 VCCOPS3_PGOOD Green VCCOPS3 1.81 VDC power on
DS27 ENET_LED_1 Green EHPY U98 1000BASE-T link is established
DS29 UTIL_1V8 Green UTIL_1V8 1.8VDC power on
DS30 PL_DDR4_VTERM_0V60_PGOOD Green PL_DDR4_VTERM 0.6VDC power on
DS31 PS_DDR4_VTERM_0V60_PGOOD Green PS_DDR4_VTERM 0.6VDC power on
DS32 DONE Green MPSoC U1 bit file download is complete.
DS33 PS_ERR_STATUS(1) Green
PS error status indicates a secure lockdown state.
Alternatively, it can be used by the PMU firmware
to indicate system status.
DS34 DP_VCC3V3 Green Display port 3.3VDC power on
DS35 PS_ERR_OUT(1) Red
PS error out is asserted for accidental loss of
power, an error in the PMU that holds the CSU in
reset, or an exception in the PMU.
DS36 POR_RST_B Red
POR U22 asserts RST_B low when any of the
monitored voltages (IN_) falls below its
respective threshold, any EN_ goes low, or MR is
asserted.
DS37-DS44 GPIO_LED_1, GPIO_LED_[0,2:7] Green USER GPIO LEDs
DS46 MSP430_LED1 Green MSP430 U41 GPIO LED
DS47 MSP430_LED0 Green MSP430 U41 GPIO LED
DS49 UTIL_1V13_PG Green UTIL_1V13 1.13VDC power on
DS50 MIO23_LED Green MPSoC U1 Bank 500 GPIO LED
DS51 USB3 MIC2544 U121 FLG Green PS USB 3.0 ULPI VBUS power error
Notes:
1. See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more information about Zynq UltraScale+
MPSoC configuration pins.
Table 3-36: Power and Status LEDs (Cont’d)
Ref. Des. Net Name LED Color Description
{I XILINX¢ ‘01“. [£05 LED7 U L Send Feedback
ZCU106 Board User Guide 91
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-37 shows the power and status LEDs area of the board.
GTH Transceivers
[Figure 2-1, callout 1]
The Zynq UltraScale+ XCZU7EV MPSoC has 20 GTH gigabit transceivers (16.3 Gb/s capable)
on the PL-side.
The GTH transceivers in the XCZU7EV device are grouped into four channels referred to as
Quads. The reference clock for a Quad can be sourced from the Quad above or the Quad
below the GTH Quad of interest. There are five GTH Quads on the ZCU106 board with
connectivity as listed here:
Quad 223:
• MGTREFCLK0 - HDMI_SI5324_OUT_C_P/N
• MGTREFCLK1 - HDMI_RX_CLK_C_P/N
• Contains three GTH transceivers allocated to HDMI_TX/RX[2:0]_P/N
• Contains one GTH transceiver allocated to FMC_HPC1_DP0_C2M/M2C_P/N
X-Ref Target - Figure 3-37
Figure 3-37: Power and Status LEDs
X19197-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 92
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Quad 224:
• MGTREFCLK0 - PCIE_CLK_P/N
• MGTREFCLK1 - USER_SMA_MGT_CLOCK_C_P/N
• Contains four GTH transceivers allocated to PCIE_TX/RX[0:3]_P/N
Quad 225:
• MGTREFCLK0 - FMC_HPC1_GBTCLK0_M2C_C_P/N
• MGTREFCLK1 - SFP_SI5328_OUT_C_P/N
• Contains one GTH transceiver allocated to SDI_MGT_TX/RX_P/N
• Contains one GTH transceiver allocated to SMA_MGT TX/RX_P/N
• Contains two GTH transceivers allocated to SFP[0:1]_TX/RX_P/N
Quad 226:
• MGTREFCLK0 - FMC_HPC0_GBTCLK0_M2C_C_P/N
• MGTREFCLK1 - USER_MGT_SI570_CLOCK1_C_P/N
• Contains four GTH transceivers allocated to FMC_HPC0_DP[0:3]_C2M/M2C_P/N
Quad 227:
• MGTREFCLK0 - FMC_HPC0_GBTCLK1_M2C_C_P/N
• MGTREFCLK1 - USER_MGT_SI570_CLOCK2_C_P/N
• Contains four GTH transceivers allocated to FMC_HPC0_DP[4:7]_C2M/M2C_P/N
(I X|L|NXm Send Feed back
ZCU106 Board User Guide 93
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
GTH transceiver interface assignments on the ZCU106 are shown in Figure 3-38.
X-Ref Target - Figure 3-38
Figure 3-38: GTH Transceiver Bank Assignments
0*7BB
0*7BB
0*7BB
0*7BB
0*7BB5()&/.B
0*7BB5()&/.B
+'0,B
+'0,B
+'0,B
)0&B+3&B'3
+'0,B6,B287
+'0,B5;B&/.
0*7BB
0*7BB
0*7BB
0*7BB
0*7BB5()&/.B
0*7BB5()&/.B
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B*%7&/.
86(5B0*7B6,B&/2&.
0*7BB
0*7BB
0*7BB
0*7BB
0*7BB5()&/.B
0*7BB5()&/.B
3&,(B
3&,(B
3&,(B
3&,(B
3&,(B&/.
86(5B60$B0*7B&/2&.
0*7BB
0*7BB
0*7BB
0*7BB
0*7BB5()&/.B
0*7BB5()&/.B
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B'3
)0&B+3&B*%7&/.
86(5B0*7B6,B&/2&.
0*7BB
0*7BB
0*7BB
0*7BB
0*7BB5()&/.B
0*7BB5()&/.B
6',B0*7
60$B0*7
6)3
6)3
)0&B+3&B*%7&/.B
6)3B6,B287
%$1.
%$1.
%$1.
%$1.
%$1.
X19198-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 94
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
FMC HPC_0
Eight MGTs in a common FPGA column are provided by PL-side MGT banks 226 and 227.
Available MGT reference clocks include the FMC defined GBT clocks 0 and 1 for HPC0, and
a programmable Si570 buffered 1-to-2 clock. Additional MGT reference clocks are located
in adjacent MGT banks.
FMC HPC_1
One MGT is provided by PL-side MGT bank 223. Available MGT reference clocks include the
two HDMI associated clocks HDMI_RX_CLK and HDMI_SI5324_OUT. Additional MGT
reference clocks are located in adjacent MGT banks.
SFP+
Two PL-side GTH transceivers in bank 228 are provided for the Quad SFP+ interface.
Available GTH transceiver reference clocks include the FMC defined GBT clock 0 for HPC1
and a jitter attenuated recovered clock from a Si5328. SFP+ modules typically provide an
I2C based control interface. This I2C interface is accessible for each individual SFP+ module
through the I2C multiplexer topology on the ZCU106.
HDMI
Three PL-side GTH transceivers are dedicated for HDMI source and sink. Modes supported
are 4K, 2K at 60 f/s, and 2160p60. External circuitry for interfacing TMDS signals with the
GTH transceivers is required.
(I XILINXa Send Feed back
ZCU106 Board User Guide 95
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
SMA
One MGT in bank 225 is provided on TX and RX SMA connector pairs. Available MGT clocks
include the FMC defined GBT clock 0 for HPC1 and a jitter attenuated recovered clock from
a Si5328. Table 3- 37 through Ta ble 3 -4 1 list the five GTH transceiver bank (223-227)
connections.
Table 3-37: GTH Transceiver Bank 223 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
AN6 MGTHTXP0 HDMI_TX0_P 8 IN_D0P
SN65DP159RGZ HDMI
re-timer U94
AN5 MGTHTXN0 HDMI_TX0_N 9 IN_D0N
AM4 MGTHTXP1 HDMI_TX1_P 5 IN_D1P
AM3 MGTHTXN1 HDMI_TX1_N 6 IN_D1N
AL6 MGTHTXP2 HDMI_TX2_P 2 IN_D2P
AL5 MGTHTXN2 HDMI_TX2_N 3 IN_D2N
AP4 MGTHRXP0 HDMI_RX0_C_P(1) B7 TMDS_DATA0_P
P7 MOLEX HDMI
bottom port
AP3 MGTHRXN0 HDMI_RX0_C_N(1) B9 TMDS_DATA0_N
AN2 MGTHRXP1 HDMI_RX1_C_P(1) B4 TMDS_DATA1_P
AN1 MGTHRXN1 HDMI_RX1_C_N(1) B6 TMDS_DATA1_N
AL2 MGTHRXP2 HDMI_RX2_C_P(1) B1 TMDS_DATA2_P
AL1 MGTHRXN2 HDMI_RX2_C_N(1) B3 TMDS_DATA2_N
AC10 MGTREFCLK1P HDMI_RX_CLK_C_P(1) B10 TMDS_CLK_P
AC9 MGTREFCLK1N HDMI_RX_CLK_C_N(1) B12 TMDS_CLK_N
AJ6 MGTHTXP3 FMC_HPC1_DP0_C2M_P C2 DP0_C2M_P
FMC HPC1 J4
AJ5 MGTHTXN3 FMC_HPC1_DP0_C2M_N C3 DP0_C2M_N
AK4 MGTHRXP3 FMC_HPC1_DP0_M2C_P C6 DP0_M2C_P
AK3 MGTHRXN3 FMC_HPC1_DP0_M2C_N C7 DP0_M2C_N
AD8 MGTREFCLK0P HDMI_SI5324_OUT_C_P(1) 28 CKOUT1_P SI5319C JITTER
ATTEN. U108
AD7 MGTREFCLK0N HDMI_SI5324_OUT_C_N(1) 29 CKOUT1_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
(I XILINXa Send Feed back
ZCU106 Board User Guide 96
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-38: GTH Transceiver Bank 224 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
AH4 MGTHTXP0 PCIE_TX3_P(1) A29PERp3
PCIe 4-lane edge
connector P3
AH3 MGTHTXN0 PCIE_TX3_N(1) A30PERn3
AJ2 MGTHRXP0 PCIE_RX3_P B27 PETp3
AJ1 MGTHRXN0 PCIE_RX3_N B28 PETn3
AG6 MGTHTXP1 PCIE_TX2_P(1) A25 PERp2
AG5 MGTHTXN1 PCIE_TX2_N(1) A26 PERn2
AG2 MGTHRXP1 PCIE_RX2_P B23 PETp2
AG1 MGTHRXN1 PCIE_RX2_N B24 PETn2
AE6 MGTHTXP2 PCIE_TX1_P(1) A21 PERp1
AE5 MGTHTXN2 PCIE_TX1_N(1) A22 PERn1
AF4 MGTHRXP2 PCIE_RX1_P B19 PETp1
AF3 MGTHRXN2 PCIE_RX1_N B20 PETn1
AD4 MGTHTXP3 PCIE_TX0_P(1) A16 PERp0
AD3 MGTHTXN3 PCIE_TX0_N(1) A17PERn0
AE2 MGTHRXP3 PCIE_RX0_P B14 PETp0
AE1 MGTHRXN3 PCIE_RX0_N B15 PETn0
AB8 MGTREFCLK0P PCIE_CLK_P(1) A13 REFCLK+
AB7 MGTREFCLK0N PCIE_CLK_N(1) A14 REFCLK-
AA10 MGTREFCLK1P USER_SMA_MGT_CLOCK_C_P 1 SIG SMA J79
AA9 MGTREFCLK1N USER_SMA_MGT_CLOCK_C_N 1 SIG SMA J80
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
(I XILINXa Send Feed back
ZCU106 Board User Guide 97
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-39: GTH Transceiver Bank 225 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name Schematic Net Name(2)
Connected To
Pin
No. Pin Name Device
AC6 MGTHTXP0 SDI_MGT_TX_P(1) 3SDI_P
M23145G_14PG
re-clocker
AC5 MGTHTXN0 SDI_MGT_TX_N(1) 4SDI_N
AC2 MGTHRXP0 SDI_MGT_RX_P(1) 20 SDO0_P M23554G_14PG
re-clocker
AC1 MGTHRXN0 SDI_MGT_RX_N(1) 19 SDO0_N
AA6 MGTHTXP1 SMA_MGT_TX_P 1 SIG MGT SMA J72
AA5 MGTHTXN1 SMA_MGT_TX_N 1 SIG MGT SMA J42
AB4 MGTHRXP1 SMA_MGT_RX_C_P(1) 1 SIG MGT SMA J74
AB3 MGTHRXN1 SMA_MGT_RX_C_N(1) 1SIG MGT SMA J73
Y4 MGTHTXP2 SFP0_TX_P 18 TD_P
SFP0 connector P1
Y3 MGTHTXN2 SFP0_TX_N 19 TD_N
AA2 MGTHRXP2 SFP0_RX_P 13 RD_P
AA1 MGTHRXN2 SFP0_RX_N 12 RD_N
W6 MGTHTXP3 SFP1_TX_P 18 TD_P
SFP0 connector P2
W5 MGTHTXN3 SFP1_TX_N 19 TD_N
W2 MGTHRXP3 SFP1_RX_P 13 RD_P
W1 MGTHRXN3 SFP1_RX_N 12 RD_N
Y8 MGTREFCLK0P FMC_HPC1_GBTCLK0_M2C_C_P(1) D4 GBTCLK0_M2C_P FMC HPC1 J4
Y7 MGTREFCLK0N FMC_HPC1_GBTCLK0_M2C_C_N(1) D5 GBTCLK0_M2C_N
W10 MGTREFCLK1P SFP_SI5328_OUT_C_P(1) 28 CKOUT1_P SI5328B U20
W9 MGTREFCLK1N SFP_SI5328_OUT_C_N(1) 29CKOUT1_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
(I XILINXa Send Feed back
ZCU106 Board User Guide 98
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-40: GTH Transceiver Bank 226 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
U6 MGTHTXP0 FMC_HPC0_DP3_C2M_P A30 DP3_C2M_P
FMC HPC0 J5
U5 MGTHTXN0 FMC_HPC0_DP3_C2M_N A31 DP3_C2M_N
V4 MGTHRXP0 FMC_HPC0_DP3_M2C_P A10 DP3_M2C_P
V3 MGTHRXN0 FMC_HPC0_DP3_M2C_N A11 DP3_M2C_N
T4 MGTHTXP1 FMC_HPC0_DP1_C2M_P A22 DP1_C2M_P
T3 MGTHTXN1 FMC_HPC0_DP1_C2M_N A23 DP1_C2M_N
U2 MGTHRXP1 FMC_HPC0_DP1_M2C_P A2 DP1_M2C_P
U1 MGTHRXN1 FMC_HPC0_DP1_M2C_N A3 DP1_M2C_N
R6 MGTHTXP2 FMC_HPC0_DP0_C2M_P C2 DP0_C2M_P
R5 MGTHTXN2 FMC_HPC0_DP0_C2M_N C3 DP0_C2M_N
R2 MGTHRXP2 FMC_HPC0_DP0_M2C_P C6 DP0_M2C_P
R1 MGTHRXN2 FMC_HPC0_DP0_M2C_N C7 DP0_M2C_N
N6 MGTHTXP3 FMC_HPC0_DP2_C2M_P A26 DP2_C2M_P
N5 MGTHTXN3 FMC_HPC0_DP2_C2M_N A27 DP2_C2M_N
P4 MGTHRXP3 FMC_HPC0_DP2_M2C_P A6 DP2_M2C_P
P3 MGTHRXN3 FMC_HPC0_DP2_M2C_N A7 DP2_M2C_N
V8 MGTREFCLK0P FMC_HPC0_GBTCLK0_M2C_C_P(1) D4 GBTCLK0_M2C_P
V7 MGTREFCLK0N FMC_HPC0_GBTCLK0_M2C_C_N(1) D5 GBTCLK0_M2C_N
U10 MGTREFCLK1P USER_MGT_SI570_CLOCK1_C_P(1) 11 Q1_P SI53340 U51
1-to-2 buffer
U9 MGTREFCLK1N USER_MGT_SI570_CLOCK1_C_N(1) 12 Q1_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
(I XILINXa Send Feed back
ZCU106 Board User Guide 99
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-41: GTH Transceiver Bank 227 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
M4 MGTHTXP0 FMC_HPC0_DP6_C2M_P B36 DP6_C2M_P
FMC HPC0 J5
M3 MGTHTXN0 FMC_HPC0_DP6_C2M_N B37 DP6_C2M_N
N2 MGTHRXP0 FMC_HPC0_DP6_M2C_P B16 DP6_M2C_P
N1 MGTHRXN0 FMC_HPC0_DP6_M2C_N B17 DP6_M2C_N
L6 MGTHTXP1 FMC_HPC0_DP5_C2M_P A38 DP5_C2M_P
L5 MGTHTXN1 FMC_HPC0_DP5_C2M_N A39 DP5_C2M_N
L2 MGTHRXP1 FMC_HPC0_DP5_M2C_P A18 DP5_M2C_P
L1 MGTHRXN1 FMC_HPC0_DP5_M2C_N A19 DP5_M2C_N
K4 MGTHTXP2 FMC_HPC0_DP7_C2M_P B32 DP7_C2M_P
K3 MGTHTXN2 FMC_HPC0_DP7_C2M_N B33 DP7_C2M_N
J2 MGTHRXP2 FMC_HPC0_DP7_M2C_P B12 DP7_M2C_P
J1 MGTHRXN2 FMC_HPC0_DP7_M2C_N B13 DP7_M2C_N
H4 MGTHTXP3 FMC_HPC0_DP4_C2M_P A34 DP4_C2M_P
H3 MGTHTXN3 FMC_HPC0_DP4_C2M_N A35 DP4_C2M_N
G2 MGTHRXP3 FMC_HPC0_DP4_M2C_P A14 DP4_M2C_P
G1 MGTHRXN3 FMC_HPC0_DP4_M2C_N A15 DP4_M2C_N
T8 MGTREFCLK0P FMC_HPC0_GBTCLK1_M2C_C_P(1) B20 GBTCLK1_M2C_P
T7 MGTREFCLK0N FMC_HPC0_GBTCLK1_M2C_C_N(1) B21 GBTCLK1_M2C_N
R10 MGTREFCLK1P USER_MGT_SI570_CLOCK2_C_P(1) 13 Q2_P SI53340 U51
1-to-2 buffer
R9 MGTREFCLK1N USER_MGT_SI570_CLOCK2_C_N(1) 14 Q2_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
(I XILINXa 22 22 224 22 22 Send Feed back
ZCU106 Board User Guide 100
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
PCI Express Endpoint Connectivity
[Figure 2-1, callout 36]
The 4-lane PCI Express® edge connector P3 performs data transfers at the rate of 2.5 GT/s
for Gen1 applications, 5.0 GT/s for Gen2 applications, and 8.0 GT/s for Gen3 applications.
The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω
±10%. The PCIe clock is routed as a 100Ω differential pair. The XCZU7EV (-2 speed grade)
supports up to Gen3 x8.
The PCIe reference clock input is from the P3 edge connector. It is AC coupled to MPSoC U1
through the MGTREFCLK0 pins of Quad 224. PCIE_CLK_P is connected to U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock connection is shown in
Figure 3-39 and the PCI Express connector is shown in Figure 3-40.
PCIe lane size is selected by jumper J162 as shown in Figure 3-40. The J162 default = no
jumper, which allows the lane size to be selected based on the IP requirements.
X-Ref Target - Figure 3-39
Figure 3-39: PCIe Edge Connector Clock
PCI Express
Four-Lane
Edge Connector
OE
GND
REFCLK+
REFCLK-
GND
A12
A13
A14
A15
PCIE_CLK_Q0_C_P
PCIE_CLK_Q0_C_N
GND
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
C340
0.1 μf
0.1 μf
C339
P3
X19199-050117
(I X|L|NXm LAN. 5' - mm“. . .c a. :555 ”1..., .leunl . “mm... m m, x at .mm mm” m m, Juan mnmlxl m "m, m- mm mm» mm XIII! alsz Send Feed back
ZCU106 Board User Guide 101
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
See Table 3- 38 for the PCIe P3 edge connector wiring to MPSoC U1.
X-Ref Target - Figure 3-40
Figure 3-40: PCI Express Connector P3 and Lane Size Select Jumper J162
X19200-050117
(I XILINX¢ Q ‘ BANK 505 XCZU7EVFFVC1156 1129 (.10 m: n 1: P5 mum 5:15 my —. ps:mrmo:sos:mo W. psimnxnisnsivzz fl P5 mama sus U34 fix ‘ - - I29 (.11 up n p psimrxmisosinzs WW. PLIIGI'RTmisnsinzn W—l Ps_mnxm_sos_n1 1'3 2 m: psimisosinz ml!" (.12 use n P H mum 5:15 [:31 —. ’ * , P32 v.12 nsno 1': ll PS “Hum 505 1132 ——I ‘ - - m an usao u 1) P5 my: sns n23 —. Ps’mmfsns’nu MM. ‘ - - 1129 in: sun TX P PS mum 505 .29 —. ps’mrm’sns’lzn MEM- 7 7 ’ "33 G13 sun 2x 1) Ps_mnxp3_sos_u33 WSW. PS mm so; '34 —. PS,IL‘T'IRFCLKOP:505:T27 Ps_m'nlrcl.xol_5 0532 a psinmkmnpisosipz'l ps_msmnw_5 n5_1=2 5 ps minimum? 505 I27 wimkmxnfinsjz a PS_II¢‘1'RBFCLXJP_5 u s_u3 1 psimsmleis 05132 Psimnspisnsin: 1 U1 Send Feed back
ZCU106 Board User Guide 102
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
PS GTR Transceivers
[Figure 2-1, callout 1]
The PS GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0) and
SATA, as shown in Figure 3-41.
X-Ref Target - Figure 3-41
Figure 3-41: PS-GTR Lane Assignments
X19201-050117
(I XILINXa M's N13, NE 0cm N15 Dem 513 sum 1x1: cu sun 1x)! .4 u v: s‘lanorsons N1: Hg snnmrxv 2 In“, new I 0°" 8’15 5‘“ P1 1"“ 1 m} menu 2 on mgsn-ugx“ H SATAYIRXN 5m“ $;¢ I an sun 11x P .4‘ In I 1 53“ Pl ‘1 F 5 an} em 7 a a P9 Send Feed back
ZCU106 Board User Guide 103
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Bank 505 DP (DisplayPort) lanes 0 and 1 TX support the 2-channel source only PS-side
DisplayPort circuitry described in DisplayPort DPAUX (MIO 27-30), page 69.
Bank 505 USB0 lane 2 supports the USB3.0 interface described in USB 3.0 Transceiver and
USB 2.0 ULPI PHY, page 40.
Bank 505 SATA1 lane 3 supports SATA connector P9 as shown in Figure 3-42.
Bank 505 reference clocks are connected to the U69 SI5341B clock generator as described
in SI5341B 10 Independent Output Any-Frequency Clock Generator. Bank 505 connections
are shown in Tab le 3 -42 .
X-Ref Target - Figure 3-42
Figure 3-42: PS-GTR SATA
X19202-050117
Table 3-42: PS-GTR Bank 505 Interface Connections
XCZU7EV
(U1) Pin XCZU7EV Pin Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
U29 PS_MGTRTXP0 GT0_DP_TX_P(1) 4ML_LANE1_P
DisplayPort
connector P11
U30 PS_MGTRTXN0 GT0_DP_TX_N(1) 6 ML_LANE1_N
R29 PS_MGTRTXP1 GT1_DP_TX_P(1) 1 ML_LANE0_P
R30 PS_MGTRTXN1 GT1_DP_TX_N(1) 3 ML_LANE0_N
U33 PS_MGTRRXP0 NC NA NA
NA
U34 PS_MGTRRXN0 NC NA NA
T31 PS_MGTRRXP1 NC NA NA
T32 PS_MGTRRXN1 NC NA NA
P31 PS_MGTRTXP2 GT2_USB0_TX_P(1) 9 SSTXP
USB J96
P32 PS_MGTRTXN2 GT2_USB0_TX_N(1) 8 SSTXN
R33 PS_MGTRRXP2 GT2_USB0_RX_P 6 SSRXP
R34 PS_MGTRRXN2 GT2_USB0_RX_N 5 SSRXN
(I XILINXa Send Feed back
ZCU106 Board User Guide 104
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
FPGA Mezzanine Card Interface
[Figure 2-1, callouts 32, 33]
The ZCU106 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)
specification [Ref 23] by providing subset implementations of high pin count connectors at
J5 (HPC0) and J4 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400
pins. The connectors are keyed so that a mezzanine card, when installed in either of these
FMC connectors on the ZCU106 evaluation board, faces away from the board.
FMC HPC0 Connector J5
[Figure 2-1, callout 32]
The FMC connector at J5 (HPC0) implements a subset of the full FMC HPC connectivity:
• 68 single-ended, or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• Eight GTH transceiver DP differential pairs
• Two GBTCLK differential clocks
• 159 ground and 15 power connections
N29 PS_MGTRTXP3 GT3_SATA1_TX_P(1) 2 HTX_P
SATA P9
N30 PS_MGTRTXN3 GT3_SATA1_TX_N(1) 3 HTX_N
N33 PS_MGTRRXP3 GT3_SATA1_RX_P(1) 6 HRX_P
N34 PS_MGTRRXN3 GT3_SATA1_RX_N(1) 5 HRX_N
T27 PS_MGTREFCLK0P NC NA NA NA
T28 PS_MGTREFCLK0N NC NA NA
P27 PS_MGTREFCLK1P GTR_REF_CLK_SATA_C_P(1) 35 OUT3_P
SI5341B U69
P28 PS_MGTREFCLK1N GTR_REF_CLK_SATA_C_N(1) 34 OUT3_N
M27 PS_MGTREFCLK2P GTR_REF_CLK_USB3_C_P(1) 31 OUT2_P
M28 PS_MGTREFCLK2N GTR_REF_CLK_USB3_C_N(1) 30 OUT2_N
M31 PS_MGTREFCLK3P GTR_REF_CLK_DP_C_P(1) 24 OUT0_P
M32 PS_MGTREFCLK3N GTR_REF_CLK_DP_C_N(1) 23 OUT0_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
Table 3-42: PS-GTR Bank 505 Interface Connections (Cont’d)
XCZU7EV
(U1) Pin XCZU7EV Pin Name Schematic Net Name(2) Connected To
Pin No. Pin Name Device
(I XILINXa Send Feed back
ZCU106 Board User Guide 105
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 board FMC VADJ voltage VADJ_FMC_BUS for the J5 (HPC0) and J4 (HPC1) FMC
connectors is determined by the MAX15301 U63 voltage regulator described in Board
Power System, page 122. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The
HPC0 J5 connections to XCZU7EV U1 are shown in Tabl e 3-4 3 through Ta ble 3 -4 6.
Table 3-43: J5 HPC0 FMC Section A and B Connections to XCZU7EV U1
J5 Pin Schematic Net Name I/O
Standard
U1
Pin J5 Pin Schematic Net Name I/O
Standard
U1
Pin
A2 FMC_HPC0_DP1_M2C_P (7) U2 B1 NC
A3 FMC_HPC0_DP1_M2C_N (7) U1 B4 NC
A6 FMC_HPC0_DP2_M2C_P (7) P4 B5 NC
A7 FMC_HPC0_DP2_M2C_N (7) P3 B8 NC
A10 FMC_HPC0_DP3_M2C_P (7) V4 B9 NC
A11 FMC_HPC0_DP3_M2C_N (7) V3 B12 FMC_HPC0_DP7_M2C_P (7) J2
A14 FMC_HPC0_DP4_M2C_P (7) G2 B13 FMC_HPC0_DP7_M2C_N (7) J1
A15 FMC_HPC0_DP4_M2C_N (7) G1 B16 FMC_HPC0_DP6_M2C_P (7) N2
A18 FMC_HPC0_DP5_M2C_P (7) L2 B17 FMC_HPC0_DP6_M2C_N (7) N1
A19 FMC_HPC0_DP5_M2C_N (7) L1 B20 FMC_HPC0_GBTCLK1_M2C_P (1)(7) T8
A22 FMC_HPC0_DP1_C2M_P (7) T4 B21 FMC_HPC0_GBTCLK1_M2C_N (1)(7) T7
A23 FMC_HPC0_DP1_C2M_N (7) T3 B24 NC
A26 FMC_HPC0_DP2_C2M_P (7) N6 B25 NC
A27 FMC_HPC0_DP2_C2M_N (7) N5 B28 NC
A30 FMC_HPC0_DP3_C2M_P (7) U6 B29 NC
A31 FMC_HPC0_DP3_C2M_N (7) U5 B32 FMC_HPC0_DP7_C2M_P (7) K4
A34 FMC_HPC0_DP4_C2M_P (7) H4 B33 FMC_HPC0_DP7_C2M_N (7) K3
A35 FMC_HPC0_DP4_C2M_N (7) H3 B36 FMC_HPC0_DP6_C2M_P (7) M4
A38 FMC_HPC0_DP5_C2M_P (7) L6 B37 FMC_HPC0_DP6_C2M_N (7) M3
A39 FMC_HPC0_DP5_C2M_N (7) L5 B40 NC
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. FPGA U1 JTAG TCK, TMS, TDO pins are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card
is plugged onto J5).
5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13.
6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
7. U1 MGT (I/O standards do not apply).
(I XILINXa Send Feed back
ZCU106 Board User Guide 106
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-44: J5 HPC0 FMC Section C and D Connections to XCZU7EV U1
J5
Pin Schematic Net Name I/O
Standard
U1
Pin
J5
Pin Schematic Net Name I/O
Standard
U1
Pin
C2 FMC_HPC0_DP0_C2M_P (7) R6 D1 VADJ_FMC_PGOOD (6)
C3 FMC_HPC0_DP0_C2M_N (7) R5 D4 FMC_HPC0_GBTCLK0_M2C_P (1) (1)(7) V8
C6 FMC_HPC0_DP0_M2C_P (7) R2 D5 FMC_HPC0_GBTCLK0_M2C_N (1) (1)(7) V7
C7 FMC_HPC0_DP0_M2C_N (7) R1 D8 FMC_HPC0_LA01_CC_P LVCMOS18 H18
C10 FMC_HPC0_LA06_P LVCMOS18 H19 D9 FMC_HPC0_LA01_CC_N LVCMOS18 H17
C11 FMC_HPC0_LA06_N LVCMOS18 G19 D11 FMC_HPC0_LA05_P LVCMOS18 K17
C14 FMC_HPC0_LA10_P LVCMOS18 L15 D12 FMC_HPC0_LA05_N LVCMOS18 J17
C15 FMC_HPC0_LA10_N LVCMOS18 K15 D14 FMC_HPC0_LA09_P LVCMOS18 H16
C18 FMC_HPC0_LA14_P LVCMOS18 C13 D15 FMC_HPC0_LA09_N LVCMOS18 G16
C19 FMC_HPC0_LA14_N LVCMOS18 C12 D17 FMC_HPC0_LA13_P LVCMOS18 G15
C22 FMC_HPC0_LA18_CC_P LVCMOS18 D11 D18 FMC_HPC0_LA13_N LVCMOS18 F15
C23 FMC_HPC0_LA18_CC_N LVCMOS18 D10 D20 FMC_HPC0_LA17_CC_P LVCMOS18 F11
C26 FMC_HPC0_LA27_P LVCMOS18 A8 D21 FMC_HPC0_LA17_CC_N LVCMOS18 E10
C27 FMC_HPC0_LA27_N LVCMOS18 A7 D23 FMC_HPC0_LA23_P LVCMOS18 B11
C30 FMC_HPC0_IIC_SCL (2) D24 FMC_HPC0_LA23_N LVCMOS18 A11
C31 FMC_HPC0_IIC_SDA (2) D26 FMC_HPC0_LA26_P LVCMOS18 B9
C34 GND D27 FMC_HPC0_LA26_N LVCMOS18 B8
C35 VCC12_SW D29 FMC_HPC0_TCK_BUF (3)
C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF (4)
C39 UTIL_3V3 D31 FMC_HPC0_TDO_HPC1_TDI (3)(4)
D32 UTIL_3V3
D33 FMC_HPC0_TMS_BUF (3)
D34 NC
D35 GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. FPGA U1 JTAG TCK, TMS, TDO pins are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card is
plugged onto J5).
5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13.
6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
7. U1 MGT (I/O standards do not apply).
(I XILINXa Send Feed back
ZCU106 Board User Guide 107
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-45: J5 HPC0 FMC Section E and F Connections to XCZU7EV U1
J5
Pin Schematic Net Name I/O
Standard
U1
Pin
J5
Pin Schematic Net Name I/O
Standard
U1
Pin
E2 NC F1 FMC_HPC0_PG_M2C P/U to 3.3V
via R277
E3 NC F4 NC
E6 NC F5 NC
E7 NC F7 NC
E9 NC F8 NC
E10 NC F10 NC
E12 NC F11 NC
E13 NC F13 NC
E15 NC F14 NC
E16 NC F16 NC
E18 NC F17 NC
E19 NC F19 NC
E21 NC F20 NC
E22 NC F22 NC
E24 NC F23 NC
E25 NC F25 NC
E27 NC F26 NC
E28 NC F28 NC
E30 NC F29 NC
E31 NC F31 NC
E33 NC F32 NC
E34 NC F34 NC
E36 NC F35 NC
E37 NC F37 NC
E39 VADJ_FMC_BUS F38 NC
F40 VADJ_FMC_BUS
(I XILINXa Send Feed back
ZCU106 Board User Guide 108
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-46: J5 HPC0 FMC Section G and H Connections to XCZU7EV U1
J5 Pin Schematic Net Name I/O
Standard
U1
Pin
J5
Pin Schematic Net Name I/O
Standard
U1
Pin
G2 FMC_HPC0_CLK1_M2C_P LVDS G10 H1 NC
G3 FMC_HPC0_CLK1_M2C_N LVDS F10 H2 FMC_HPC0_PRSNT_M2C_B (5)
G6 FMC_HPC0_LA00_CC_P LVDS F17 H4 FMC_HPC0_CLK0_M2C_P LVDS E15
G7 FMC_HPC0_LA00_CC_N LVDS F16 H5 FMC_HPC0_CLK0_M2C_N LVDS E14
G9 FMC_HPC0_LA03_P LVCMOS18 K19 H7 FMC_HPC0_LA02_P LVCMOS18 L20
G10 FMC_HPC0_LA03_N LVCMOS18 K18 H8 FMC_HPC0_LA02_N LVCMOS18 K20
G12 FMC_HPC0_LA08_P LVCMOS18 E18 H10 FMC_HPC0_LA04_P LVCMOS18 L17
G13 FMC_HPC0_LA08_N LVCMOS18 E17 H11 FMC_HPC0_LA04_N LVCMOS18 L16
G15 FMC_HPC0_LA12_P LVCMOS18 G18 H13 FMC_HPC0_LA07_P LVCMOS18 J16
G16 FMC_HPC0_LA12_N LVCMOS18 F18 H14 FMC_HPC0_LA07_N LVCMOS18 J15
G18 FMC_HPC0_LA16_P LVCMOS18 D17 H16 FMC_HPC0_LA11_P LVCMOS18 A13
G19 FMC_HPC0_LA16_N LVCMOS18 C17 H17 FMC_HPC0_LA11_N LVCMOS18 A12
G21 FMC_HPC0_LA20_P LVCMOS18 F12 H19 FMC_HPC0_LA15_P LVCMOS18 D16
G22 FMC_HPC0_LA20_N LVCMOS18 E12 H20 FMC_HPC0_LA15_N LVCMOS18 C16
G24 FMC_HPC0_LA22_P LVCMOS18 H13 H22 FMC_HPC0_LA19_P LVCMOS18 D12
G25 FMC_HPC0_LA22_N LVCMOS18 H12 H23 FMC_HPC0_LA19_N LVCMOS18 C11
G27 FMC_HPC0_LA25_P LVCMOS18 C7 H25 FMC_HPC0_LA21_P LVCMOS18 B10
G28 FMC_HPC0_LA25_N LVCMOS18 C6 H26 FMC_HPC0_LA21_N LVCMOS18 A10
G30 FMC_HPC0_LA29_P LVCMOS18 K10 H28 FMC_HPC0_LA24_P LVCMOS18 B6
G31 FMC_HPC0_LA29_N LVCMOS18 J10 H29 FMC_HPC0_LA24_N LVCMOS18 A6
G33 FMC_HPC0_LA31_P LVCMOS18 F7 H31 FMC_HPC0_LA28_P LVCMOS18 M13
G34 FMC_HPC0_LA31_N LVCMOS18 E7 H32 FMC_HPC0_LA28_N LVCMOS18 L13
G36 FMC_HPC0_LA33_P LVCMOS18 C9 H34 FMC_HPC0_LA30_P LVCMOS18 E9
G37 FMC_HPC0_LA33_N LVCMOS18 C8 H35 FMC_HPC0_LA30_N LVCMOS18 D9
G39 VADJ_FMC_BUS H37 FMC_HPC0_LA32_P LVCMOS18 F8
H38 FMC_HPC0_LA32_N LVCMOS18 E8
H40 VADJ_FMC_BUS
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. FPGA U1 JTAG TCK, TMS, TDO pins are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card
is plugged onto J5).
5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13.
6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
7. U1 MGT (I/O standards do not apply).
(I XILINXa Send Feed back
ZCU106 Board User Guide 109
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-47: J5 HPC0 FMC Section J and K Connections to XCZU7EV U1
J5 Pin Schematic Net Name I/O
Standard
U1
Pin
J5
Pin Schematic Net Name I/O
Standard U1 Pin
J2 NC K1 NC
J3 NC K4 NC
J6 NC K5 NC
J7 NC K7 NC
J9 NC K8 NC
J10 NC K10 NC
J12 NC K11 NC
J13 NC K13 NC
J15 NC K14 NC
J16 NC K16 NC
J18 NC K17 NC
J19 NC K19 NC
J21 NC K20 NC
J22 NC K22 NC
J24 NC K23 NC
J25 NC K25 NC
J27 NC K26 NC
J28 NC K28 NC
J30 NC K29 NC
J31 NC K31 NC
J33 NC K32 NC
J34 NC K34 NC
J36 NC K35 NC
J37 NC K37 NC
J39 NC K38 NC
K40 NC
(I XILINXa Send Feed back
ZCU106 Board User Guide 110
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
FMC HPC1 Connector J4
[Figure 2-1, callout 33]
The FMC connector at J4 (HPC1) implements a subset of the full FMC HPC connectivity:
• 34 single-ended, or 17 differential user-defined pairs (LA[00:16])
• One GTH transceiver DP differential pair
• One GBTCLK differential clocks
• 159 ground and 15 power connections
The ZCU106 board FMC VADJ voltage VADJ_FMC_BUS for the J5 (HPC0) and J4 (HPC1) FMC
connectors is determined by the MAX15301 U63 voltage regulator described in Board
Power System. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The HPC1 J4
connections to XCZU7EV U1 are shown in Table 3 -4 8 through Tab le 3 -5 2.
Table 3-48: J4 HPC1 FMC Section A and B Connections to XCZU7EV U1
J4 Pin Schematic Net Name I/O
Standard U1 Pin J4 Pin Schematic Net Name I/O
Standard U1 Pin
A2 NC B1 NC
A3 NC B4 NC
A6 NC B5 NC
A7 NC B8 NC
A10 NC B9 NC
A11 NC B12 NC
A14 NC B13 NC
A15 NC B16 NC
A18 NC B17 NC
A19 NC B20 NC
A22 NC B21 NC
A23 NC B24 NC
A26 NC B25 NC
A27 NC B28 NC
A30 NC B29 NC
A31 NC B32 NC
A34 NC B33 NC
A35 NC B36 NC
A38 NC B37 NC
A39 NC B40 NC
(I XILINXa Send Feed back
ZCU106 Board User Guide 111
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-49: J4 HPC1 FMC Section C and D Connections to XCZU7EV U1
J4
Pin Schematic Net Name I/O
Standard
U1
Pin
J4
Pin Schematic Net Name I/O Standard U1
Pin
C2 FMC_HPC1_DP0_C2M_P (7) AJ6 D1 VADJ_FMC_PGOOD (6)
C3 FMC_HPC1_DP0_C2M_N (7) AJ5 D4 FMC_HPC1_GBTCLK0_M2C_P (1)(7) Y8
C6 FMC_HPC1_DP0_M2C_P (6) AK4 D5 FMC_HPC1_GBTCLK0_M2C_N (1)(6) Y7
C7 FMC_HPC1_DP0_M2C_N (7) AK3 D8 FMC_HPC1_LA01_CC_P LVDS E24
C10 FMC_HPC1_LA06_P LVDS H21 D9 FMC_HPC1_LA01_CC_N LVDS D24
C11 FMC_HPC1_LA06_N LVDS H22 D11 FMC_HPC1_LA05_P LVDS G25
C14 FMC_HPC1_LA10_P LVDS F22 D12 FMC_HPC1_LA05_N LVDS G26
C15 FMC_HPC1_LA10_N LVDS E22 D14 FMC_HPC1_LA09_P LVDS G20
C18 FMC_HPC1_LA14_P LVDS D20 D15 FMC_HPC1_LA09_N LVDS F20
C19 FMC_HPC1_LA14_N LVDS D21 D17 FMC_HPC1_LA13_P LVDS C21
C22 NC D18 FMC_HPC1_LA13_N LVDS C22
C23 NC D20 NC
C26 NC D21 NC
C27 NC D23 NC
C30 FMC_HPC1_IIC_SCL (2) D24 NC
C31 FMC_HPC1_IIC_SDA (2) D26 NC
C34 GND D27 NC
C35 VCC12_SW D29 FMC_HPC1_TCK_BUF (3)
C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF (4)
C39 UTIL_3V3 D31 FMC_HPC1_TDO_HPC1_TDI (3)(4)
D32 UTIL_3V3
D33 FMC_HPC1_TMS_BUF (3)
D34 NC
D35 GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 6 and 7.
3. FPGA U1 JTAG TCK, TMS, and TDO pins are buffered by U48 SN74AVC8T245.
4. J4 HPC1 TDO-TDI connections to U24 HPC1 FMC JTAG bypass switch (N.C. normally-closed/bypassing J4 until an FMC card
is plugged onto J4).
5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
6. U1 MGT (I/O standards do not apply).
(I XILINXa Send Feed back
ZCU106 Board User Guide 112
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-50: J4 HPC1 FMC Section E and F Connections to XCZU7EV U1
J4 Pin Schematic Net Name I/O
Standard U1 Pin J4 Pin Schematic Net Name I/O
Standard U1 Pin
E2 NC F1 FMC_HPC1_PG_M2C P/U to 3.3V via R250
E3 NC F4 NC
E6 NC F5 NC
E7 NC F7 NC
E9 NC F8 NC
E10 NC F10 NC
E12 NC F11 NC
E13 NC F13 NC
E15 NC F14 NC
E16 NC F16 NC
E18 NC F17 NC
E19 NC F19 NC
E21 NC F20 NC
E22 NC F22 NC
E24 NC F23 NC
E25 NC F25 NC
E27 NC F26 NC
E28 NC F28 NC
E30 NC F29 NC
E31 NC F31 NC
E33 NC F32 NC
E34 NC F34 NC
E36 NC F35 NC
E37 NC F37 NC
E39 VADJ_FMC_BUS F38 NC
F40 VADJ_FMC_BUS
(I XILINXa Send Feed back
ZCU106 Board User Guide 113
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-51: J4 HPC1 FMC Section G and H Connections to XCZU7EV U1
J4
Pin Schematic Net Name I/O Standard U1
Pin
J4
Pin Schematic Net Name I/O
Standard
U1
Pin
G2 FMC_HPC1_CLK1_M2C_P LVDS H1 NC
G3 FMC_HPC1_CLK1_M2C_N LVDS H2 FMC_HPC1_PRSNT_M2C_B (1)
G6 FMC_HPC1_LA00_CC_P LVDS B18 H4 FMC_HPC1_CLK0_M2C_P LVDS F23
G7 FMC_HPC1_LA00_CC_N LVDS B19 H5 FMC_HPC1_CLK0_M2C_N LVDS E23
G9 FMC_HPC1_LA03_P LVDS J21 H7 FMC_HPC1_LA02_P LVDS K22
G10 FMC_HPC1_LA03_N LVDS J22 H8 FMC_HPC1_LA02_N LVDS K23
G12 FMC_HPC1_LA08_P LVDS J25 H10 FMC_HPC1_LA04_P LVDS J24
G13 FMC_HPC1_LA08_N LVDS H26 H11 FMC_HPC1_LA04_N LVDS H24
G15 FMC_HPC1_LA12_P LVDS E19 H13 FMC_HPC1_LA07_P LVDS D22
G16 FMC_HPC1_LA12_N LVDS D19 H14 FMC_HPC1_LA07_N LVDS C23
G18 FMC_HPC1_LA16_P LVDS C18 H16 FMC_HPC1_LA11_P LVDS A20
G19 FMC_HPC1_LA16_N LVDS C19 H17 FMC_HPC1_LA11_N LVDS A21
G21 NC H19 FMC_HPC1_LA15_P LVDS A18
G22 NC H20 FMC_HPC1_LA15_N LVDS A19
G24 NC H22 NC
G25 NC H23 NC
G27 NC H25 NC
G28 NC H26 NC
G30 NC H28 NC
G31 NC H29 NC
G33 NC H31 NC
G34 NC H32 NC
G36 NC H34 NC
G37 NC H35 NC
G39 VADJ_FMC_BUS H37 NC
H38 NC
H40 VADJ_FMC_BUS
Notes:
1. FMC_HPC1_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U24.4 OE control signal is driven from I2C I/O expander
U97.14.
(I XILINXa Send Feed back
ZCU106 Board User Guide 114
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-52: J4 HPC1 FMC Section J and K Connections to XCZU7EV U1
J4 Pin Schematic Net Name I/O
Standard U1 Pin J4 Pin Schematic Net Name I/O
Standard U1 Pin
J2 NC K1 NC
J3 NC K4 NC
J6 NC K5 NC
J7 NC K7 NC
J9 NC K8 NC
J10 NC K10 NC
J12 NC K11 NC
J13 NC K13 NC
J15 NC K14 NC
J16 NC K16 NC
J18 NC K17 NC
J19 NC K19 NC
J21 NC K20 NC
J22 NC K22 NC
J24 NC K23 NC
J25 NC K25 NC
J27 NC K26 NC
J28 NC K28 NC
J30 NC K29 NC
J31 NC K31 NC
J33 NC K32 NC
J34 NC K34 NC
J36 NC K35 NC
J37 NC K37 NC
J39 NC K38 NC
K40 NC
(I X|L|NXm Keyed Fan Header vccu .- 1195 x955 ZZ‘PL J "'"":21%:;Z?: Fan Controller I ‘ Ragtrauzy ‘ “9‘ “’53 2 n1 1‘ g“ '1/Ifinglliw51/ISI s m “ m ,. m ,3 m, mm m”. . mun-In}; / . m" n mm .0 mm )1 L "ME, mm.“ 2 mm Send Feed back / 1,7.
ZCU106 Board User Guide 115
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Cooling Fan Connector
[Figure 2-1, near callout 10]
The ZCU106 cooling fan connector is shown in Figure 3-43.
The ZCU106 uses the Maxim MAX6643 fan controller, which autonomously controls the fan
speed by controlling the pulse width modulation (PWM) signal to the fan based on the die
temperature sensed via the FPGA's DXP and DXN pins. The fan rotates slowly (acoustically
quiet) when the FPGA is cool and rotates faster as the FPGA heats up (acoustically noisy).
The fan speed (PWM) versus the FPGA die temperature algorithm along with the over
temperature set point and fan failure alarm mechanisms are defined by the strapping
resistors on the MAX6643 device. The over temperature and fan failures alarms can be
monitored by the any available processor in the FPGA by polling the I2C expander, U97. See
the MAX6643 [Ref 22] data sheet for more information on the device circuit implementation
on this board.
Note: At initial power on, it is normal for the fan controller to energize at full speed for a few
seconds.
X-Ref Target - Figure 3-43
Figure 3-43: ZCU106 12V Fan Controller
X19203-052417
(I XILINXa Send Feed back
ZCU106 Board User Guide 116
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
VADJ_FMC Power Rail
The ZCU106 evaluation board implements the ANSI/VITA 57.1 section 5.5.1 IPMI support
functionality. The power control of the VADJ_FMC power rail is managed by the U41 system
controller. This rail powers both the FMC HPC0 (J5) and the FMC HPC1 (J4) VADJ pins, as well
as the XCZU7EV HP banks 28, 67, and 68. The valid values of the VADJ_FMC rail are 1.2V, 1.5V,
and 1.8V.
At power on, the system controller detects if an FMC module is connected to each interface:
• If no cards are attached to the FMC ports, the VADJ voltage is set to 1.8V.
• When one FMC card is attached, its IIC EEPROM is read to find a VADJ voltage
supported by both the ZCU106 board and the FMC module, within the available
choices of 1.8V, 1.5V, 1.2V, and 0.0V.
• When two FMC cards are attached with differing VADJ requirements, VADJ_FMC is set to
the lowest value compatible with the ZCU106 board and the FMC modules, within the
available choices of 1.8V, 1.5V, 1.2V, and 0.0V.
• If no valid information is found in an FMC card IIC EEPROM, the VADJ_FMC rail is set to
0.0V.
The system controller user interface allows the FMC IPMI routine to be overridden and an
explicit value can be set for the VADJ_FMC rail. Override mode is useful for FMC mezzanine
cards that do not contain valid IPMI EPROM data defined by the ANSI/VITA57.1
specification.
TI MSP430 System Controller
[Figure 2-1, callout 19]
The ZCU106 board includes an on-board MSP430 with integrated power advantage
demonstration and system controller firmware. A host PC resident system controller user
interface (SCUI) is provided on the ZCU106 web page. This GUI enables you to query and
control select programmable features such as clocks, FMC functionality, and power system
parameters. The ZCU106 web page also includes a tutorial on the SCUI (XTP433) [Ref 12]
and board setup instructions (XTP435) [Ref 13].
(I XILINX¢ ‘ a: 1Voltages[power lmc lGelEEPROMData Set ‘Read [saucer nequenty Se! Si570 Use! Flequemy Frequency (10-800MH2): [ 52: 5.570 MGI Frequency Frequency (10-800mm): Set 565328 Fvequency Frequency (0.008-305MH1). Send Feed back
ZCU106 Board User Guide 117
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The board setup instructions are summarized here:
1. Ensure that the Silicon Labs VCP USB-UART drivers are installed (see [Ref 8]).
2. Download the SCUI host PC application.
3. Connect the micro-USB to ZCU106 USB-UART connector (J83).
4. Power-cycle the ZCU106.
5. Observe that SYSCTLR LED0 (DS47) blinks and LED1 DS46 is illuminated.
6. Launch the SCUI.
The SCUI GUI is shown in Figure 3-44.
X-Ref Target - Figure 3-44
Figure 3-44: System Controller User Interface
X19204-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 118
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
On first use of the SCUI, select FMC > Set VADJ > Boot-up and click USE FMC EEPROM
Voltage. The SCUI buttons are grayed out during command execution and return to their
original appearance when ready to accept a new command.
See the System Controller GUI Tutorial (XTP433) [Ref 12] and the ZCU106 Software Install
and Board Setup Tutorial (XTP435) [Ref 13] for more information on installing and using the
system controller utility.
Switches
[Figure 2-1, callouts 27, 29, 31, and 46]
The ZCU106 board includes power, configuration, and reset switches:
• SW1 power on/off slide switch (callout 29)
•SW5 (PS_PROG_B), active-Low pushbutton (callout 31)
• SW3 (SRST_B), active-Low pushbutton (callout 27)
•SW4 (POR_B), active-Low pushbutton (callout 27)
• SW6 U1 MPSoC PS bank 503 4-pole mode DIP switch (callout 46)
(I XILINX¢ m. g a“. m. T $9 T g ,; "ax : Km}; :4. : m... m :x m. mm _; a m. J; a: m mun (mm - 1;}: .152 7;” a. m T“ EC n". A: .. on Send Feed back
ZCU106 Board User Guide 119
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Power On/Off Slide Switch
[Figure 2-1, callout 29]
The ZCU106 board power switch is SW1. Sliding the switch actuator from the off to the on
position applies 12V power from J52, a 6-pin mini-fit connector. Green LED DS2 illuminates
when the ZCU106 board power is on. See Board Power System for details on the on-board
power system.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the ZCU106 board power
connector J52. The ATX 6-pin connector has a different pin-out than J52. Connecting an ATX 6-pin
connector into J52 damages the ZCU106 board and voids the board warranty.
Figure 3-45 shows the power connector J52, power switch SW1, and LED indicator DS2.
X-Ref Target - Figure 3-45
Figure 3-45: Power Input
X16548-050117
(I X|L|NXm 1.8V vccogs 37 BUS 1 121.4 Pushhutton 2 ' :élsw TL3301EF100QG l PS PROG B . 1 P1 L P2 2 . 3 p3 TP D4 4 SW5 —. Send Feed back
ZCU106 Board User Guide 120
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Program_B Pushbutton
[Figure 2-1, callout 31]
PS_PROG_B pushbutton switch SW5 grounds the XCZU7EV MPSoC PS_PROG_B pin T24
when pressed (see Figure 3-46). This action clears the programmable logic configuration,
which can then be acted on by the PS software. See the Zynq UltraScale+ MPSoC Technical
Reference Manual (UG1085) [Ref 3] for information about Zynq UltraScale+ MPSoC
configuration.
X-Ref Target - Figure 3-46
Figure 3-46: PS_PROG_B Pushbutton Switch SW5
X16549-052417
{I XILINX¢ . s ”“42 iii.“ Inn. 3') “MALI"! mu m I 127 ’ 3.5." no.3; R265’R241 z 25v 1 K11 $331 :7}; "mm 7 .. .. “I m 3.29“ z m mu mo...“ I 523‘ PS POR 5 ,m m“. ....n.m‘m ‘52 mm». omzn mum ' mm...“ a , ‘ mum—L.“ m . m1) 4‘ .. "n... 7 ' H II V!) m m“ 123111318 1: __ m n im m 7 5'4 ‘ an " 1 my: III) 5 ‘5 3 .L . m n LL w m T ~7— mps SRST B ‘ , ) x271 F—lm m m m um “5:35;; , :(W' rm m,“ 5}" 5}" 53:7 ‘ I I I .% v T T T 7 an) m an m 5w: Send Feed back
ZCU106 Board User Guide 121
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
System Reset Pushbuttons
[Figure 2-1, callout 27]
Figure 3-47 shows the reset circuitry for the PS.
PS_POR_B Reset
Depressing and then releasing pushbutton SW4 causes net PS_POR_B to strobe Low. This
reset is used to hold the PS in reset until all PS power supplies are at the required voltage
levels. It must be held Low through PS power-up. PS_POR_B should be generated by the
power supply power-good signal. When the voltage at IN1 is below its threshold or EN1
(P.B. switch SW4 is pressed) goes Low, OUT1 (PS_POR_B) goes Low.
X-Ref Target - Figure 3-47
Figure 3-47: PS SRST_B and POR_B Pushbutton Switches SW3 and SW4
X16550-050117
(I XILINXa Send Feed back
ZCU106 Board User Guide 122
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
PS_SRST_B Reset
Depressing and then releasing pushbutton SW3 causes net PS_SRST_B to strobe Low. This
reset is used to force a system reset. It can be tied or pulled High, and can be High during
the PS supply power ramps. When the voltage at IN2 is below its threshold or EN2 (P.B.
switch SW3 is pressed) goes Low, OUT2 (PS_SRST_B) goes Low.
Active-Low reset output RST_B asserts when any of the monitored voltages (IN_) falls below
the respective threshold, any EN_ goes Low, or MR is asserted. RST_B remains asserted for
the reset time-out period after all of the monitored voltages exceed their respective
threshold, all EN_ are High, all OUT_ are High, and MR is deasserted. See the Zynq
UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for information on the
resets.
Board Power System
[Figure 2-1, callout 35]
The ZCU106 hosts a Maxim PMBus based power system. Each individual Maxim
MAX20751EKX, MAX15301, or MAX15303 voltage regulator has a PMBus interface.
Figure 3-48 shows the ZCU106 power system block diagram.
{I XILINXo 'agIGG Name: Page numbers reference file pages on scrematic 0881770 vccm “guano: I an I... a m man: I u Pan-63 menu. lmhtnx 0 mm natal VCCINTJKXI WI“! 0 31 Im 69 “RAVE Maul-tux I anon rag-a1 I‘M mm Imam: I 3; Iraq-7a mum water I nun ran-53 @flfi mun luau-to: I 21 rag-71 nn_nnm_vnnu Inn-latex - :- nag-u {L vcczn Winter I s; run-72 Isinnnivppizvs mnhtox I u Hg- 35 A; “mg-c III-Into: I 101 1341-73 mun mum: I n ”was IHH ll pL_nn_rrlIll_2rr5 nqunm I rag-74 mum ”mum: I soon ”I057 flfi VVVVVVVV nave: nguumx I u lag-75 mum“ Inuit" I anon Ila-Ba 4} Ianvn- llIIIllmr o a PIE-76 "1121113 "II-1m: I u nag-m max Inqulato! I n pin-77 urn)“ nan-to: I u "”90 rrccpsnn'u Inqulatol I urn run-75 wcvsxm-u nan-1am: I 11 9:41.79 nn._:rn ”qr-mar I no: mm ] “11.3110 “gunner I n p... 92 mum when I soon “you: $vfiva _ Ir:_nrrn_n'r llgulatnr I n _ m- 93 (vu:=nnn_)xlx_rnmn) ‘ pr._vn4_vn- llmllltox I n _ rag-93 (we: - vccavzr fifi fiflfi Send Feedback
ZCU106 Board User Guide 123
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
X-Ref Target - Figure 3-48
Figure 3-48: Power System Block Diagram
X19206-022218
(I XILINXa Send Feed back
ZCU106 Board User Guide 124
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 evaluation board uses power regulators and PMBus compliant POL controllers
from Maxim Integrated Circuits [Ref 22] to supply the core and auxiliary voltages listed in
Tab le 3- 53 . The schematic page references are to 0381770.
Table 3-53: Power System Devices
Device
Type
Ref.
Des.
PMBus
Addr. Description Power Rail Net
Name
Power Rail
Voltage
INA226
Address
Schem.
Page
MAX15301 U47 0x13 Maxim InTune digital
POL controller 20A VCCINT 0.85V PL:0x40 67
MAX15303 U7 0x14 Maxim InTune digital
POL controller 6A VCCBRAM 0.85V PL:0x41 68
MAX8556 U153 NA Maxim LDO
regulator 3A VCCINT_VCU 0.90V PL:0x4A 69
MAX15303 U6 0x15 Maxim InTune digital
POL controller 3A VCCAUX 1.80V PL:0x42 70
MAX15303 U10 0x16 Maxim InTune digital
POL controller 2A VCC1V2 1.20V PL:0x43 71
MAX15303 U9 0x17 Maxim InTune digital
POL controller 5A VCC3V3 3.30V PL:0x44 72
MAX15301 U63 0x18 Maxim InTune digital
POL controller 5A VADJ_FMC 1.80V PL:0x45 73
MAX15027 U38 NA Maxim LDO
regulator 1A PL_DDR4_VPP_2V5 2.5V NA 74
MAX20751 U95 0x72
Maxim multiphase
master with smart
slave VT77518 6A
MGTAVCC 0.90V PL:0x46 75
MAX20751 U96 0x73
Maxim multiphase
master with smart
slave VT77518 6A
MGTAVTT 1.20V PL:0x47 76
MAX8869E U14 NA Maxim LDO
regulator 1A MGTVCCAUX 1.81V NA 77
MAX15301 U46 0x0A Maxim InTune digital
POL controller 10A VCCPSINTFP 0.85V PS:0x40 78
MAX15303 U4 0x0B Maxim InTune digital
POL controller 2A VCCPSINTLP 0.85V PS:0x41 79
MAX8869E U3 NA Maxim LDO
regulator 500MA VCCPSAUX 1.81V PS:0x42 80
MAX8869E U17 NA Maxim LDO
regulator 200MA VCCPSPLL 1.20V PS:0x43 81
MAX8869E U5 NA Maxim LDO
regulator 400MA MGTRAVCC 0.85V PS:0x44 82
MAX8869E U12 NA Maxim LDO
regulator 100MA MGTRAVTT 1.81V PS:0x45 83
MAX15303 U18 0x1D Maxim InTune digital
POL controller 6A DDR4_DIMM_VDDQ 1.20V NA 84
(I XILINXa Send Feed back
ZCU106 Board User Guide 125
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
The FMC HPC0 (J5) and FMC HPC1 (J4) VADJ pins are wired to the programmable rail
VADJ_FMC_BUS. The VADJ_FMC_BUS rail is programmed to 1.80V by default. The valid
values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The VADJ_FMC derivative rail powers
the XCZU7EV HP banks 28, 67, and 68 (see Ta bl e 3 -2 , pag e 28). Documentation describing
PMBus programming for the Maxim InTune power controllers is available at the Maxim
website [Ref 22]. The PCB layout and power system design meets the recommended criteria
described in the UltraScale Architecture PCB Design User Guide (UG583) [Ref 4].
MAX15027 U39 NA Maxim LDO
regulator 1A PS_DDR4_VPP_2V5 2.50V NA 85
MAX15303 U13 0x10 Maxim InTune digital
POL controller 4A VCCOPS 1.80V PS:0x47 86
MAX8869E U31 NA Maxim LDO
regulator 300MA VCCOPS3 1.81V PS:0x4A 87
MAX8869E U30 NA Maxim LDO
regulator 100MA VCCPSDDRPLL 1.81V PS:0x4B 88
MAX8869E U143 NA Maxim LDO
regulator 1A UTIL_1V13 1.13V NA 89
MAX8869E U37 NA Maxim LDO
regulator 1A UTIL_1V8 1.80V NA 90
MAX15301 U49 0x1A Maxim InTune digital
POL controller 20A UTIL_3V3 3.30V NA 91
MAX15303 U8 0x1B Maxim InTune digital
POL controller 6A UTIL_5V0 5.00V NA 92
TPS15200 U36 NA
Memory Vtt
sink-source
regulator 3A
PS_DDR4_VTT 0.6V NA 93
TPS15200 U35 NA
Memory Vtt
sink-source
regulator 3A
PL_DDR4_VTT 0.6V NA 93
Table 3-53: Power System Devices (Cont’d)
Device
Type
Ref.
Des.
PMBus
Addr. Description Power Rail Net
Name
Power Rail
Voltage
INA226
Address
Schem.
Page
(I XILINXa Send Feed back
ZCU106 Board User Guide 126
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Chapter 3: Board Component Descriptions
Monitoring Voltage and Current
Voltage and current monitoring and control are available for the Maxim power system
controllers through the Maxim PowerTool graphical user interface. The on-board Maxim
InTune power controllers listed in Tabl e 3- 53 are accessed through the 2x8 keyed shrouded
PMBus connector J84, which is provided for use with the Maxim PowerTool USB cable
(Maxim part number MAXPOWERTOOL001#). This cable can be ordered from the Maxim
website [Ref 22]. The associated Maxim PowerTool GUI can be downloaded from the Maxim
website. This is the simplest and most convenient way to monitor the voltage and current
values for the Maxim PMBus programmed power rails listed in Tabl e 3- 53.
Each PMBus programmable Maxim controller can report the voltage and current of its
controlled rail to the Maxim GUI. A subset of the programmable rails and two fixed rails
have a TI INA226 PMBus power monitor circuit with connections to the rail series current
sense resistor. This arrangement permits the INA226 to report the sensed parameters
separately on the PMBus. The rails configured with the INA226 power monitors are shown
in Tab le 3-53 .
As described in I2C0 (MIO 14-15), page 60, the I2C0 bus provides access to the PMBus
power controllers and the PS-side and PL-side INA226 power monitors via the U60
PCA9544A bus switch. All PMBus controlled Maxim regulators are tied to the
MAXIM_PMBUS, while the INA226 power monitors are separated to PS_PMBUS and
PL_PMBUS.
Figure 3-17, page 61 and Table3-21, page63 document the I2C0 bus access path to the
Maxim PMBus controllers and INA226 power monitor op amps. Also, see schematic
0381770. The MPSoC core related power rail measurements (PL_PMBUS) and PS related
power measurements (PS_PMBUS) are accessible to the system controller and MPSoC PL
logic through their respective I2C0 bus connections.
These measurements are displayed in the system controller menu selections. The Maxim
controller PMBus is accessible by the system controller, which can also display the rail
voltage measurement made by its sourcing Maxim controller. User IP in the MPSoC PL can
access the same set of PMBus resident devices through the logic I2C0 connections.
(I X|L|NX. Send Feed back
ZCU106 Board User Guide 127
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix A
VITA 57.1 FMC Connector Pinouts
Overview
Figure A-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) J2
defined by the VITA 57.1 FMC specification. For a description of how the ZCU106 evaluation
board implements the FMC specification, see FPGA Mezzanine Card Interface, FMC HPC0
Connector J5, and FMC HPC1 Connector J4.
X-Ref Target - Figure A-1
Figure A-1: FMC HPC Connector Pinouts
X19207-050117
(I X|L|NX. Send Feed back
ZCU106 Board User Guide 128
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix B
Xilinx Constraints File
Overview
The Xilinx design constraints (XDC) file template for the ZCU106 board provides for designs
targeting the ZCU106 evaluation board. Net names in the constraints correlate with net
names on the latest ZCU106 evaluation board schematic. Identify the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User
Guide: Using Constraints (UG903) [Ref 10] for more information.
The FMC connectors J5 (HPC0) and J4 (HPC1) are connected to MPSoC banks powered by
the variable voltage VAJ_FMC. Because different FMC cards implement different circuitry, the
FMC bank I/O standards must be uniquely defined by each customer.
IMPORTANT: The XDC file can be accessed on the Zynq UltraScale+ ZCU106 Development Kit website.
(I X|L|NX.
ZCU106 Board User Guide 129
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix C
Regulatory and Compliance Information
Overview
This product is designed and tested to conform to the European Union directives and
standards described in this section.
ZCU106 Evaluation Kit — Master Answer Record
For Technical Support, open a Support Service Request.
CE Directives
2006/95/EC, Low Voltage Directive (LVD)
2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards
EN standards are maintained by the European Committee for Electrotechnical
Standardization (CENELEC). IEC standards are maintained by the International
Electrotechnical Commission (IEC).
Electromagnetic Compatibility
EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics –
Limits and Methods of Measurement
EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits and
Methods of Measurement
This is a Class A product. In a domestic environment, this product can cause radio
interference, in which case the user might be required to take adequate measures.
(I XILINXa
ZCU106 Board User Guide 130
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix C: Regulatory and Compliance Information
Safety
IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements
EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements
Markings
In August of 2005, the European Union (EU) implemented the EU
WEEE Directive 2002/96/EC and later the WEEE Recast Directive
2012/19/EU requiring Producers of electronic and electrical
equipment (EEE) to manage and finance the collection, reuse,
recycling and to appropriately treat WEEE that the Producer places on
the EU market after August 13, 2005. The goal of this directive is to
minimize the volume of electrical and electronic waste disposal and to
encourage re-use and recycling at the end of life.
Xilinx has met its national obligations to the EU WEEE Directive by
registering in those countries to which Xilinx is an importer. Xilinx has
also elected to join WEEE Compliance Schemes in some countries to
help manage customer returns at end-of-life.
If you have purchased Xilinx-branded electrical or electronic products
in the EU and are intending to discard these products at the end of
their useful life, please do not dispose of them with your other
household or municipal waste. Xilinx has labeled its branded
electronic products with the WEEE Symbol to alert our customers that
products bearing this label should not be disposed of in a landfill or
with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of
hazardous substances (RoHS) in electrical and electronic equipment.
This product complies with CE Directives 2006/95/EC, Low Voltage
Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC)
Directive.
(I X|L|NX.
ZCU106 Board User Guide 131
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix D
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
Documentation Navigator and Design Hubs
Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support
resources, which you can filter and search to find information. To open the Xilinx
Documentation Navigator (DocNav):
• From the Vivado® IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:
• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.
(I X|L|NXm Send Feed back
ZCU106 Board User Guide 132
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix D: Additional Resources and Legal Notices
References
The most up to date information related to the ZCU106 board and its documentation is
available on the ZCU106 Evaluation Kit website.
These Xilinx documents provide supplemental material useful with this guide:
1. Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891)
2. Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
3. Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
4. UltraScale Architecture PCB Design User Guide (UG583)
5. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
6. UltraScale Architecture GTH Transceivers User Guide (UG576)
7. UltraScale Architecture Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide
(PG156)
8. Silicon Labs CP210x USB-to-UART Installation Guide (UG1033)
9. Tera Term Terminal Emulator Installation Guide (UG1036)
10. Vivado Design Suite User Guide: Using Constraints (UG903)
11. UltraScale Architecture System Monitor User Guide (UG580)
12. ZCU106 System Controller GUI Tutorial (XTP495)
13. ZCU106 Software Install and Board Setup Tutorial (XTP497)
14. For additional documents associated with Xilinx devices, design tools, intellectual
property, boards, and kits see the Xilinx documentation website.
The following websites provide supplemental material useful with this guide:
15. Micron Technology: www.micron.com
(MT40A256M16GE-075E, MT25QU512ABB8ESF-0SIT, MTA4ATF51264HZ-2G6E1 data
sheets)
16. Standard Microsystems Corporation (SMSC): www.microchip.com
(USB3320 data sheet)
17. SanDisk Corporation: www.sandisk.com
18. SD Association: www.sdcard.org
19. Silicon Labs: www.silabs.com/Pages/default.aspx
(I X|L|NXm Send Feed back
ZCU106 Board User Guide 133
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix D: Additional Resources and Legal Notices
(SI5341B, Si570, Si5319C, Si53340, CP2108 data sheets)
20. Texas Instruments: www.ti.com/product/DP83867IR
(TI DP83867 data sheet)
21. PCI: https://pcisig.com/specifications
22. Maxim Integrated Circuits: https://www.maximintegrated.com
23. VITA FMC Marketing Alliance: www.vita.com/fmc
24. Digilent: www.digilentinc.com
(Pmod Peripheral Modules)
25. The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies
and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009.
Sourcegate only manufactures the latest revision, which is currently A4. To order, contact
Aries Ang, aries.ang@sourcegate.net, +65 6483 2878 for price and availability. This is a
custom cable and cannot be ordered from the Sourcegate website.
26. Future Technology Devices International Ltd.: http://www.ftdichip.com
(FT232HL)
Please Read: Important Legal Notices
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To t he
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect,
special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage
suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had
been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to
notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display
the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty,
please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to
warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be
fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products
in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF
AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY
DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY
TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY
AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.
© Copyright 2018-2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks
of PCI-SIG and used under license. The DisplayPort Icon is a trademark of the Video Electronics Standards Association, registered
(I XILINXa Send Feed back
ZCU106 Board User Guide 134
UG1244 (v1.4) October 23, 2019 www.xilinx.com
Appendix D: Additional Resources and Legal Notices
in the U.S. and other countries. CPRI is a trademark of Siemens AG. All other trademarks are the property of their respective
owners. Arm is a registered trademark of Arm in the EU and other countries. CPRI is a trademark of Siemens AG. All other
trademarks are the property of their respective owners.