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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

LM5575-Q1 75-V, 1.5-A Step-down Switching Regulator

1 Features

1• AEC-Q100-qualified for automotive applications:

– Device temperature grade 1: –40°C to +125°C

operating temperature

– Device temperature grade 0: –40°C to +150°C

operating temperature

– Device HBM ESD classification level 2

• Integrated 75-V, 330-mΩN-channel MOSFET

• Ultra-wide input-voltage from 6 V to 75 V

• Adjustable output voltage as low as 1.225 V

• 1.65% Feedback reference accuracy

• Operating frequency adjustable between 50 kHz

and 500 kHz with single resistor

• Master or slave frequency synchronization

• Adjustable soft start

• Emulated current-mode-control architecture

• Wide bandwidth error amplifier

• Built-in protection

• Create a custom design using the LM5575-Q1

with the WEBENCH®Power Designer

2 Applications

• Automotive

• Industrial

3 Description

The LM5575-Q1 is an easy-to-use buck regulator that

allows design engineers to design and optimize a

robust power supply using a minimum set of

components. Operating with an input voltage range of

6 V to 75 V, the LM5575-Q1 delivers 1.5 A of

continuous output current with an integrated 330-mΩ

N-channel MOSFET. The regulator utilizes an

emulated current mode architecture which provides

inherent line regulation, tight load-transient response,

and ease-of-loop compensation without the usual

limitation of low-duty cycles associated with current

mode regulators. The operating frequency is

adjustable from 50 kHz to 500 kHz to allow

optimization of size and efficiency. The LM5575-Q1

ensures robustness with cycle-by-cycle current limit,

short-circuit protection, thermal shutdown, and

remote shutdown. The device is available in a power

enhanced 16-pin HTSSOP package featuring an

exposed die attach pad for thermal dissipation. The

LM5575-Q1 is supported by the full suite of

WEBENCH®on-Line design tools. For AEC-Q100

grade 1 and grade 0 orderable numbers, see the

orderable addendum at the end of this data sheet.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM5575-Q1 HTSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

l TEXAS INSTRUMENTS

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

7 Detailed Description.............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram......................................... 9

7.3 Feature Description................................................... 9

7.4 Device Functional Modes........................................ 10

8 Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application ................................................. 17

9 Power Supply Recommendations...................... 23

10 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 23

10.2 Layout Examples................................................... 24

10.3 Thermal Considerations........................................ 25

11 Device and Documentation Support ................. 25

11.1 Device Support .................................................... 25

11.2 Receiving Notification of Documentation Updates 25

11.3 Community Resources.......................................... 25

11.4 Trademarks........................................................... 25

11.5 Electrostatic Discharge Caution............................ 26

11.6 Glossary................................................................ 26

12 Mechanical, Packaging, and Orderable

Information ........................................................... 26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (February 2019) to Revision F Page

• Added Grade 0 information to Features ................................................................................................................................ 1

• Added Grade 1 and Grade 0 sentence to end of Description ............................................................................................... 1

Changes from Revision D (March 2018) to Revision E Page

• Removed references to the LM2xxx devices from the data sheet ........................................................................................ 1

• Changed "760" mΩto "800 mΩ" in buck switch Rds(on) over full operating junction temperature row ................................ 6

• Changed forced off-time maximum value from: 590 ns to: 626 ns in full operating junction temperature range................... 6

Changes from Revision C (December 2014) to Revision D Page

• Added links for WEBENCH; minor editorial updates for SEO improvement.......................................................................... 1

• Changed RθJA from "50°C/W" to "38.4°C/W" ......................................................................................................................... 5

• Changed RθJC(top) from "14°C/W" to "21.8°C/W"; add additional thermal values ................................................................... 5

• Corrected unit for RL to "kΩ".................................................................................................................................................. 8

Changes from Revision B (April 2013) to Revision C Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Semiconductor data sheet to TI format.................................................................................... 25

l TEXAS INSTRUMENTS

VIN

PRE

VCC

AGND

OUT

RAMP 9

COMP

BST

PGND

SYNC

LM5575-Q1

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5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP With Exposed Thermal Pad

Top View

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION

NO. NAME

1 VCC O Output of the bias regulator VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 V. A 0.1-µF to

1-µF ceramic decoupling capacitor is required. An external voltage (7.5 V –

14 V) can be applied to this pin to reduce internal power dissipation.

2 SD I Shutdown or UVLO input

If the SD pin voltage is lower than 0.7 V, the regulator is in a low power

state. If the SD pin voltage is between 0.7 V and 1.225 V the regulator is in

standby mode. If the SD pin voltage is higher than 1.225 V, the regulator is

operational. An external voltage divider can be used to set a line

undervoltage shutdown threshold. If the SD pin is left open circuit, a 5-µA

pullup current source configures the regulator fully operational.

3 VIN I Input supply voltage Nominal operating range: 6 V to 75 V.

4 SYNC I Oscillator synchronization input

or output

The internal oscillator can be synchronized to an external clock with an

external pulldown device. Multiple LM5575-Q1 devices can be synchronized

together by connection of their SYNC pins.

5 COMP O Output of the internal error

amplifier The loop compensation network must be connected between this pin and

the FB pin.

6 FB I Feedback signal from the

regulated output This pin is connected to the inverting input of the internal error amplifier. The

regulation threshold is 1.225 V.

7 RT I Internal oscillator frequency set

input The internal oscillator is set with a single resistor connected between this pin

and the AGND pin.

8 RAMP O Ramp control signal An external capacitor connected between this pin and the AGND pin sets the

ramp slope used for current mode control. Recommended capacitor range

50 pF to 2000 pF.

9 AGND GND Analog ground Internal reference for the regulator control functions

10 SS O Soft start An external capacitor and an internal 10-µA current source set the time

constant for the rise of the error amp reference. The SS pin is held low

during standby, VCC UVLO, and thermal shutdown.

11 OUT O Output voltage connection Connect directly to the regulated output voltage.

12 PGND GND Power ground Low-side reference for the PRE switch and the IS sense resistor.

13 IS I Current sense

Current measurement connection for the re-circulating diode. An internal

sense resistor and a sample and hold circuit sense the diode current near

the conclusion of the off-time. This current measurement provides the DC

level of the emulated current ramp.

14 SW O Switching node The source terminal of the internal buck switch. Connect the SW pin to the

external Schottky diode and to the buck inductor.

l TEXAS INSTRUMENTS

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Pin Functions (continued)

PIN I/O DESCRIPTION APPLICATION INFORMATION

NO. NAME

15 PRE O Pre-charge assist for the

bootstrap capacitor

This open-drain output can be connected to SW pin to help charging the

bootstrap capacitor during very light load conditions or in applications where

the output may be pre-charged before the LM5575-Q1 is enabled. An

internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to

the on-time interval of the buck switch.

16 BST I Boost input for bootstrap

capacitor

An external capacitor is required between the BST and the SW pins. TI

recommends a 0.022-µF ceramic capacitor. The capacitor is charged from

VCC through an internal diode during the off-time of the buck switch.

NA EP -- Exposed Pad Exposed metal pad on the underside of the device. TI recommends to

connect this pad to the PWB ground plane to help with heat dissipation.

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are

conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the

Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2).

MIN MAX UNIT

VIN to GND 76 V

BST to GND 90 V

PRE to GND 76 V

SW to GND (steady-state) −1.5 V

BST to VCC 76 V

SD, VCC to GND 14 V

BST to SW 14 V

OUT to GND Limited to VIN

SYNC, SS, FB, RAMP to GND 7 V

Storage temperature, Tstg –65 150 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are

conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the

Electrical Characteristics.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN 6 75 V

Operation junction temperature −40 150 °C

l TEXAS INSTRUMENTS

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

LM5575-Q1

UNITPWP (HTSSOP)

16 PINS

RθJA Junction-to-ambient thermal resistance 38.4 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 21.8 °C/W

RθJB Junction-to-board thermal resistance 15.6 °C/W

ψJT Junction-to-top characterization parameter 0.5 °C/W

ψJB Junction-to-board characterization parameter 16.4 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.5 Electrical Characteristics

Specifications are for TJ= 25°C. VIN = 48 V, RT= 32.4 kΩunless otherwise stated. (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

START-UP REGULATOR

VccReg VCC regulator output

7.15 V

Over full operating junction

temperature range 6.85 7.5

VCC LDO mode turnoff 9 V

VCC current limit VCC = 0 V 25 mA

VCC SUPPLY

VCC UVLO threshold

(VCC increasing) 5.35 V

Over full operating junction

temperature range 5.01 5.69

VCC undervoltage hysteresis 0.35 V

Bias current (Iin)

FB = 1.3 V 3.7 mA

Over full operating junction

temperature range 4.5

Shutdown current (Iin)

SD = 0 V 57 µA

Over full operating junction

temperature range 85

SHUTDOWN THRESHOLDS

Shutdown threshold

(SD Increasing) 0.7 V

Over full operating junction

temperature range 0.43 0.9

Shutdown hysteresis 0.1 V

Standby threshold

(Standby Increasing) 1.225 V

Over full operating junction

temperature range 1.15 1.30

Standby hysteresis 0.1 V

SD pullup current source 5 µA

l TEXAS INSTRUMENTS

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Electrical Characteristics (continued)

Specifications are for TJ= 25°C. VIN = 48 V, RT= 32.4 kΩunless otherwise stated. (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWITCH CHARACTERISTICS

Buck switch Rds(on)

330 mΩ

Over full operating junction

temperature range 800

BOOST UVLO 4 V

BOOST UVLO hysteresis 0.56 V

Pre-charge switch Rds(on) 70 Ω

Pre-charge switch on-time 250 ns

CURRENT LIMIT

Cycle by cycle current limit

RAMP = 0 V 2.1 A

Over full operating junction

temperature range 1.8 2.7

Cycle by cycle current limit delay RAMP = 2.5 V 85 ns

SOFT START

SS current source

10 µA

Over full operating junction

temperature range 7 14

OSCILLATOR

Frequency1

200 kHz

Over full operating junction

temperature range 180 220

Frequency2

RT= 11 kΩ485 kHz

Over full operating junction

temperature range 425 545

SYNC source impedance 11 kΩ

SYNC sink impedance 110 Ω

SYNC threshold (falling) 1.3 V

SYNC frequency

RT= 11 kΩkHz

Over full operating junction

temperature range 550

SYNC pulse width minimum Over full operating junction

temperature range 15 ns

RAMP GENERATOR

Ramp current 1

VIN = 60 V, VOUT=10 V 550 µA

Over full operating junction

temperature range 467 633

Ramp current 2

VIN = 10 V, VOUT= 10 V 50 µA

Over full operating junction

temperature range 36 64

PWM COMPARATOR

Forced off-time

500 ns

Over full operating junction

temperature range 390 626

Minimum on-time 80 ns

COMP to PWM comparator offset 0.7 V

l TEXAS INSTRUMENTS loan NORMALIZED OSC‘LATOR FREQUENCY 1 004 1 003 1 002 1001 1 000 0 999 0 99B 0 997 0 996 750 725 0 25 50 75 100125150 TEMPERATURE (“0)

RT (k:)

OSCILLATOR FREQUENCY (kHz)

1 10 100 1000

100

1000

LM5575-Q1

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Electrical Characteristics (continued)

Specifications are for TJ= 25°C. VIN = 48 V, RT= 32.4 kΩunless otherwise stated. (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER

Feedback voltage

VFB = COMP 1.225 V

Over full operating junction

temperature range 1.205 1.245

FB bias current 17 nA

DC gain 70 dB

COMP sink / source current Over full operating junction

temperature range 2.5 mA

Unity gain bandwidth 3 MHz

DIODE SENSE RESISTANCE

DSENSE 83 mΩ

THERMAL SHUTDOWN

TSD Thermal shutdown threshold 180 °C

Thermal shutdown hysteresis 25 °C

6.6 Typical Characteristics

Figure 1. Oscillator Frequency vs RTFigure 2. Oscillator Frequency vs Temperature

FOSC = 200 kHz

*9 TEXAS INSTRUMENTS ‘cc 4 3 2 9 a 0 0 D 0 0 9 9 9 1 1 1 1 1 0 0 u 1 u 7 hzmmmzo F35 EOw ENZ<§koz 6="" 9="" 0="" -50="" -25="" u="" 25="" 50="" 75="" 100125150="" temperature="" (°c)="" w="" mo="" ‘out="">

0.25 0.5 1 1.250.75 1.5

100

EFFICIENCY (%)

IOUT (A)

VIN = 24V

VIN = 48V

VIN = 75V

VIN = 7V

PHASE (°)

10k 100k 1M 10M 100M

FREQUENCY (Hz)

-30

-20

-10

GAIN (dB)

-135

-90

-45

135

180

225

GAIN

PHASE

0 2 4 6 8 10

VCC (V)

VIN (V)

Ramp Up

Ramp Down

04 16 20 24

ICC (mA)

VCC (V)

812

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

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Product Folder Links: LM5575-Q1

Typical Characteristics (continued)

Figure 3. Soft-Start Current vs Temperature Figure 4. VCC vs ICC VIN = 12 V

Figure 5. VCC vs VIN RL= 7 kΩFigure 6. Error Amplifier Gain / Phase AVCL = 101

Figure 7. Demoboard Efficiency vs IOUT and VIN

VIN

BST

AGND

CLK

PRE

4 7 811

LM5575

SHUTDOWN

STANDBY

REGULATOR

SYNC

OSCILLATOR

RAMP OUT

PGND

CLK

COMP

ERROR

AMP

21k

470p

C11

330p

C10

120

1.65k

5.11k

47 PH

0.022

0.47

CMSH3-100

THERMAL

SHUTDOWN

UVLO

CLK

DIS

VCC

LEVEL

SHIFT

DRIVER

1.225V

0.7V

49.9k

0.01

open

OPEN

C12

OPEN

0.01

1.0

OPEN

7V ± 75V VIN

VIN

2.1V

PWM

C_LIMIT

10 PA

5 PA

VIN

TRACK

SAMPLE

and

HOLD

1V/A

RAMP GENERATOR

Ir = (10 PA x (VIN ± VOUT))

+ 50 PA

LM5575-Q1

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SNOSB23F –OCTOBER 2008–REVISED JULY 2019

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7 Detailed Description

7.1 Overview

The LM5575-Q1 switching regulator features the functions necessary to implement an efficient high-voltage buck

regulator using a minimum of external components. This easy-to-use regulator integrates a 75-V N-Channel buck

switch with an output current capability of 1.5 amps. The regulator control method is based on current mode

control using an emulated current ramp. Peak current mode control provides inherent line voltage feed-forward,

cycle-by-cycle current limiting, and ease-of-loop compensation. The use of an emulated control ramp reduces

noise sensitivity of the pulse-width modulation circuit, which allows reliable processing of very small duty cycles

necessary in high-input voltage applications. The operating frequency is user programmable from 50 kHz to 500

kHz. An oscillator synchronization pin allows multiple LM5575-Q1 regulators to self-synchronize or be

synchronized to an external clock. The output voltage can be set as low as 1.225 V. Fault protection features

include, current limiting, thermal shutdown, and remote shutdown capability. The device is available in the 16-pin

HTSSOP package that features an exposed pad to help thermal dissipation.

7.2 Functional Block Diagram

The LM5575-Q1 device can be applied in numerous applications to efficiently step down a high, unregulated

input voltage. The device is designed for telecom, industrial, and automotive power bus voltage ranges.

7.3 Feature Description

7.3.1 Shutdown and Standby

The LM5575-Q1 contains a dual-level shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the

regulator is in a low-current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225

V, the regulator is in standby mode. In standby mode, the VCC regulator is active but the output switch is

disabled. When the SD pin voltage exceeds 1.225 V, the output switch is enabled and normal operation begins.

An internal 5-µA pullup current source configures the regulator to be fully operational if the SD pin is left open.

l TEXAS INSTRUMENTS

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Feature Description (continued)

An external set-point voltage divider from VIN to GND can be used to set the operational input range of the

regulator. The divider must be designed such that the voltage at the SD pin is greater than 1.225 V when VIN is

in the desired operating range. The internal 5-µA pullup current source must be included in calculations of the

external set-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The SD

pin is internally clamped with a 1-kΩresistor and an 8-V Zener clamp. The voltage at the SD pin should never

exceed 14 V. If the voltage at the SD pin exceeds 8 V, the bias current increase at a rate of 1 mA/V.

The SD pin can also be used to implement various remote enable and disable functions. Pulling the SD pin

below the 0.7-V threshold totally disables the controller. If the SD pin voltage is higher than 1.225 V, the regulator

is operational.

7.3.2 Current Limit

The LM5575-Q1 contains a unique current monitoring scheme for control and overcurrent protection. When set

correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current

with a scale factor of 1 V/A. The emulated ramp signal is applied to the current limit comparator. If the emulated

ramp signal exceeds 2.1 V (2.1 A), the present current cycle is terminated (cycle-by-cycle current limiting). In

applications with small output inductance and high-input voltage, the switch current may overshoot due to the

propagation delay of the current limit comparator. If an overshoot should occur, the diode current sampling circuit

will detect the excess inductor current during the off-time of the buck switch. If the sample and hold DC level

exceeds the 2.1-V current limit threshold, the buck switch will be disabled and skip pulses until the diode current

sampling circuit detects the inductor current has decayed below the current limit threshold. This approach

prevents current runaway conditions due to propagation delays or inductor saturation because the inductor

current is forced to decay following the current overshoot.

7.3.3 Soft Start

The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing

start-up stresses and surges. The internal soft-start current source, set to 10 µA, gradually increases the voltage

of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the

reference input of the error amplifier. Various sequencing and tracking schemes can be implemented using

external circuits that limit or clamp the voltage level of the SS pin.

In the event a fault is detected (overtemperature, Vcc UVLO, SD) the soft-start capacitor will be discharged.

When the fault condition is no longer present, a new soft-start sequence will commence.

7.3.4 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature is exceeded. When activated (typically at 180°C), the controller is forced into a low-power reset

state, which disables the output driver and the bias regulator. This feature is provided to prevent catastrophic

failures from accidental device overheating.

7.4 Device Functional Modes

7.4.1 High-Voltage Start-Up Regulator

The LM5575-Q1 contains a dual-mode internal high-voltage start-up regulator that provides the VCC bias supply

for the PWM controller and bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to the

input voltage, as high as 75 V. For input voltages lower than 9 V, a low dropout switch connects VCC directly to

VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltage greater than 9 V, the low-dropout

switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating

range of 6 V to 75 V is achieved through the use of this dual-mode regulator.

The output of the VCC regulator is current-limited to 25 mA. Upon power up, the regulator sources current into the

capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 5.35

V and the SD pin is greater than 1.225 V, the output switch is enabled and a soft-start sequence begins. The

output switch remains enabled until VCC falls below 5 V or the SD pin falls below 1.125 V.

l TEXAS INSTRUMENTS

RT =

- 580 x 10-9

135 x 10-12

VIN

VCC

Internal Enable Signal

5.25V

LM5575-Q1

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Device Functional Modes (continued)

An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary

voltage is greater than 7.3 V, the internal regulator essentially shuts off, reducing the IC power dissipation. The

VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased in

normal operation. Therefore the auxiliary VCC voltage should never exceed the VIN voltage.

In high-voltage applications, take care to ensure the VIN pin does not exceed the absolute maximum voltage

rating of 76 V. During line or load transients, voltage ringing on the VIN line that exceeds the absolute maximum

ratings can damage the IC. Both careful printed-circuit board layout and the use of quality bypass capacitors

located close to the VIN and GND pins are essential.

Figure 8. VIN and VCC Sequencing

7.4.2 Oscillator and Sync Capability

The LM5575-Q1 oscillator frequency is set by a single external resistor connected between the RT pin and the

AGND pin. Place the RTresistor very close to the device and connected directly to the pins of the IC (RT and

AGND). To set a desired oscillator frequency (F), the necessary value for the RTresistor can be calculated by

Equation 1:

(1)

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be

of higher frequency than the free-running frequency set by the RTresistor. A clock circuit with an open-drain

output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration must be

greater than 15 ns.

DDDDD

SYNC

10k

DEADTIME

ONE-SHOT

2.5V

I = f(RT)

SYNC

LM5575

UP TO 5 TOTAL

DEVICES

LM5575

SYNC

AGND

LM5575

CLK

SYNC

500 ns

LM5575-Q1

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Device Functional Modes (continued)

Figure 9. Sync From External Clock Figure 10. Sync From Multiple Devices

Multiple LM5575-Q1 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration, all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11

shows the SYNC input and output features of the LM5575-Q1. The internal oscillator circuit drives the SYNC pin

with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low either by the internal oscillator

or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the

SYNC pins of several LM5575-Q1 ICs are connected together, the IC with the highest internal clock frequency

pulls the connected SYNC pins low first and terminate the oscillator ramp cycles of the other ICs. The LM5575-

Q1 with the highest programmed clock frequency will serve as the master and control the switching frequency of

the all the devices with lower oscillator frequency.

Figure 11. Simplified Oscillator Block Diagram and Sync I/O Circuit

7.4.3 Error Amplifier and PWM Comparator

The internal high-gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is

connected to the COMP pin, which allows the user to provide loop compensation components, generally a type II

network, as shown in Functional Block Diagram. This network creates a pole at DC, a zero and a noise-reducing,

high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP

generator to the error amplifier output voltage at the COMP pin.

l TEXAS INSTRUMENTS

Sample and

Hold DC Level

1V/A

RAMP

TON

tON

CRAMP

(10 P x (VIN ± VOUT) + 50 P) x

LM5575-Q1

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Device Functional Modes (continued)

7.4.4 Ramp Generator

The ramp signal used in the pulse-width modulator for current-mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.

Using this signal for the PWM ramp simplifies the control-loop-transfer function to a single pole response and

provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.

Also, the current measurement may introduce significant propagation delays. The filtering, blanking time, and

propagation delay limit the minimum achievable pulse width. In applications where the input voltage may be

relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary

for regulation. The LM5575-Q1 uses a unique ramp generator, which does not actually measure the buck switch

current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp

signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The

current reconstruction is comprised of two elements; a sample and hold DC level and an emulated current ramp.

Figure 12. Composition of Current Sense Signal

The sample and hold DC level shown in Figure 12 is derived from a measurement of the re-circulating Schottky

diode anode current. The re-circulating diode anode should be connected to the IS pin. The diode current flows

through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense

resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode

current sensing and sample and hold provide the DC level of the reconstructed current signal. The positive slope

inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an

internal voltage controlled current source. The ramp current source that emulates the inductor current is a

function of the VIN and VOUT voltages per Equation 2:

IRAMP = (10 µA × (VIN – VOUT)) + 50 µA (2)

Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of

CRAMP can be selected from Equation 3:

CRAMP = L × 10–5

where

• L is the value of the output inductor in Henrys (3)

l TEXAS INSTRUMENTS

RAMP

VCC

CRAMP

RRAMP

LM5575-Q1

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Product Folder Links: LM5575-Q1

Device Functional Modes (continued)

With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC

level sample and hold (1 V/A). Locate the CRAMP capacitor very close to the device and connect directly to the

pins of the IC (RAMP and AGND).

For duty cycles greater than 50%, peak-current-mode control circuits are subject to sub-harmonic oscillation.

Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch

node. Add a fixed slope voltage ramp (slope compensation) to the current sense signal to prevent this oscillation.

The 50 µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal.

In some high-output voltage, high duty cycle applications, additional slope may be required. In these applications,

a pullup resistor may be added between the VCC and RAMP pins to increase the ramp slope compensation.

For VOUT > 7.5 V:

Calculate optimal slope current, IOS = VOUT × 10 µA/V.

For example, at VOUT = 10 V, IOS = 100 µA.

Install a resistor from the RAMP pin to VCC:

RRAMP = VCC / (IOS – 50 µA) (4)

Figure 13. RRAMP to VCC for VOUT > 7.5 V

7.4.5 BOOST Pin

The LM5575-Q1 integrates an N-Channel buck switch and associated floating high-voltage level shift and gate

driver. This gate-driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. TI

recommends a 0.022-µF ceramic capacitor, connected with short traces between the BST pin and SW pin.

During the off-time of the buck switch, the SW pin voltage is approximately –0.5 V, and the bootstrap capacitor is

charged from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck

switch is forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged.

Under very light-load conditions or when the output voltage is pre-charged, the SW voltage does not remain low

during the off-time of the buck switch. If the inductor current falls to zero and the SW pin rises, the bootstrap

capacitor does not receive sufficient voltage to operate the buck switch gate driver. For these applications, the

PRE pin can be connected to the SW pin to pre-charge the bootstrap capacitor. The internal pre-charge

MOSFET and diode connected between the PRE pin and PGND turns on each cycle for 250 ns just prior to the

onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode

(CCM)), then no current flows through the pre-charge MOSFET/diode.

TEXAS INSTRUMENTS

VinMIN = Vout + VD

1 - Fs x 500 ns

LM5575-Q1

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Device Functional Modes (continued)

7.4.6 Maximum Duty Cycle and Input Dropout Voltage

There is a forced off-time of 500 ns implemented each cycle to ensure sufficient time for the diode current to be

sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle varies

with the operating frequency.

DMAX = 1 – Fs × 500 ns

where

• Fs is the oscillator frequency. (5)

Limiting the maximum duty cycle will raise the input dropout voltage. The input dropout voltage is the lowest input

voltage required to maintain regulation of the output voltage. Equation 6 calculates an approximation of the input

dropout voltage.

where

• VDis the voltage drop across the re-circulatory diode. (6)

Operating at high switching frequency raises the minimum input voltage necessary to maintain regulation.

‘5‘ TEXAS INSTRUMENTS |\

BST

VCC

GND

LM5575

COUT

VOUT

BST

VCC

GND

LM5575

VOUT

COUT

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

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Product Folder Links: LM5575-Q1

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Bias Power Dissipation Reduction

Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of

the IC. The VCC regulator must step down the input voltage VIN to a nominal VCC level of 7 V. The large voltage

drop across the VCC regulator translates into a large power dissipation within the VCC regulator. There are several

techniques that can significantly reduce this bias regulator power dissipation. Figure 14 and Figure 15 depict two

methods to bias the IC from the output voltage. In each case, the internal VCC regulator is used to initially bias

the VCC pin. After the output voltage is established, the VCC pin potential is raised higher than the nominal 7-V

regulation level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin should

never exceed 14 V. The VCC voltage should never be larger than the VIN voltage.

Figure 14. VCC Bias From VOUT for 8 V < VOUT < 14 V

Figure 15. VCC Bias With Additional Winding on the Output Inductor

l TEXAS INSTRUMENTS %? i: 35‘: i i ﬁTJTm {H FL- <11>

VIN

BST

AGND

CLK

PRE

4 7 811

LM5575

SHUTDOWN

STANDBY

REGULATOR

SYNC

OSCILLATOR

RAMP OUT

PGND

CLK

COMP

ERROR

AMP

21k

470p

C11

330p

C10

120

1.65k

5.11k

47 PH

0.022

0.47

CMSH3-100

THERMAL

SHUTDOWN

UVLO

CLK

DIS

VCC

LEVEL

SHIFT

DRIVER

1.225V

0.7V

49.9k

0.01

open

OPEN

C12

OPEN

0.01

1.0

OPEN

7V ± 75V VIN

VIN

2.1V

PWM

C_LIMIT

10 PA

5 PA

VIN

TRACK

SAMPLE

and

HOLD

1V/A

RAMP GENERATOR

Ir = (10 PA x (VIN ± VOUT))

+ 50 PA

LM5575-Q1

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8.2 Typical Application

Figure 16. Typical Application Circuit

8.2.1 Design Requirements

The circuit shown in Functional Block Diagram is configured for the following specifications:

• VOUT =5V

• VIN =7Vto75V

• Fs = 300 kHz

• Minimum load current (for CCM) = 200 mA

• Maximum load current = 1.5 A

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5575-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these steps are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

l TEXAS INSTRUMENTS Kinsgﬁ

L1 = 5V x (75V ± 5V)

0.4A x 300 kHz x 75V = 39 PH

L1 = VOUT x (VIN(max) ± VOUT)

IRIPPLE x FS x VIN(max)

IPK+

L1 Current

0 mA

IPK-

IRIPPLE

1/Fs

RT = [(1 / 300 x 103) ± 580 x 10-9]

135 x 10-12

LM5575-Q1

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Typical Application (continued)

8.2.2.2 External Components

The procedure for calculating the external components is illustrated with the following design example.

8.2.2.3 R3 (RT)

RTsets the oscillator switching frequency. Generally, higher-frequency applications are smaller but have higher

losses. Operation at 300 kHz was selected for this example as a reasonable compromise for both small size and

high efficiency. The value of RTfor 300-kHz switching frequency can be calculated as Equation 7.

(7)

The nearest standard value of 21 kΩwas chosen for RT.

8.2.2.4 L1

The inductor value is determined based on the operating frequency, load current, ripple current, and the

minimum and maximum input voltage (VIN(min), VIN(max)).

Figure 17. Inductor Current Waveform

To keep the circuit in CCM, the maximum ripple current IRIPPLE must be less than twice the minimum load

current, or 0.4 Ap-p. Using this value of ripple current, the value of inductor (L1) is calculated using Equation 8

and Equation 9:

(8)

(9)

This procedure provides a guide to select the value of L1. The nearest standard value (47 µH) is used. L1 must

be rated for the peak current (IPK+) to prevent saturation. During normal loading conditions, the peak current

occurs at maximum load current plus maximum ripple. During an overload condition, the peak current is limited to

2.1 A nominal (2.5 A maximum). The selected inductor has a conservative 3.25-Amp saturation current rating.

The saturation rating is defined by inductor manufacturers as the current necessary for the inductance to reduce

by 30%, at 20°C.

8.2.2.5 C3 (CRAMP)

With the inductor value selected, Equation 10 calculates the value of C3 (CRAMP) necessary for the emulation

ramp circuit:

CRAMP = L × 10–5

where

• L is in Henrys. (10)

With L1 selected for 47 µH, the recommended value for C3 is 470 pF.

l TEXAS INSTRUMENTS

'VOUT = 'IL x 1

8 x FS x COUT

©ESR +

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Typical Application (continued)

8.2.2.6 C9, C10

The output capacitors, C9 and C10, smooth the inductor ripple current and provide a source of charge for

transient loading conditions. For this design a 10-µF ceramic capacitor and a 120-µF AL organic capacitor were

selected. The ceramic capacitor provides ultra-low ESR to reduce the output ripple voltage and noise spikes,

while the AL capacitor provides a large bulk capacitance in a small volume for transient loading conditions.

Equation 11 calculates an approximation for the output ripple voltage.

(11)

8.2.2.7 D1

A Schottky type re-circulating diode is required for all LM5575-Q1 applications. Ultra-fast diodes are not

recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal

reverse recovery characteristics and low forward-voltage drop are particularly important diode characteristics for

high-input voltage and low-output voltage applications common to the LM5575-Q1. The reverse recovery

characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The

reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch

occurring during turnon each cycle. The resulting switching losses of the buck switch are significantly reduced

when using a Schottky diode. Select the reverse breakdown rating for the maximum VIN, plus some safety

margin.

The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a

low output voltage. Rated current for diodes vary widely from various manufacturers. The worst case is to

assume a short-circuit load condition. In this case the diode carries the output current almost continuously. For

the LM5575-Q1 this current can be as high as 2.1 A. Assuming a worst-case, 1-V drop across the diode, the

maximum diode power dissipation can be as high as 2.1 W. For the reference design a 100-V Schottky in a SMC

package was selected.

8.2.2.8 C1, C2

The regulator supply voltage has a large source impedance at the switching frequency. Good-quality input

capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the

inductor current waveform, ramps up to the peak value, then drops to zero at turnoff. The average current into

VIN during the on-time is the load current. Select the input capacitance for RMS current rating and minimum

ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.

Select quality ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage

effects, two 1-µF, 100-V ceramic capacitors are used. If step input voltage transients are expected near the

maximum rating of the LM5575-Q1, a careful evaluation of ringing and possible spikes at the device VIN pin

must be completed. An additional damping network or input voltage clamp may be required in these cases.

8.2.2.9 C8

The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value

of C8 is no smaller than 0.1 µF and should be a good-quality, low-ESR, ceramic capacitor. A value of 0.47 µF

was selected for this design.

8.2.2.10 C7

The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch

gate at turnon. The recommended value of C7 is 0.022 µF and should be a good-quality, low-ESR, ceramic

capacitor.

l TEXAS INSTRUMENTS

R2 = 1.225 x R1

VIN(min) + (5 x 10-6 x R1) ± 1.225

tss = C4 x 1.225V

10 PA

LM5575-Q1

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Product Folder Links: LM5575-Q1

Typical Application (continued)

8.2.2.11 C4

The capacitor at the SS pin determines the soft-start time; that is, the time for the reference voltage and the

output voltage, to reach the final regulated value. Equation 12 determines the time.

(12)

For this application, a C4 value of 0.01 µF was chosen which corresponds to a soft-start time of 1 ms.

8.2.2.12 R5, R6

R5 and R6 set the output voltage level. The ratio of these resistors is calculated from Equation 13:

R5/R6 = (VOUT / 1.225V) – 1 (13)

For a 5-V output, the R5/R6 ratio calculates to 3.082. Choose the resistors from standard value resistors. A good

starting point is selection in the range of 1 kΩto 10 kΩ. Values of 5.11 kΩfor R5,and 1.65 kΩfor R6, were

selected.

8.2.2.13 R1, R2, C12

A voltage divider can be connected to the SD pin to set a minimum operating voltage VIN(min) for the regulator. If

this feature is required, the easiest approach to select the divider resistor values is to select a value for R1

(between 10 kΩand 100 kΩrecommended) then calculate R2 from Equation 14:

(14)

Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8 V. When using

an external set-point divider, it may be necessary to clamp the SD pin at high input-voltage conditions. The

reference design uses the full range of the LM5575-Q1 (6 V to 75 V); therefore, these components can be

omitted. With the SD pin open circuit the LM5575-Q1 responds once the VCC UVLO threshold is satisfied.

8.2.2.14 R7, C11

A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing

and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the

rating of the LM5575-Q1 or the re-circulating diode can damage these devices. TI recommends to select the

values for the snubber through empirical methods. First, make sure the lead lengths for the snubber connections

are very short. For the current levels typical for the LM5575-Q1, a resistor value between 5 and 20 Ωis

adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a

minimum value of C11 that provides adequate damping of the SW pin waveform at high load.

8.2.2.15 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One

advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.

The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of

the LM5575-Q1 is calculated by Equation 15:

DC Gain(MOD) = Gm(MOD) × RLOAD = 1 × RLOAD (15)

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output

capacitance (COUT). The corner frequency of this pole is calculated by Equation 16:

fp(MOD) = 1 / (2πRLOAD COUT) (16)

For RLOAD = 5 Ωand COUT = 130 µF then fp(MOD) = 245 Hz

DC Gain(MOD) = 1 × 5 = 14 dB

For the design example of Functional Block Diagram, the measured modulator gain vs. frequency characteristic

is shown in Figure 18.

l TEXAS INSTRUMENTS

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz

10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

100k

LM5575-Q1

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Product Folder Links: LM5575-Q1

Typical Application (continued)

RLOAD = 5 ΩCOUT = 130 µF

Figure 18. Gain and Phase of Modulator

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a

zero at fZ=1/(2πR4C5). The error amplifier zero cancels the modulator pole and leaves a single pole response

at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very

stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. Select the

compensation network zero (fZ) at least an order of magnitude less than the target crossover frequency. This

constrains the product of R4 and C5 for a desired compensation network zero 1 / (2πR4 C5) to be less than 2

kHz. If the user increases R4 while they proportionally decrease C5, the error amp gain increases. Conversely, if

the user decreases R4 while proportionally they increase C5, the error amp gain decreases. For the design

example, C5 was selected for 0.01 µF and R4 was selected for 49.9 kΩ. These values configure the

compensation network zero at 320 Hz. The error amp gain at frequencies greater than fZis: R4 / R5, which is

approximately 10 (20 dB).

Figure 19. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

l TEXAS INSTRUMENTS luau ‘00 ‘ouT

0.25 0.5 1 1.250.75 1.5

100

EFFICIENCY (%)

IOUT (A)

VIN = 24V

VIN = 48V

VIN = 75V

VIN = 7V

RT (k:)

OSCILLATOR FREQUENCY (kHz)

1 10 100 1000

100

1000

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

100k

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

www.ti.com

Product Folder Links: LM5575-Q1

Typical Application (continued)

Figure 20. Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured, and the error amplifier gain can be

configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier

compensation components can be designed with the guidelines given. Step-load transient tests can be

performed to verify acceptable performance. The step-load goal is minimum overshoot with a damped response.

C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value

of C6 must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer

function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of

the pole added by C6 is: fp2 = fz × C5 / C6.

8.2.3 Application Curves

Figure 21. Oscillator Frequency vs RTFigure 22. Demoboard Efficiency vs IOUT and VIN

l TEXAS INSTRUMENTS

LM5575-Q1

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9 Power Supply Recommendations

The LM5575-Q1 is designed to operate from an input voltage supply range between 6 V and 75 V. This input

supply must be able to withstand the maximum input current and maintain a voltage higher than 6 V. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the LM5575-Q1 supply voltage. That drop in supply voltage can cause a false UVLO fault trigger

and system reset. If the input supply is placed more than a few inches from the LM5575-Q1, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not

critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

The circuit in Functional Block Diagram serves as both a block diagram of the LM5575-Q1 and a typical

application board schematic for the LM5575-Q1. In a buck regulator, there are two loops where currents are

switched very fast. The first loop starts from the input capacitors, to the regulator VIN pin, to the regulator SW

pin, and then to the inductor then out to the load. The second loop starts from the output capacitor ground, to the

regulator PGND pins, to the regulator IS pins, to the diode anode, to the inductor and then out to the load. The

user can minimize the loop area of these two loops to reduce the stray inductance and to minimize noise and

possible erratic operation. A ground plane in the printed-circuit board (PCB) is recommended as a means to

connect the input filter capacitors to the output filter capacitors and the PGND pins of the regulator. Connect all

of the low-power ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND

and PGND pins together through the top-side copper area that covers the entire underside of the device. Place

several vias in this underside copper area to the ground plane.

The two highest power-dissipating components are the re-circulating diode and the LM5575-Q1 regulator IC. The

easiest method to determine the power dissipated within the LM5575-Q1 is to measure the total conversion

losses (Pin – Pout) then subtract the power losses in the Schottky diode, output inductor, and snubber resistor.

Equation 17 calculates an approximation for the Schottky diode loss.

P = (1 – D) × IOUT × Vfwd (17)

Equation 18 calculates an approximation for the output inductor power.

P = IOUT2× R x 1.1

where

• R is the DC resistance of the inductor and the 1.1 factor is an approximation for the AC losses (18)

If a snubber is used, Equation 19 calculates an approximation for the damping resistor power dissipation.

P = VIN2× Fsw × Csnub

where

• Fsw is the switching frequency and Csnub is the snubber capacitor (19)

The regulator has an exposed thermal pad to help power dissipation. Add several vias under the device to the

ground plane to greatly reduce the regulator junction temperature. Select a diode with an exposed pad to help

the power dissipation of the diode.

The most significant variables that affect the power dissipated by the LM5575-Q1 are the output current, input

voltage, and operating frequency. The power dissipated while the device operates near the maximum output

current and maximum input voltage can be appreciable. The operating frequency of the LM5575-Q1 evaluation

board has been designed for 300 kHz. When the device operates at 1.5-A output current with a 70-V input, the

power dissipation of the LM5575-Q1 regulator is approximately 1.25 W.

l TEXAS INSTRUMENTS SD UUUT p1 : (:12 S :1 (:2 3 _: MC} ® 3 I H ISYNC —C8— %’ TT. N, B g ..L_) I D J1 _ u _ C3 _ 5' C11 L1 13 [22995 65— ;m — — LM5575 F26: -a C“ 5 mi 1 ® EUﬁLUHTION BU. I R5 551812868—901 REU B S/N- GNU 1? ?all

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

www.ti.com

Product Folder Links: LM5575-Q1

10.2 Layout Examples

Figure 23. Silkscreen

Figure 24. Component Side

Figure 25. Solder Side

l TEXAS INSTRUMENTS

LM5575-Q1

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Product Folder Links: LM5575-Q1

10.3 Thermal Considerations

The junction-to-ambient thermal resistance of the LM5575-Q1 varies with the application. The most significant

variables are the area of copper in the PCB, the number of vias under the IC exposed pad, and the amount of

forced air cooling provided. As shown in the evaluation board artwork, the area under the LM5575-Q1

(component side) is covered with copper and there are 5 connection vias to the solder-side ground plane.

Additional vias under the IC have diminishing value as more vias are added. The integrity of the solder

connection from the IC exposed pad to the PCB is critical. Excessive voids will greatly diminish the thermal

dissipation capacity. The junction-to-ambient thermal resistance of the LM5575-Q1 mounted in the evaluation

board varies from 50°C/W with no airflow to 28°C/W with 900 LFM (linear feet per minute). With a 25°C ambient

temperature and no airflow, the predicted junction temperature for the LM5575-Q1 is 25 + (50 × 1.25) = 88°C. If

the evaluation board operates at 1.5-A output current, 70-V input voltage, and a high ambient temperature for a

prolonged period of time, the thermal shutdown protection within the IC may activate. The IC turns off to allow

the junction to cool, followed by restart with the soft-start capacitor reset to zero.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5575-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

l TEXAS INSTRUMENTS

LM5575-Q1

SNOSB23F –OCTOBER 2008–REVISED JULY 2019

www.ti.com

Product Folder Links: LM5575-Q1

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS mp mp mp mum.» mp1

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM5575Q0MH/NOPB ACTIVE HTSSOP PWP 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 150 LM5575

Q0MH

LM5575Q0MHX/NOPB ACTIVE HTSSOP PWP 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 150 LM5575

Q0MH

LM5575QMH/NOPB ACTIVE HTSSOP PWP 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM5575

QMH

LM5575QMHX/NOPB ACTIVE HTSSOP PWP 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM5575

QMH

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM5575-Q1 :

•Catalog: LM5575

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM5575Q0MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

LM5575QMHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM5575Q0MHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0

LM5575QMHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2021

Pack Materials-Page 2

I-III if i

www.ti.com

PACKAGE OUTLINE

TYP

6.6

6.2

14X 0.65

16X 0.30

0.19

4.55

(0.15) TYP

0 - 8 0.15

0.05

3.3

2.7

3.3

2.7

2X 1.34 MAX

NOTE 5

1.2 MAX

(1)

0.25

GAGE PLANE

0.75

0.50

NOTE 3

5.1

4.9

B4.5

4.3

4X 0.166 MAX

NOTE 5

4214868/A 02/2017

PowerPAD HTSSOP - 1.2 mm max heightPWP0016A

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present.

PowerPAD is a trademark of Texas Instruments.

116

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

THERMAL

PAD

www.ti.com

EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(3.4)

NOTE 9

(5)

NOTE 9

(3.3)

( 0.2) TYP

VIA (1.1) TYP

(1.1)

TYP

4214868/A 02/2017

PowerPAD HTSSOP - 1.2 mm max heightPWP0016A

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

EXPOSED

METAL

SOLDER MASK

DEFINED

SOLDER MASK

METAL UNDER SOLDER MASK

OPENING

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

(3.3)

BASED ON

0.125 THICK

STENCIL

14X (0.65)

(R0.05) TYP

(5.8)

4214868/A 02/2017

PowerPAD HTSSOP - 1.2 mm max heightPWP0016A

PLASTIC SMALL OUTLINE

2.79 X 2.790.175

3.01 X 3.010.15

3.3 X 3.3 (SHOWN)0.125

3.69 X 3.690.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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