Fiche technique pour NCP1589(A,B) de onsemi

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© Semiconductor Components Industries, LLC, 2017
February, 2019 − Rev. 3
1Publication Order Number:
NCP1589A/D
NCP1589A, NCP1589B
Synchronous Buck
Controller, Low Voltage
The NCP1589A/B is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V. This device is capable of converting
voltage from as low as 2.5 V. This 10−pin device provides an optimal
level of integration to reduce size and cost of the power supply.
Features include a 1.5 A gate driver design and an internally set 300
kHz or 600 kHz oscillator. In addition to the 1.5 A gate drive
capability, other efficiency enhancing features of the gate driver
include adaptive non−overlap circuitry. The NCP1589A/B also
incorporates an externally compensated error amplifier. Protection
features include programmable short circuit protection and
undervoltage lockout (UVLO).
Features
•VCC Range from 4.5 V to 13.2 V
•300 kHz and 600 kHz Internal Oscillator
•Boost Pin Operates to 30 V
•Voltage Mode PWM Control
•Precision 0.8 V Internal Reference
•Adjustable Output Voltage
•Internal 1.5 A Gate Drivers
•80% Max Duty Cycle
•Input Under Voltage Lockout
•Programmable Current Limit
•This is a Pb−Free Device
Applications
•Graphics Cards
•Desktop Computers
•Servers / Networking
•DSP & FPGA Power Supply
•DC−DC Regulator Modules
DFN10
CASE 485C
MARKING DIAGRAM
PIN CONNECTIONS
1589x = Specific Device Code
x = A or B
A = Assembly Location
L = Wafer Lot (Optional)
Y = Year
W = Work Week
G= Pb−Free Device
1
BOOT 10 PGOOD
2
LX
3
UG
4
LG
9 VOS
8FB
7 COMP/DISB
(Top View)
Device Package Shipping†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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5
GND 6VCC
(Note: Microdot may be in either location)
NCP1589AMNTWG
DFN10
(Pb−Free)
3000 /
Tape & Reel
NCP1589BMNTWG
1589x
ALYWG
G
NCP1589AMNTXG
NCP1589BMNTXG
NCP158 i— b1” : T-- H— _ LG i—‘ N — E :: GND vos 8 amuw __ c3 0 m R4 m u mm X X o7nF ”7W . m as a a u 2;; v v _ ' v 0 Figure 1. Typical Application Diagram 9 —I: F L F ; www.cnsemi.com 2
NCP1589A, NCP1589B
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2
Figure 1. Typical Application Diagram
BOOT
UG
LX
VCC
GND
FB
VOS
LG
PGOOD
VIN = 2.5 V − 20 VVCC = 4.5 V − 13.2 V
0.1mF
4.7nF
2x1800mF
2.2
1mH
1500mF
1.02k
R4
3.878kW
C3
0.014mF
1.02k
R3
74.2W
R1
4.12kW
C2
0.007mF
R2
17.08kW
C1
0.0015mF
1mF
COMP/DISB
ROCSET
NTD4806 NTD4809
3x22mF
1500mF
2x0.22mF
VBST = 4.5 V − 15 V
GND
VOUT
1.65 V
R9 R10
Figure 2. Detailed Block Diagram
POR
UVLO
PWM
OUT
LATCH
7
BOOT
UG
LX
LG
GND
CLOCK
RAMP
OSC
OSC
FB
VOCP
FAULT
FAULT
FAULT
SOFT
START
VOS PGOOD
MONITOR
OV and UV
PGOOD
0.8 V
(Vref)
0.8 V
(Vref)
COMP/DISB
+
−+
−
Q
R
S
8
9
10
+
−
+
−VCC
2 V
VCC
±10% of Vref
±25% of Vref
6
1
3
2
4
5
+
−
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PIN FUNCTION DESCRIPTION
Pin No. Symbol Description
1 BOOT Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin
and the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the
IC.
2 LX Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the
top MOSFET.
3 UG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.
4 LG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET.
5 GND IC ground reference. All control circuits are referenced to this pin.
6 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capaci-
tor to GND. Ensure that this decoupling capacitor is placed near the IC.
7 COMP/DISB Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM
comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop.
Pull this pin low for disable.
8 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com-
pensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to Vout.
9 VOS Voltage Offset Sense
10 PGOOD Power Good output. Pulled Low if VOS is ±10% of 0.8 V Vref.
ABSOLUTE MAXIMUM RATINGS
Pin Name Symbol VMAX VMIN
Main Supply Voltage Input VCC 15 V −0.3 V
Bootstrap Supply Voltage Input BOOT 35 V wrt/GND
40 V < 100 ns
15 V wrt/LX
−0.3 V
−0.3 V
−0.3 V
Switching Node (Bootstrap Supply Return) LX 35 V
40 V for < 100 ns
−5 V
−10 V for < 200 ns
High−Side Driver Output (Top Gate) UG 30 V wrt/GND
15 V wrt/LX
40 V for < 100 ns
−0.3 V wrt/LX
−2 V for < 200 ns
Low−Side Driver Output (Bottom Gate) LG VCC + 0.3 V −0.3 V
−5 V for < 200 ns
Feedback, VOS FB, VOS 5.0 V −0.3 V
COMP/DISB COMP/DISB 3.6 V −0.3 V
PGOOD PGOOD 7 V −0.3 V
MAXIMUM RATINGS
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient RqJA 165 °C/W
Thermal Resistance, Junction−to−Case RqJC 45 °C/W
Operating Junction Temperature Range TJ0 to 150 °C
Operating Ambient Temperature Range TA0 to 70 °C
Storage Temperature Range Tstg −55 to +150 °C
Moisture Sensitivity Level MSL 1 −
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
This device is ESD sensitive. Use standard ESD precautions when handling.
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NCP1589A, NCP1589B
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ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V,
CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)
Characteristic Conditions Min Typ Max Unit
VCC Voltage Range 4.5 13.2 V
Boost Voltage Range 13.2 V wrt LX 4.5 30 V
Supply Current
Quiescent Supply Current (NCP1589A) VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 8.0 mA
Boost Quiescent Current VFB = 1.0 V, No Switching 0.1 mA
Undervoltage Lockout
UVLO Threshold VCC Rising 3.8 4.0 4.2 V
UVLO Threshold VCC Falling 3.4 3.6 3.8 V
UVLO Hysteresis VCC Rising or VCC Falling 0.4 V
Switching Regulator
VFB Feedback Voltage (FB Tied to Comp. Measure FB Pin.) 0.7936 0.8 0.8064 V
Oscillator Frequency (NCP1589A) 270 300 330 kHz
Oscillator Frequency (NCP1589B) 540 600 660 kHz
Ramp−Amplitude Voltage 1.1 V
Minimum Duty Cycle 0 %
Maximum Duty Cycle 70 75 80 %
LG Minimum on Time 500 ns
Error Amplifier
Open Loop DC Gain (Note 1) 70 80 dB
Output Source Current
Output Sink Current
Vfb < 0.8 V
Vfb > 0.8 V
2.0
2.0
mA
Input Offset Voltage (Note 1) −2.0 0 2.0 mV
Input Bias Current 0.1 1.0 mA
Unity Gain Bandwidth (Note 1) 15 Mhz
Disable Threshold 0.6 0.8 V
Output Source Current During Disable 10 40 mA
Gate Drivers
Upper Gate Source VCC = 5 V, VUG − VLX = 2.5 V 1.5 A
Upper Gate Sink 1.4 W
Lower Gate Source 1.5 A
Lower Gate Sink VCC = 12 V 1.0 W
UG Falling to LG Rising Delay VCC = 12 V, UG−LX < 2.0 V, LG > 2.0 V 12.4 18 ns
LG Falling to UG Rising Delay VCC = 12 V, LG < 2.0 V, UG > 2.0 V 12.4 18 ns
Soft−Start
Soft−Start time 3.0 7.0 ms
Power Good
Output Voltage Logic Low, Sinking 4 mA 0.4 V
OVP Threshold to PGOOD Output Low Ramp VOS from 0.7 to 1.2.
Monitor when PGOOD goes Low
0.88 1.0 V
OVP Threshold to Part Disable Ramp VOS from 0.8 to 1.2.
Monitor when outputs disable
1.0 1.2 V
UVP Threshold to PGOOD Output Low Ramp VOS from 800 mV to 500 mV.
Monitor when PGOOD goes Low
0.65 0.72 V
UVP Threshold to Part Disable Ramp VOS from 800 mV to 500 mV.
Monitor when utputs stop switching
0.5 0.6 V
Overcurrent Protection
OC Current Source (Note 1) Sourced from LG pin, before SS 9.0 10 11 mA
1. Guaranteed by design but not tested in production.
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5
TYPICAL CHARACTERISTICS
303
010 70
TJ, JUNCTION TEMPERATURE (°C)
FSW, FREQUENCY (kHz)
302
301
300
299
Figure 3. Oscillator Frequency (FSW) vs.
Temperature
543
542
541
540
5390 20 406080
TJ, JUNCTION TEMPERATURE (°C)
OCP THRESHOLD (mV)
020406080
TJ, JUNCTION TEMPERATURE (°C)
ICC (mA)
5.3
5.0
4.7
4.4
3.5
Figure 4. Reference Voltage (Vref) vs.
Temperature
Figure 5. ICC vs. Temperature
3.8
4.1
VCC = 12 V
Figure 6. OCP Threshold at 55k vs. Temperature
808
04080
TJ, JUNCTION TEMPERATURE (°C)
Vref, REFERENCE (mV)
806
804
802
800
798
796
794
792
VCC = 5 V
20 30 40 50 60 20 60
NCP1589B
NCP1589A
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APPLICATIONS INFORMATION
Over Current Protection (OCP)
The NCP1589A/B monitors the voltage drop across the
low side mosfet and uses this information to determine if
there is excessive output current. The voltage across the low
side mosfet is measured from the LX pin, and is referenced
to ground. The over current measurement is timed to occur
at the end of the low side mosfet conduction period, just
before the bottom mosfet is turned off.
If the voltage drop across the bottom mosfet exceeds the
over current protection threshold, then an internal counter is
incremented. If the voltage drop does not exceed the over
current protection threshold, then the internal counter is
reset. The NCP1589A/B will latch the over current
protection fault condition only if the over current protection
threshold is exceeded for four consecutive cycles.
When the NCP1589A/B latches an over current
protection fault, both the high side and low side mosfets are
turned off. To reset the over current protection fault, the
power to the VCC pin must be cycled.
The over current threshold voltage can be externally, by
varying the value of the ROCSET resistor. The ROCSET
resistor is a resistor connected between the LG pin (low side
mosfet gate) and ground.
During startup, after the VCC and BOOT pins reach the
under voltage lock out threshold, the NCP1589A/B will
source 10 mA of current out of the LG pin. This current will
flow through the ROCSET resistor and produce a voltage
that is sampled and then used as the over current protection
threshold voltage. For example, if ROCSET is set to 10 kW,
the 10 mA of current will yield a 100 mV threshold, and if the
voltage drop across the low side mosfet exceeds 100 mV at
the end of its conduction period, then an over current event
will be detected.
If the ROCSET resistor is not present, then the over
current protection threshold will max out at 640 mV. The
valid range for ROCSET is 5 kW to 55 kW which yields a
threshold voltage range of 50 mV to 550 mV.
Internal Soft-Start
To prevent excess inrush current during startup, the
NCP1589A/B uses a calibrated current source with an
internal soft start capacitor to ramp the reference voltage
from 0 to 800 mV over a period of 4 ms. The softstart ramp
generator will reset if the input power supply voltages reach
the under voltage lockout threshold, or if the NCP1589A/B
is disabled by having the COMP pin pulled low.
Startup into a Precharged Load
During a startup and soft start sequence the NCP1589A
will detect a residual charge on the output capacitors and not
forcefully discharge the capacitors before beginning the
softstart sequence, instead, the softstart ramping of the
output will begin at the voltage level of the residual charge.
For example, if the NCP1589A/B is configured to provide
a regulated output voltage of 2.5 V, the normal softstart
sequence will ramp the output voltage from 0 to 2.5 V in
4.2 ms; however if the output capcitors already have a 1.2 V
charge on them, the NCP1589A/B will not discharge the
capacitors, instead the softstart sequence will begin at 1.2 V
and then ramp the output to 2.5 V.
Power Good
The PGOOD pin is an open drain active high output pin
that signals the condition of the VOS (Voltage Output Sense)
pin. PGOOD is pulled low during soft start cycle, and if there
is a latched over current, over voltage, or under voltage fault.
If the voltage on the VOS pin is within ±10% of Vref
(800 mV) then the PGOOD pin will not be pulled low. The
PGOOD pin does not have an internal pull-up resistor.
Overvoltage Protection
If the voltage on the VOS pin exceeds the over voltage
threshold the NCP1589A/B will latch an over voltage fault.
During an over voltage fault the UG pin will be pulled low,
and the LG pin will be high while the until the voltage on the
VOS pin goes below Vref/2 (400 mV). The NCP1589A will
continue drive the LG pin, LG will go high if VOS exceeds
1 V and then go low when VOS goes below 400 mV. The
power to the NCP1589 must be cycled to reset the over
voltage protection fault.
Under Voltage Protection
If the voltage on the VOS pin falls below the under voltage
threshold after the soft start cycle completes, then the
NCP1589A/B will latch an under voltage fault. During an
under voltage fault, both the UG and LG pins will be pulled
low. The power to the NCP1589 must be cycled to reset the
under voltage protection fault.
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NCP1589A, NCP1589B
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7
Figure 7. Typical Startup Sequence
VCC
COMP
UG
LG
VOUT
FB
PGOOD
Internal
UVLO
Fault
−0.7 V
1.45 V
700 mV
50 mV
OCP
Program-
mable
0.8 V
NORMALSSUVLOPOR
4.0 V
3.6 V
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NCP1589A, NCP1589B
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8
Figure 8. Typical Power Good Function
U
G
LG
0.88V
0.4V
1.0V
PGOOD
0.88V
0.8V
0.72V
0.8V
0.6V
VOS
Overvoltage Undervoltage
Feedback and Compensation
The NCP1589A/B allows the output voltage to be
adjusted from 0.8 V to 5.0 V via an external resistor divider
network. The controller will try to maintain 0.8 V at
feedback pin. Thus, if a resistor divider circuit was placed
across the feedback pin to VOUT, the controller will regulate
the output voltage proportional to the resistor divider
network in order to maintain 0.8 V at the FB pin. The same
formula applies to the VOS pin and the controller will
maintain 0.8 V at the VOS pin.
VOUT
R1
R4
FB
Figure 9.
The relationship between the resistor divider network
above and the output voltage is shown in the following
equation:
R4+R1 ǒVREF
VOUT *VREFǓ
The same formula can be applied to the feedback resistors
at VOS.
R9+R10 ǒVREF
VOUT *VREFǓ
Design Example
Voltage Mode Control Loop with TYPE III
Compensation
Converter Parameters:
Input Voltage: VIN = 5 V
Output Voltage: VOUT = 1.65 V
Switching Frequency: 300 kHz
Total Output Capacitance: COUT = 3600 mF
Total ESR: ESR = 6 mW
Output Inductance: LOUT: 1 mH
Ramp Amplitude: VRAMP = 1.1 V
−
+
Figure 10.
C3R3
R1
C1
C2R2
VOUT VCOMP
Vref
E/A
R4
a.. Set a target for the close loop bandwidth at 1/6th of
the switching frequency.
Fcross_over :+50 kHz
R1 SW SW)
NCP1589A, NCP1589B
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9
b.. Output Filter Double Pole Frequency
Flc +2.653 kHz
Flc :+1
2@p@LOUT @COUT
Ǹ
c.. ESR Zero Frequency:
FESR +7.368 kHz
FESR :+1
2@p@COUT @CESR
Step 1: Set a value for R1 between 2 kW and 5 kW
R1 :+4.12 kW
Step 2: Pick compensation DC gain (R2/R1) for desired
close loop bandwidth.
VRAMP :+1.1 V
R2 :+R1 @ǒVRAMP
VIN Ǔ@ǒFcross_over
Flc Ǔ
R2 +17.085 kW
Step 3: Place 1st zero at half the output filter double pole
frequency.
C2 :+
2@LOUT @COUT
Ǹ
R2
C2 +7.024 10−3mF
Step 4: Place 1st pole at ESR zero frequency.
C1 :+C2
C2 @R2 @2@p@FESR *1
C1 +1.542 10−3mF
Step 5: Place 2nd zero at the output filter double pole
frequency.
R3 :+R1
FSW
2@Flc *1
R3 +74.169 W
Step 6: Place 2nd pole at half the switching frequency.
C3 :+1
ǒp@R3 @FSWǓ
C3 +0.014 mF
Step 7: R4 is sized to maintain the feedback voltage to
Vref = 0.8 V.
R4 :+
VREF @R1
VOUT *VREF
R4 +3.878 kW
The Component values for Type III Compensation are:
R1 = 4.12 kW
R2 = 17.085 kW
R3 = 74.169 W
R4 = 3.878 kW
C1 = 0.0015 mF
C2 = 0.007 mF
C3 = 0.014 mF
NOTE: Recommend to change values to industry
standard component values.
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DFN10, 3x3, 0.5P
CASE 485C
ISSUE E
DATE 11 FEB 2016
SCALE 2:1
10X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
15
10 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B
ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET-
TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON
SIDE VIEW OF PACKAGE.
B
A
0.15 CTOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN ONE
REFERENCE
0.10 C
0.08 C
(A3)
C
10X
10X
0.10 C
0.05 C
A B
NOTE 3
K
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 2.40 2.60
E3.00 BSC
E2 1.70 1.90
e0.50 BSC
L0.35 0.45
L1 0.00 0.03
DETAIL A
K0.19 TYP
2X
2X
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
XXXXX
XXXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
(Note: Microdot may be in either location)
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
2.64
1.90
0.50
0.55
10X
3.30
0.30
10X
DIMENSIONS: MILLIMETERS
PITCH
PACKAGE
OUTLINE
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ALTERNATE B−2ALTERNATE B−1
ALTERNATE A−2ALTERNATE A−1
DETAIL B
WETTABLE FLANK OPTION
CONSTRUCTION
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DFN10, 3X3 MM, 0.5 MM PITCH
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LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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