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TMS320F2802x Microcontrollers
1 Features
• High-efficiency 32-bit CPU (TMS320C28x)
– 60 MHz (16.67-ns cycle time)
– 50 MHz (20-ns cycle time)
– 40 MHz (25-ns cycle time)
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
– Harvard bus architecture
– Atomic operations
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
• Endianness: Little endian
• Low cost for both device and system:
– Single 3.3-V supply
– No power sequencing requirement
– Integrated power-on and brown-out resets
– Small packaging, as low as 38-pin available
– Low power
– No analog support pins
• Clocking:
– Two internal zero-pin oscillators
– On-chip crystal oscillator and external clock
input
– Watchdog timer module
– Missing clock detection circuitry
• Up to 22 individually programmable, multiplexed
GPIO pins with input filtering
• Peripheral Interrupt Expansion (PIE) block that
supports all peripheral interrupts
• Three 32-bit CPU timers
• Independent 16-bit timer in each Enhanced Pulse
Width Modulator (ePWM)
• On-chip memory
– Flash, SARAM, OTP, Boot ROM available
• Code-security module
• 128-bit security key and lock
– Protects secure memory blocks
– Prevents firmware reverse engineering
• Serial port peripherals
– One Serial Communications Interface (SCI)
Universal Asynchronous Receiver/Transmitter
(UART) module
– One Serial Peripheral Interface (SPI) module
– One Inter-Integrated-Circuit (I2C) module
• Enhanced control peripherals
– ePWM
– High-Resolution PWM (HRPWM)
– Enhanced Capture (eCAP) module
– Analog-to-Digital Converter (ADC)
– On-chip temperature sensor
– Comparator
• Advanced emulation features
– Analysis and breakpoint functions
– Real-time debug through hardware
• Package options
– 38-pin DA Thin Shrink Small-Outline Package
(TSSOP)
– 48-pin PT Low-Profile Quad Flatpack (LQFP)
• Temperature options
– T: –40°C to 105°C
– S: –40°C to 125°C
– Q: –40°C to 125°C
(AEC Q100 qualification for automotive
applications)
2 Applications
•Air conditioner outdoor unit
•Inverter & motor control
•Textile machine
•Micro inverter
•AC drive power stage module
•AC-input BLDC motor drive
•DC-input BLDC motor drive
•Industrial AC-DC
•Three phase UPS
•Merchant DC/DC
•Merchant network & server PSU
•Merchant telecom rectifiers
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The F2802x family of microcontrollers provides the power of the C28x core coupled with highly integrated control
peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also
provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to
allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have
been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-
scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low
overhead and latency.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information
PART NUMBER(1) PACKAGE BODY SIZE
TMS320F28027PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28026PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28023PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28022PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28021PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28020PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F280200PT LQFP (48) 7.0 mm × 7.0 mm
TMS320F28027DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F28026DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F28023DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F28022DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F28021DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F28020DA TSSOP (38) 12.5 mm × 6.2 mm
TMS320F280200DA TSSOP (38) 12.5 mm × 6.2 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
2Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS comm comm com: | HHHHM++ ¢ | Cnpynghl © 2017, Texas Instrumems Incurpnrmed
4 Functional Block Diagram
Functional Block Diagram shows the functional block diagram for the device.
3 External Interrupts
16-Bit Peripheral Bus
SCI
(4L FIFO)
ePWM
SPI
(4L FIFO)
I2C
(4L FIFO) HRPWM
eCAP
32-Bit Peripheral Bus
Code
Security
Module
GPIO MUX
C28x
32-Bit CPU
A7:0
B7:0
PIE
CPU Timer 0
CPU Timer 1
CPU Timer 2
TCK
TDI
TMS
TDO
TRST
OSC1,
OSC2,
Ext,
PLL,
LPM,
WD
XCLKIN
X2
XRS
32-Bit Peripheral Bus
ECA Px
EPWMxA
EPWMSYNCI
SDAx
SPISTEx
SCLx
SPISIMOx
SPICLKx
COMP1OUT
SCIRXDx
GPIO
Mux
LPM Wakeup
AIO
MUX
ADC
PSWD
FLASH
8K/16K/32K × 16
Secure
OTP 1K × 16
Secure
OTP/Flash
Wrapper
M0
SARAM 1K × 16
(0-wait)
M1
SARAM 1K × 16
(0-wait)
Boot-ROM
8K × 16
(0-wait)
SARAM
1K/3K/4K × 16
(0-wait)
Secure
COMP
COMP1A
COMP1B
COMP2A
COMP2B
COMP2OUT
X1
GPIO
MUX
VREG
From
COMP1OUT,
COMP2OUT
POR/
BOR
Memory Bus
Memory Bus
Memory Bus
TZx
SCITXDx
SPISOMIx
EPWMxB
EPWMSYNCO
Copyright © 2017, Texas Instruments Incorporated
32-Bit Peripheral Bus
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 4-1. Functional Block Diagram
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams.............................................................. 8
7.2 Signal Descriptions................................................... 10
8 Specifications................................................................ 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD Ratings – Automotive....................................... 15
8.3 ESD Ratings – Commercial...................................... 16
8.4 Recommended Operating Conditions.......................16
8.5 Power Consumption Summary................................. 17
8.6 Electrical Characteristics...........................................21
8.7 Thermal Resistance Characteristics......................... 23
8.8 Thermal Design Considerations................................24
8.9 JTAG Debug Probe Connection Without Signal
Buffering for the MCU..................................................24
8.10 Parameter Information............................................ 25
8.11 Test Load Circuit..................................................... 25
8.12 Power Sequencing..................................................26
8.13 Clock Specifications................................................29
8.14 Flash Timing............................................................33
9 Detailed Description......................................................36
9.1 Overview................................................................... 36
9.2 Memory Maps........................................................... 44
9.3 Register Maps...........................................................51
9.4 Device Emulation Registers......................................52
9.5 VREG/BOR/POR...................................................... 53
9.6 System Control......................................................... 55
9.7 Low-power Modes Block...........................................63
9.8 Interrupts...................................................................64
9.9 Peripherals................................................................69
10 Applications, Implementation, and Layout............. 119
10.1 TI Reference Design............................................. 119
11 Device and Documentation Support........................120
11.1 Device and Development Support Tool
Nomenclature............................................................ 120
11.2 Tools and Software................................................121
11.3 Documentation Support........................................ 123
11.4 Support Resources............................................... 124
11.5 Trademarks........................................................... 124
11.6 Electrostatic Discharge Caution............................ 124
11.7 Glossary................................................................ 124
12 Mechanical, Packaging, and Orderable
Information.................................................................. 125
12.1 Packaging Information.......................................... 125
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
4Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
5 Revision History
Changes from October 30, 2020 to January 18, 2021 (from Revision O (October 2020) to
Revision P (January 2021)) Page
•Device Comparison: Updated part numebrs.......................................................................................................6
•ESD Ratings – Automotive: Updated part numbers......................................................................................... 15
•ESD Ratings – Commercial: Updated part numbers........................................................................................ 16
•Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................120
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
6 Device Comparison
Table 6-1 lists the features of the TMS320F2802x devices.
Table 6-1. Device Comparison
FEATURE TYPE
(1)
28027
28027-Q1
28027F
28027F-Q1
(60 MHz)(2)
28026
28026-Q1
28026F
28026F-Q1
(60 MHz)(2)
28023
28023-Q1
(50 MHz)
28022
28022-Q1
(50 MHz)
28021
(40 MHz)
28020
(40 MHz)
280200
(40 MHz)
Package Type
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
38-Pin
DA
TSSOP
48-Pin
PT
LQFP
Instruction cycle – 16.67 ns 16.67 ns 20 ns 20 ns 25 ns 25 ns 25 ns
On-chip flash (16-bit word) – 32K 16K 32K 16K 32K 16K 8K
On-chip SARAM (16-bit word) – 6K 6K 6K 6K 5K 3K 3K
Code security for on-chip
flash/SARAM/OTP blocks – Yes Yes Yes Yes Yes Yes Yes
Boot ROM (8K x 16) – Yes Yes Yes Yes Yes Yes Yes
One-time programmable
(OTP) ROM (16-bit word) – 1K 1K 1K 1K 1K 1K 1K
ePWM channels 1 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4)
eCAP inputs 0 1 1 1 1 1 1 –
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes
12-Bit ADC
MSPS
3
4.6 4.6 3 3 2 2 2
Conversion
Time 216.67 ns 216.67 ns 260 ns 260 ns 500 ns 500 ns 500 ns
Channels 7 13 7 13 7 13 7 13 7 13 7 13 7 13
Temperature
Sensor Yes Yes Yes Yes Yes Yes Yes
Dual Sample-
and-Hold Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers – 3 3 3 3 3 3 3
High-resolution ePWM
Channels 14 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A) –––
Comparators w/ Integrated
DACs 012121212121212
Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1
Serial Peripheral Interface
(SPI) 11111111
Serial Communications
Interface (SCI) (UART
Compatible)
01111111
I/O pins
(shared)
Digital (GPIO) – 20 22 20 22 20 22 20 22 20 22 20 22 20 22
Analog (AIO) – 6 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Temperature
options
T: –40°C to
105°C – Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
S: –40°C to
125°C – Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Q: –40°C to
125°C(3) – Yes Yes Yes Yes Yes Yes Yes Yes – – – – – –
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
(2) TMS320F28027F and TMS320F28026F are InstaSPIN-FOC™-enabled MCUs. For more information, see Section 11.3 for a list of
InstaSPIN Technical Reference Manuals.
(3) The letter Q refers to AEC Q100 qualification for automotive applications.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
6Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
6.1 Related Products
For information about similar products, see the following links:
TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-
count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The
F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable
logic block (CLB) versions are available.
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS E ( u E s x E u 2
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the 48-pin PT low-profile quad flatpack (LQFP) pin assignments. Figure 7-2 shows the 38-pin
DA thin shrink small-outline package (TSSOP) pin assignments.
GPIO2/EPWM2A 37
GPIO3/EPWM2B/COMP2OUT 38
GPIO4/EPWM3A 39
GPIO5/EPWM3B/ECAP1 40
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41
GPIO7/EPWM4B/SCIRXDA 42
VSS
43
VDD
44
X1 45
X2 46
GPIO12/ /SCITXDATZ1 47
GPIO28/SCIRXDA/SDAA/TZ2 48
GPIO29/SCITXDA/SCLA/TZ3 1
XRS
2
TRST
3
ADCINA6/AIO6 4
ADCINA4/COMP2A/AIO4 5
ADCINA7 6
ADCINA3 7
ADCINA1 8
ADCINA2/COMP1A/AIO2 9
ADCINA0/VREFHI 10
VDDA 11
V/V
SSA REFLO 12
24 GPIO18/SPICLKA/SCITXDA/XCLKOUT
23 GPIO38/XCLKIN(TCK)
22 GPIO37(TDO)
21 GPIO36(TMS)
20 GPIO35(TDI)
19 GPIO34/COMP2OUT
18 ADCINB7
17 ADCINB6/AIO14
16 ADCINB4/COMP2B/AIO12
15 ADCINB3
14 ADCINB2/COMP1B/AIO10
13 ADCINB1
36
VREGENZ
35
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
34
VDDIO
33 VSS
32 VDD
31 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
30 TEST
29 GPIO0/EPWM1A
28 GPIO1/EPWM1B/COMP1OUT
27 GPIO16/SPISIMOA/TZ2
26 GPIO17/SPISOMIA/TZ3
25 GPIO19/XCLKIN/ /SCIRXDA/ECAP1SPISTEA
Figure 7-1. 2802x 48-Pin PT LQFP (Top View)
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
8Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS JJJJJJJJJJJJJJJJJJJ
VDD 1
VSS 2
VDDIO
3
VREGENZ
4
GPIO2/EPWM2A 5
GPIO3/EPWM2B 6
GPIO4/EPWM3A 7
GPIO5/EPWM3B/ECAP1 8
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 9
GPIO7/EPWM4B/SCIRXDA 10
VSS
11
VDD
12
GPIO12/ /SCITXDATZ1 13
GPIO28/SCIRXDA/SDAA/TZ2 14
GPIO29/SCITXDA/SCLA/TZ3 15
XRS
16
TRST
17
ADCINA6/AIO6 18
ADCINA4/AIO4 19
TEST
38
GPIO0/EPWM1A
37
GPIO1/EPWM1B/COMP1OUT
36
GPIO16/SPISIMOA/TZ2
35
GPIO17/SPISOMIA/TZ3
34
GPIO19/XCLKIN/ /SCIRXDA/ECAP1SPISTEA
33
GPIO18/SPICLKA/SCITXDA/XCLKOUT
32
GPIO38/XCLKIN (TCK)
31
GPIO37 (TDO)
30
GPIO36 (TMS)
29
GPIO35 (TDI)
28
GPIO34
27
ADCINB6/AIO14
26
ADCINB4/AIO12
25
ADCINB2/COMP1B/AIO10
24
V/V
SSA REFLO
23
VDDA
22
ADCINA0/VREFHI
21
ADCINA2/COMP1A/AIO2
20
Figure 7-2. 2802x 38-Pin DA TSSOP (Top View)
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
7.2 Signal Descriptions
Section 7.2.1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions.
Some peripheral functions may not be available in all devices. See Table 6-1 for details. Inputs are not 5-V
tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-
pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The
pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.
Note
When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins
could glitch during power up. This potential glitch will finish before the boot mode pins are read and
will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied
externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins
and any external driver could be considered to limit the potential for degradation to the pin and/or
external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply.
However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before
the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin
during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring
that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
7.2.1 Signal Descriptions
TERMINAL
I/O/Z DESCRIPTION
NAME(1) PT
PIN NO.
DA
PIN NO.
JTAG
TRST 2 16 I
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode, and the test reset signals
are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times
during normal device operation. An external pulldown resistor is required on this
pin. The value of this resistor should be based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Because this is application-specific, TI recommends validating each
target board for proper operation of the debugger and the application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup (↑)
TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
input is clocked into the TAP controller on the rising edge of TCK. (↑)
TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
selected register (instruction or data) on a rising edge of TCK. (↑)
TDO See GPIO37 O/Z
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
TEST 30 38 I/O Test Pin. Reserved for TI. Must be left unconnected.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
TERMINAL
I/O/Z DESCRIPTION
NAME(1) PT
PIN NO.
DA
PIN NO.
CLOCK
XCLKOUT See GPIO18 O/Z
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the
same frequency, one-half the frequency, or one-fourth the frequency of
SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.
At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by
setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to
XCLKOUT for this signal to propogate to the pin.
XCLKIN See GPIO19 and GPIO38 I
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the
X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the
XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock
for normal device operation may need to incorporate some hooks to disable this
path during debug using the JTAG connector. This is to prevent contention with the
TCK signal, which is active during JTAG debug sessions. The zero-pin internal
oscillators may be used during this time to clock the device.
X1 45 – I
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a
ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN
path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it
must be tied to GND. (I)
X2 46 – O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS 3 17 I/OD
Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-
on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-
out condition, this pin is driven low by the device. An external circuit may also drive
this pin to assert a device reset. This pin is also driven low by the MCU when a
watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from
2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be 100 nF or smaller. These
values will allow the watchdog to properly drive the XRS pin to VOL within
512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the
source, a device reset causes the device to terminate execution. The program
counter points to the address contained at the location 0x3F FFC0. When reset is
deactivated, execution begins at the location designated by the program counter.
The output buffer of this pin is an open-drain device with an internal pullup. (↑) If
this pin is driven by an external device, it should be done using an open-drain
device.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 6 – I ADC Group A, Channel 7 input
ADCINA6 4 18 I ADC Group A, Channel 6 input
AIO6 I/O Digital AIO 6
ADCINA4
5 19
I ADC Group A, Channel 4 input
COMP2A I Comparator Input 2A (available in 48-pin device only)
AIO4 I/O Digital AIO 4
ADCINA3 7 – I ADC Group A, Channel 3 input
ADCINA2
9 20
I ADC Group A, Channel 2 input
COMP1A I Comparator Input 1A
AIO2 I/O Digital AIO 2
ADCINA1 8 – I ADC Group A, Channel 1 input
ADCINA0
10 21
I ADC Group A, Channel 0 input
VREFHI I ADC External Reference High – only used when in ADC external reference mode.
See Section 9.9.1.1, ADC.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
TERMINAL
I/O/Z DESCRIPTION
NAME(1) PT
PIN NO.
DA
PIN NO.
ADCINB7 18 – I ADC Group B, Channel 7 input
ADCINB6 17 26 I ADC Group B, Channel 6 input
AIO14 I/O Digital AIO 14
ADCINB4
16 25
I ADC Group B, Channel 4 input
COMP2B I Comparator Input 2B (available in 48-pin device only)
AIO12 I/O Digital AIO12
ADCINB3 15 – I ADC Group B, Channel 3 input
ADCINB2
14 24
I ADC Group B, Channel 2 input
COMP1B I Comparator Input 1B
AIO10 I/O Digital AIO 10
ADCINB1 13 – I ADC Group B, Channel 1 input
CPU AND I/O POWER
VDDA 11 22 Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin.
VSSA 12 23 Analog Ground Pin
VREFLO I ADC External Reference Low (always tied to ground)
VDD
32 1 CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF
capacitor between each VDD pin and ground. Higher value capacitors may be
used.
43 11
VDDIO 35 4
Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG
is enabled. Place a decoupling capacitor on this pin. The exact value should be
determined by the system voltage regulation solution.
VSS
33 2 Digital Ground Pins
44 12
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 34 3 I
Internal voltage regulator (VREG) enable with internal pulldown. Tie directly to VSS
(low) to enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to disable the
VREG and use an external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS (2)
GPIO0
29 37
I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
– – –
– – –
GPIO1
28 36
I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
– –
COMP1OUT O Direct output of Comparator 1
GPIO2
37 5
I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
– –
– –
GPIO3
38 6
I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
– –
COMP2OUT O Direct output of Comparator 2 (available in 48-pin device only)
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
TERMINAL
I/O/Z DESCRIPTION
NAME(1) PT
PIN NO.
DA
PIN NO.
GPIO4
39 7
I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A and HRPWM channel
– –
– –
GPIO5
40 8
I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
– –
ECAP1 I/O Enhanced Capture input/output 1
GPIO6
41 9
I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A and HRPWM channel
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7
42 10
I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
– –
GPIO12
47 13
I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
SCITXDA O SCI-A transmit data
– –
GPIO16
27 35
I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI slave in, master out
– –
TZ2 I Trip Zone input 2
GPIO17
26 34
I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
– –
TZ3 I Trip zone input 3
GPIO18
24 32
I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
SCITXDA O SCI-A transmit
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,
one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is
controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV
to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
GPIO19
25 33
I/O/Z General-purpose input/output 19
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by
the mux function of this pin. Care must be taken not to enable this path for clocking
if it is being used for the other periperhal functions
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDA I SCI-A receive
ECAP1 I/O Enhanced Capture input/output 1
GPIO28
48 14
I/O/Z General-purpose input/output 28
SCIRXDA I SCI receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
TERMINAL
I/O/Z DESCRIPTION
NAME(1) PT
PIN NO.
DA
PIN NO.
GPIO29
1 15
I/O/Z General-purpose input/output 29.
SCITXDA O SCI transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
GPIO32
31 –
I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33
36 –
I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
GPIO34
19 27
I/O/Z General-Purpose Input/Output 34
COMP2OUT O Direct output of Comparator 2. COMP2OUT signal is not available in the DA
package.
– –
– –
GPIO35
20 28
I/O/Z General-Purpose Input/Output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK
GPIO36
21 29
I/O/Z General-Purpose Input/Output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
GPIO37
22 30
I/O/Z General-Purpose Input/Output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
GPIO38
23 31
I/O/Z General-Purpose Input/Output 38
TCK I JTAG test clock with internal pullup
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by
the mux function of this pin. Care must be taken to not enable this path for clocking
if it is being used for the other functions.
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate
functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output
path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal.
See the System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual for details.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
Supply voltage VDDIO (I/O and Flash) with respect to VSS –0.3 4.6 V
VDD with respect to VSS –0.3 2.5
Analog voltage VDDA with respect to VSSA –0.3 4.6 V
Input voltage VIN (3.3 V) –0.3 4.6 V
VIN (X1) –0.3 2.5
Output voltage VO–0.3 4.6 V
Input clamp current
Digital/analog input (per pin), IIK
(VIN < VSS or VIN > VDDIO)(3) –20 20
mA
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA)–20 20
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)–20 20
Output clamp current IOK (VO < 0 or VO > VDDIO) –20 20 mA
Junction temperature(4) TJ–40 150 °C
Storage temperature(4) Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 8.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics; Calculating Useful Lifetimes of Embedded
Processors; and Calculating FIT for a Mission Profile.
8.2 ESD Ratings – Automotive
VALUE UNIT
TMS320F28027-Q1, TMS320F28027F-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28023-Q1, TMS320F28022-Q in 48-pin
PT package
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) All pins ±2000
V
Charged device model (CDM), per AEC Q100-011
All pins except corner pins ±500
Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37,
48
±750
TMS320F28027-Q1, TMS320F28027F-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28023-Q1, TMS320F28022-Q1 in 38-pin
DA package
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) All pins ±2000
V
Charged device model (CDM), per AEC Q100-011
All pins except corner pins ±500
Corner pins on 38-pin DA:
1, 19, 20, 38 ±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8.3 ESD Ratings – Commercial
VALUE UNIT
TMS320F28027-Q1, TMS320F28027F-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28023-Q1, TMS320F28022-Q1,
TMS320F28021, TMS320F28020, TMS320F280200 in 48-pin PT package
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002(2) ±500
TMS320F28027-Q1, TMS320F28027F-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28023-Q1, TMS320F28022-Q1,
TMS320F28021, TMS320F28020, TMS320F280200 in 38-pin DA package
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.4 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V
Device supply voltage CPU, VDD (When internal VREG is
disabled and 1.8 V is supplied externally) 1.71 1.8 1.995 V
Supply ground, VSS 0 V
Analog supply voltage, VDDA 2.97 3.3 3.63 V
Analog ground, VSSA 0 V
Device clock frequency (system clock)
28020, 28021, 280200 2 40
MHz28022, 28023 2 50
28026, 28027 2 60
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V
High-level output source current, VOH = VOH(MIN), IOH
All GPIO/AIO pins –4 mA
Group 2(2) –8 mA
Low-level output sink current, VOL = VOL(MAX), IOL
All GPIO/AIO pins 4 mA
Group 2(2) 8 mA
Junction temperature, TJ (3)
T version –40 105
°C
S version –40 125
Q version
(AEC Q100
Qualification)
–40 125
(1) A tolerance of ±10% may be used for VDDIO if the BOR is not used. See the TMS320F2802x, TMS320F2802xx MCUs Silicon Errata for
more information. VDDIO tolerance is ±5% if the BOR is enabled.
(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37
(3) TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. See Section 8.8,
Thermal Design Considerations.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8.5 Power Consumption Summary
8.5.1 TMS320F2802x/F280200 Current Consumption at 40-MHz SYSCLKOUT
MODE(1) TEST CONDITIONS
VREG ENABLED VREG DISABLED
IDDIO (2) IDDA (3) IDD IDDIO (2) IDDA (3)
TYP(4) MAX TYP(4) MAX TYP(4) MAX TYP(4) MAX TYP(4) MAX
Operational
(Flash)
The following peripheral clocks are
enabled:
• ePWM1/2/3/4
• eCAP1
• SCI-A
• SPI-A
• ADC
• I2C
• COMP1/2
• CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected.(5)
Code is running out of flash with 1 wait-
state.
XCLKOUT is turned off.
70 mA 80 mA 13 mA 18 mA 62 mA 70 mA 15 mA 18 mA 13 mA 18 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are off.
13 mA 16 mA 53 μA 58 μA 15 mA 17 mA 120 μA 400 μA 53 μA 58 μA
STANDBY Flash is powered down.
Peripheral clocks are off. 3 mA 6 mA 10 μA 15 μA 3 mA 6 mA 120 μA 400 μA 10 μA 15 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(6)
50 μA 10 μA 15 μA 15 μA 25 μA 10 μA 15 μA
(1) For the TMS320F280200 device, subtract the IDD current number for eCAP (see Table 8-1) from IDD (VREG disabled)/IDDIO (VREG
enabled) current numbers shown in Section 8.5.1 for operational mode.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(4) The TYP numbers are applicable over room temperature and nominal voltage.
(5) The following is done in a loop:
• Data is continuously transmitted out of SPI-A and SCI-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(6) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
8.5.2 TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
MODE TEST CONDITIONS
VREG ENABLED VREG DISABLED
IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
Operational
(Flash)
The following peripheral clocks are
enabled:
• ePWM1/2/3/4
• eCAP1
• SCI-A
• SPI-A
• ADC
• I2C
• COMP1/2
• CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected.(4)
Code is running out of flash with 1 wait-
state.
XCLKOUT is turned off.
80 mA 90 mA 13 mA 18 mA 71 mA 80 mA 15 mA 18 mA 13 mA 18 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are off.
16 mA 19 mA 64 μA 69 μA 17 mA 20 mA 120 μA 400 μA 64 μA 69 μA
STANDBY Flash is powered down.
Peripheral clocks are off. 4 mA 7 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(5)
50 μA 10 μA 15 μA 15 μA 25 μA 10 μA 15 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A and SCI-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
8.5.3 TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
MODE TEST CONDITIONS
VREG ENABLED VREG DISABLED
IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
Operational
(Flash)
The following peripheral clocks
are enabled:
• ePWM1/2/3/4
• eCAP1
• SCI-A
• SPI-A
• ADC
• I2C
• COMP1/2
• CPU-TIMER0/1/2
All PWM pins are toggled at
60 kHz.
All I/O pins are left
unconnected.(4)
Code is running out of flash
with 2 wait states.
XCLKOUT is turned off.
90 mA 100 mA 13 mA 18 mA 80 mA 90 mA 15 mA 18 mA 13 mA 18 mA
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
MODE TEST CONDITIONS
VREG ENABLED VREG DISABLED
IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
IDLE
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are turned
off.
18 mA 23 mA 75 μA 80 μA 19 mA 24 mA 120 μA 400 μA 75 μA 80 μA
STANDBY Flash is powered down.
Peripheral clocks are off. 4 mA 7 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(5)
50 μA 10 μA 15 μA 15 μA 25 μA 10 μA 15 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A and SCI-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8.5.4 Reducing Current Consumption
The 2802x/280200 devices incorporate a method to reduce the device current consumption. Because each
peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved
by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of
the three low-power modes could be taken advantage of to reduce the current consumption even further. Table
8-1 indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 8-1. Typical Current Consumption by Various
Peripherals (at 60 MHz)
PERIPHERAL
MODULE(1) (3)
IDD CURRENT
REDUCTION (mA)
ADC 2(2)
I2C 3
ePWM 2
eCAP 2
SCI 2
SPI 2
COMP/DAC 1
HRPWM 3
CPU-TIMER 1
Internal zero-pin oscillator 0.5
(1) All peripheral clocks (except CPU Timer clocks) are disabled
upon reset. Writing to/reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA) as well.
(3) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for
one ePWM module.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the
peripherals (enabled by that application) must be added to the baseline IDD current.
Following are other methods to reduce power consumption further:
• The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18
mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320F2802x,TMS320F2802xx Technical Reference Manual to ensure each module is powered down
as well.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8.5.5 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
0
10
20
30
40
50
60
70
80
90
100
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
Operational Current (mA)
IDDIO (mA) IDDA
Figure 8-1. Typical Operational Current Versus Frequency (F2802x/F280200)
Operational Pow e r vs Fre que ncy
200
250
300
350
400
450
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
Operational Power (mW)
Figure 8-2. Typical Operational Power Versus Frequency (F2802x/F280200)
8.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = IOH MAX 2.4 V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
IIL
Input current
(low level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = 0 V All GPIO –80 –140 –205
μA
XRS pin –225 –290 –360
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = 0 V ±2
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TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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I TEXAS INSTRUMENTS
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH
Input current
(high level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = VDDIO ±2
μA
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = VDDIO 28 50 80
IOZ
Output current, pullup or pulldown
disabled VO = VDDIO or 0 V ±2 μA
CIInput capacitance 2 pF
VDDIO BOR trip point Falling VDDIO 2.42 2.65 3.135 V
VDDIO BOR hysteresis 35 mV
Supervisor reset release delay
time
Time after BOR/POR/OVR event is removed to XRS
release 400 800 μs
VREG VDD output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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I TEXAS INSTRUMENTS
8.7 Thermal Resistance Characteristics
8.7.1 PT Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 13.6 N/A
RΘJB Junction-to-board thermal resistance 30.6 N/A
RΘJA
(High k PCB) Junction-to-free air thermal resistance
64 0
50.4 150
48.2 250
45 500
PsiJT Junction-to-package top
0.56 0
0.94 150
1.1 250
1.38 500
PsiJB Junction-to-board
30.1 0
28.7 150
28.4 250
28 500
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
8.7.2 DA Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 12.8 N/A
RΘJB Junction-to-board thermal resistance 33 N/A
RΘJA
(High k PCB) Junction-to-free air thermal resistance
70.1 0
56.4 150
53.9 250
50.2 500
PsiJT Junction-to-package top
0.34 0
0.61 150
0.74 250
0.98 500
PsiJB Junction-to-board
32.5 0
32.1 150
31.7 250
31.1 500
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
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(2) lfm = linear feet per minute
8.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
8.9 JTAG Debug Probe Connection Without Signal Buffering for the MCU
Figure 8-3 shows the connection between the MCU and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 8-3 shows the simpler, no-
buffering situation. For the pullup/pulldown resistor values, see Section 7.2, Signal Descriptions.
TRST
TMS
TDI
TDO
TCK
VDDIO
MCU
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
TCK_RET
13
14
2
1
3
7
11
9
6 inches or less
PD
GND
GND
GND
GND
GND
5
4
6
8
10
12
JTAG Header
VDDIO
A. See Figure 9-39 for JTAG/GPIO multiplexing.
Figure 8-3. JTAG Debug Probe Connection Without Signal Buffering for the MCU
Note
The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard,
the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS II
8.10 Parameter Information
8.10.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don't care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
8.10.2 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
8.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 8-4. 3.3-V Test Load Circuit
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS eeeeeeeeeeeeeeeeee
8.12 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to
prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No
voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this
value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an unpowered device can
bias internal p-n junctions in unintended ways and produce unpredictable results.
tw(RSL1)
th(boot-mode)(C)
V V
(3.3 V)
DDIO DDA
,
INTOSC1
X1/X2
XRS(D)
Boot-Mode
Pins
V (1.8 V)
DD
XCLKOUT
I/O Pins
User-code dependent
User-code dependent
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code
GPIO pins as input
GPIO pins as input (state depends on internal PU/PD)
(E)
tOSCST
User-code dependent
Address/Data/
Control
(Internal)
Address/data valid, internal boot-ROM code execution phase
User-code execution phase
td(EX)
tINTOSCST
(A)
(B)
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,
SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the
pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup/pulldown will take effect when BOR is driven high.
Figure 8-5. Power-on Reset
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS K i (L { { { ( $393‘3’3‘3‘3‘3‘3’3‘3’3‘9‘3‘3’3‘o Q‘93‘OAA‘QAAAAOA‘AOAO
8.12.1 Reset ( XRS) Timing Requirements
MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles
tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles
8.12.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven by device 600 μs
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog 512tc(OSCCLK) cycles
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tINTOSCST Start-up time, internal zero-pin oscillator 3 μs
tOSCST (1) On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
th(boot-mode)(A)
tw(RSL2)
INTOSC1
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/OPins
Address/Data/
Control
(Internal)
Boot-ROMExecutionStarts
User-CodeExecutionStarts
User-CodeDependent
User-CodeExecutionPhase
User-CodeDependent
User-CodeExecution
Peripheral/GPIOFunction
User-CodeDependent
GPIOPinsasInput(StateDependsonInternalPU/PD)
GPIOPinsasInput Peripheral/GPIOFunction
td(EX)
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 8-6. Warm Reset
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS T T
Figure 8-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK
SYSCLKOUT
WritetoPLLCR
OSCCLK*2
(CurrentCPU
Frequency)
OSCCLK/2
(CPUfrequencywhilePLL isstabilizing
withthedesiredfrequency.Thisperiod
(PLL lock-uptimet )is1mslong.)
p
OSCCLK*4
(ChangedCPUfrequency)
Figure 8-7. Example of Effect of Writing Into PLLCR Register
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
8.13 Clock Specifications
8.13.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2802x MCUs. Section 8.13.1.1, Section 8.13.1.2, and Section 8.13.1.3 list the cycle times of
various clocks.
8.13.1.1 2802x Clock Table and Nomenclature (40-MHz Devices)
MIN NOM MAX UNIT
SYSCLKOUT tc(SCO), Cycle time 25 500 ns
Frequency 2 40 MHz
LSPCLK(1) tc(LCO), Cycle time 25 100(2) ns
Frequency 10(2) 40 MHz
ADC clock tc(ADCCLK), Cycle time 25 ns
Frequency 40 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 40 MHz.
8.13.1.2 2802x Clock Table and Nomenclature (50-MHz Devices)
MIN NOM MAX UNIT
SYSCLKOUT tc(SCO), Cycle time 20 500 ns
Frequency 2 50 MHz
LSPCLK(1) tc(LCO), Cycle time 20 80(2) ns
Frequency 12.5(2) 50 MHz
ADC clock tc(ADCCLK), Cycle time 20 ns
Frequency 50 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 50 MHz.
8.13.1.3 2802x Clock Table and Nomenclature (60-MHz Devices)
MIN NOM MAX UNIT
SYSCLKOUT tc(SCO), Cycle time 16.67 500 ns
Frequency 2 60 MHz
LSPCLK(1) tc(LCO), Cycle time 16.67 66.67(2) ns
Frequency 15(2) 60 MHz
ADC clock tc(ADCCLK), Cycle time 16.67 ns
Frequency 60 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 60 MHz.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
8.13.1.4 Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
tc(OSC), Cycle time 50 200 ns
Frequency 5 20 MHz
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
tc(CI), Cycle time (C8) 33.3 200 ns
Frequency 5 30 MHz
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
tc(CI), Cycle time (C8) 33.33 250 ns
Frequency 4 30 MHz
Limp mode SYSCLKOUT
(with /2 enabled) Frequency range 1 to 5 MHz
XCLKOUT tc(XCO), Cycle time (C1) 66.67 2000 ns
Frequency 0.5 15 MHz
PLL lock time(1) tp1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
8.13.1.5 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
PARAMETER MIN TYP MAX UNIT
Internal zero-pin oscillator 1 (INTOSC1)(1) (2) Frequency 10 MHz
Internal zero-pin oscillator 2 (INTOSC2)(1) (2) Frequency 10 MHz
Step size (coarse trim) 55 kHz
Step size (fine trim) 14 kHz
Temperature drift(3) 3.03 4.85 kHz/°C
Voltage (VDD) drift(3) 175 Hz/mV
(1) Oscillator frequency will vary over temperature, see Figure 8-8. To compensate for oscillator temperature drift, see the Oscillator
Compensation Guide and C2000Ware.
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
• Increase in temperature will cause the output frequency to increase per the temperature coefficient.
• Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
9.6
9.7
9.8
9.9
10
10.1
10.2
10.3
10.4
10.5
10.6
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (°C)
Output Frequency (MHz)
Typical
Max
Figure 8-8. Zero-Pin Oscillator Frequency Movement With Temperature
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
w TEXAS INSTRUMENTS #\ #\\\ H‘ fi“ l\\\\ #\\\
8.13.2 Clock Requirements and Characteristics
8.13.2.1 XCLKIN Timing Requirements – PLL Enabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN 6 ns
C10 tr(CI) Rise time, XCLKIN 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45% 55%
8.13.2.2 XCLKIN Timing Requirements – PLL Disabled
NO. MIN MAX UNIT
C9 tf(Cl) Fall time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C11 tw(CIL)
Pulse duration, XCLKIN low as a percentage of
tc(OSCCLK)
45% 55%
C12 tw(CIH)
Pulse duration, XCLKIN high as a percentage of
tc(OSCCLK)
45% 55%
The possible configuration modes are shown in Table 9-16.
8.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)(1) (2)
NO. PARAMETER MIN MAX UNIT
C3 tf(XCO) Fall time, XCLKOUT 11 ns
C4 tr(XCO) Rise time, XCLKOUT 11 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
C4
C3
XCLKOUT(B)
XCLKIN(A)
C5
C9
C10
C1
C8
C6
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 8-9. Clock Timing
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
8.14 Flash Timing
8.14.1 Flash/OTP Endurance for T Temperature Material
ERASE/PROGRAM
TEMPERATURE(1) MIN TYP MAX UNIT
NfFlash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.2 Flash/OTP Endurance for S Temperature Material
ERASE/PROGRAM
TEMPERATURE(1) MIN TYP MAX UNIT
NfFlash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.3 Flash/OTP Endurance for Q Temperature Material
ERASE/PROGRAM
TEMPERATURE(1) MIN TYP MAX UNIT
NfFlash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) –40°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.4 Flash Parameters at 60-MHz SYSCLKOUT
PARAMETER TEST
CONDITIONS MIN TYP MAX UNIT
IDDP (1) VDD current consumption during Erase/Program cycle VREG
disabled
80 mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle 60 mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle VREG
enabled
120 mA
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
8.14.5 Flash Parameters at 50-MHz SYSCLKOUT
PARAMETER TEST
CONDITIONS MIN TYP MAX UNIT
IDDP (1) VDD current consumption during Erase/Program cycle VREG disabled 70 mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle 60
IDDIOP (1) VDDIO current consumption during Erase/Program cycle VREG enabled 110 mA
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
8.14.6 Flash Parameters at 40-MHz SYSCLKOUT
PARAMETER TEST
CONDITIONS MIN TYP MAX UNIT
IDDP (1) VDD current consumption during Erase/Program cycle VREG disabled 60 mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle 60
IDDIOP (1) VDDIO current consumption during Erase/Program cycle VREG enabled 100 mA
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
8.14.7 Flash Program/Erase Time
PARAMETER TEST
CONDITIONS MIN TYP MAX(2) UNIT
Program Time(1) 8K Sector 250 2000 ms
4K Sector 125 2000 ms
16-Bit Word 50 μs
Erase Time(3) 8K Sector 2 12 s
4K Sector 2 12 s
(1) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
• the code that uses flash API to program the flash
• the Flash API itself
• Flash data to be programmed
(2) Maximum flash parameter mentioned are for the first 100 program and erase cycles.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
8.14.8 Flash/OTP Access Timing
PARAMETER MIN MAX UNIT
ta(fp) Paged Flash access time 40 ns
ta(fr) Random Flash access time 40 ns
ta(OTP) OTP access time 60 ns
8.14.9 Flash Data Retention Duration
PARAMETER TEST CONDITIONS MIN MAX UNIT
tretention Data retention duration TJ = 55°C 15 years
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 8-2. Minimum Required Flash/OTP Wait States at Different Frequencies
SYSCLKOUT
(MHz)
SYSCLKOUT
(ns)
PAGE
WAIT STATE(1)
RANDOM
WAIT STATE(1)
OTP
WAIT STATE
60 16.67 2 2 3
55 18.18 2 2 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
25 40 0 1 1
(1) Random wait state must be ≥ 1.
The equations to compute the Flash page wait state and random wait state in Table 8-2 are as follows:
integerhighestnextthetoupround1StateWaitPageFlash
)(
)(
ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=·
t
t
SCOc
pfa
largeriswhichever1,orinteger,highestnextthetoupround1StateWaitRandomFlash ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=×
t
t
c(SCO)
r)a(f
The equation to compute the OTP wait state in Table 8-2 is as follows:
largeriswhichever1,orinteger,highestnextthetoupround1StateWaitOTP ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=
t
t
c(SCO)
a(OTP)
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9 Detailed Description
9.1 Overview
9.1.1 CPU
The 2802x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based
controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++
engine, enabling users to develop not only their system control software in a high-level language, but also
enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at
system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a
second processor in many systems. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to
handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic
context save of critical registers, resulting in a device that is capable of servicing many asynchronous events
with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This
pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
9.1.2 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.
The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist of
32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations. The
multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data
value and write a data value in a single cycle. All peripherals and memories attached to the memory bus
prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)
9.1.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices
adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various
buses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32
data lines and associated control signals. Three versions of the peripheral bus are supported. One version
supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit
accesses (called peripheral frame 1).
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.4 Real-Time JTAG and Analysis
The devices implement the standard IEEE 1149.1 JTAG 1interface for in-circuit based debug. Additionally, the
devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and
register locations while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time-critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to
the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that
allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable
break events when a match occurs. These devices do not support boundary scan; however, IDCODE and
BYPASS features are available if the following considerations are taken into account. The IDCODE does not
come by default. The user must go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the
IDCODE. For BYPASS instruction, the first shifted DR value would be 1.
9.1.5 Flash
The F280200 device contains 8K × 16 of embedded flash memory, segregated into two 4K × 16 sectors. The
F28021/23/27 devices contain 32K × 16 of embedded flash memory, segregated into four 8K × 16 sectors. The
F28020/22/26 devices contain 16K × 16 of embedded flash memory, segregated into four 4K × 16 sectors. All
devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BFF. The user can
individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors.
Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP
is mapped to both program and data space; therefore, it can be used to execute code or store data information.
Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data variables and should not contain program code.
Note
The Flash and OTP wait states can be configured by the application. This allows applications running
at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait state, and OTP wait-state registers, see the
System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual .
9.1.6 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer points to
the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are
mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data
variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the
programmer. This makes for easier programming in high-level languages.
9.1.7 L0 SARAM
The device contains up to 4K × 16 of single-access RAM. Refer to the device-specific memory map figures in
Section 9.2 to ascertain the exact size for a given device. This block is mapped to both program and data space.
1IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.8 Boot ROM
The Boot ROM is factory-programmed with bootloader software. The Boot ROM uses the boot-mode-select
GPIO pins to determine what boot mode to use upon power up. The user can select to boot normally to
application code, to download new software from an external connection, or to select boot software that is
programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS
waveforms, for use in math-related algorithms. The boot-ROM content, and hence the checksum value, may
vary for different silicon revisions. For details, see the Boot ROM chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
Table 9-1. Boot Mode Selection
MODE GPIO37/TDO GPIO34/COMP2OUT TRST MODE
3 1 1 0 GetMode
2 1 0 0 Wait (see Section 9.1.9 for description)
1 0 1 0 SCI
0 0 0 0 Parallel IO
EMU x x 1 Emulation Boot
9.1.8.1 Emulation Boot
When the JTAG debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that a JTAG debug probe is connected and uses the contents of two reserved
SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
9.1.8.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot
option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash
is used. One of the following loaders can be specified: SCI, SPI, I2C, or OTP.
9.1.8.3 Peripheral Pins Used by the Bootloader
Table 9-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if
these conflict with any of the peripherals you would like to use in your application.
Table 9-2. Peripheral Bootload Pins
BOOTLOADER PERIPHERAL LOADER PINS
SCI SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot Data (GPIO[7:0])
28x Control (GPIO16)
Host Control (GPIO12)
SPI SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C SDAA (GPIO32)(1)
SCLA (GPIO33)(1)
(1) GPIO pins 32 and 33 may not be available on your device package. On these devices, this
bootload option is unavailable.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.9 Security
The devices support high levels of security to protect the user firmware from being reverse engineered. The
security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One
code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature
prevents unauthorized users from examining the memory contents through the JTAG port or trying to boot-load
some undesirable software that would export the secure memory contents. To enable access to the secure
blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password
locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized
users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the
JTAG debug probe is connected will trip the ECSL and break the debug probe connection. To allow debug of
secure code, while maintaining the CSM protection against secure memory reads, the user must write the
correct value into the lower 64 bits of the KEY register (KEY0 - KEY3), which matches the value stored in the
lower 64 bits of the password locations (PWL0 - PWL3) within the flash. Dummy reads of all 128 bits of the
password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match. During debug of secure code, operations like
single-stepping is possible. However, the actual contents of the secure memory cannot be seen in the CCS
window.
When power is applied to a secure device that is connected to a JTAG debug probe, the CPU will start executing
and may execute an instruction that performs an access to a protected area. If this happens, the ECSL will trip
and cause the JTAG circuitry to be deactivated. Under this condition, a host (such as a computer running CCS or
flash programing software) would not be able to establish connection with the device.
The solution is to use the Wait boot option. In this mode, the device loops around a software breakpoint to allow
a JTAG debug probe to be connected without tripping security. The user can then exit this mode once the JTAG
debug probe is connected by using one of the emulation boot options as described in the Boot ROM chapter in
the TMS320F2802x,TMS320F2802xx Technical Reference Manual. These devices do not support a hardware
wait-in-reset mode.
Note
• When the code-security passwords are programmed, all addresses from 0x3F7F80 to 0x3F7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If reprogramming of a secure device via JTAG may be needed in future, it is important to design
the board in such a way that the device could be put in Wait boot mode upon power-up (when
reprogramming is warranted). Otherwise, ECSL may deactivate the JTAG circuitry and prevent
connection to the device, as mentioned earlier. If reconfiguring the device for Wait boot mode in the
field is not practical, some mechanism must be implemented in the firmware to detect when a
firmware update is warranted. Code could then branch to the desired bootloader in the bootROM. It
could also branch to the Wait bootmode, at which point the JTAG debug probe could be connected,
device unsecured and programming accomplished through JTAG itself.
• If the code security feature is not used, addresses 0x3F7F80 to 0x3F7FEF may be used for code
or data. Addresses 0x3F7FF0 to 0x3F7FF5 are reserved for data and should not contain program
code.
The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros. Doing so
would permanently lock the device.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Note
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
9.1.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to
interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled/disabled within the PIE block.
9.1.11 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for
negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the
external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins.
9.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal
attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to 12 input-clock-
scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on
operating frequency if lower power operation is desired. Refer to Section 8, Electrical Specifications, for timing
details. The PLL block can be set in bypass mode.
9.1.13 Watchdog
Each device contains two watchdogs: CPU watchdog that monitors the core and NMI watchdog that is a missing
clock-detect circuit. The user software must regularly reset the CPU watchdog counter within a certain time
frame; otherwise, the CPU watchdog generates a reset to the processor. The CPU watchdog can be disabled if
necessary. The NMI watchdog engages only in case of a clock failure and can either generate an interrupt or a
device reset.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to
the CPU clock.
9.1.15 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
must function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer
will wake the processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
HALT: This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the
internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep
these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU watchdog in this mode. If the on-chip crystal oscillator is used as
the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU
watchdog can wake the device from this mode.
The CPU clock (OSCCLK) and watchdog clock source should be from the same clock source before attempting
to put the device into HALT or STANDBY.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.16 Peripheral Frames 0, 1, 2 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Waitstate Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers
PF1: GPIO: GPIO MUX Configuration and Control Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
eCAP: Enhanced Capture Module and Registers
Comparators: Comparator Modules
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
9.1.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables
the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured
as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific
inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.
The GPIO signals can also be used to bring the device out of specific low-power modes.
9.1.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can
be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to INT14 of the CPU.
If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLKOUT (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• External clock source
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.1.19 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-
band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins
support the HRPWM high resolution duty and period features. The type 1 module found on 2802x devices
also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced
triggering including trip functions based on comparator outputs.
eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
ADC: The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned out, depending on the
device. It contains two sample-and-hold units for simultaneous sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit reference for
supplying one input of the comparator.
9.1.20 Serial Port Peripherals
The devices support the following serial communication peripherals:
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used
for communications between the MCU and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and
ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI contains
a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The
SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant
with Philips Semiconductors Inter-IC bus ( I2C-bus®) specification version 2.1 and connected by way of an
I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from
the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt
servicing overhead.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
9.2 Memory Maps
In Figure 9-1, Figure 9-2, Figure 9-3, Figure 9-4, and Figure 9-5, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory
only. A user program cannot access these memory maps in program space.
•Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D7C80 to 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K 16, 0-Wait)´
M1 SARAM (1K 16, 0-Wait)´
0x00 0000
0x00 0040
0x00 0400
Data Space Prog Space
Reserved
Reserved
User OTP (1K 16, Secure Zone + ECSL)´
Reserved
0x00 9000
0x3D 7800
0x3D 7C00
Reserved
FLASH
(32K 16, 4 Sectors, Secure Zone + ECSL)´
128-Bit Password
L0 SARAM (4K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
Reserved
Boot ROM (8K 16, 0-Wait)´
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 8000
0x3F 0000
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Peripheral Frame 1
(4K 16, Protected)´
Peripheral Frame 2
(4K 16, Protected)´
L0 SARAM (4K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
0x00 2000
0x00 6000
0x00 7000
0x00 8000
Reserved
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 0E00
0x00 0D00 PIE Vector - RAM
(256 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
´
0x3D 7C80 Calibration Data
0x3D 7CC0 Get_mode function
0x3D 7CE0 Reserved
0x3D 7FFF PARTID
0x3D 7EB0 Reserved
0x3D 7E80 Calibration Data
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
Figure 9-1. 28023-Q1/28027-Q1 Memory Map
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K 16, 0-Wait)´
M1 SARAM (1K 16, 0-Wait)´
0x00 0000
0x00 0040
0x00 0400
Data Space Prog Space
Reserved
Reserved
User OTP (1K 16, Secure Zone + ECSL)´
Reserved
0x00 9000
0x3D 7800
0x3D 7C00
Reserved
FLASH
(16K 16, 4 Sectors, Secure Zone + ECSL)´
128-Bit Password
L0 SARAM (4K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
Reserved
Boot ROM (8K 16, 0-Wait)´
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 8000
0x3F 4000
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Peripheral Frame 1
(4K 16, Protected)´
Peripheral Frame 2
(4K 16, Protected)´
L0 SARAM (4K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
0x00 2000
0x00 6000
0x00 7000
0x00 8000
Reserved
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 0E00
0x00 0D00 PIE Vector - RAM
(256 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
´
0x3D 7C80 Calibration Data
0x3D 7CC0 Get_mode function
0x3D 7CE0 Reserved
0x3D 7FFF PARTID
0x3D 7EB0 Reserved
0x3D 7E80 Calibration Data
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
Figure 9-2. 28022-Q1/28026-Q1 Memory Map
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 45
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K 16, 0-Wait)´
M1 SARAM (1K 16, 0-Wait)´
0x00 0000
0x00 0040
0x00 0400
Data Space Prog Space
Reserved
User OTP (1K 16, Secure Zone + ECSL)´
Reserved
0x00 8C00
0x3D 7800
0x3D 7C00
Reserved
FLASH
(32K 16, 4 Sectors, Secure Zone + ECSL)´
128-Bit Password
L0 SARAM (3K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
Reserved
Boot ROM (8K 16, 0-Wait)´
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 8000
0x3F 0000
0x3F 7FF8
0x3F 8000
0x3F 8C00
0x3F E000
0x3F FFC0
Reserved
Peripheral Frame 1
(4K 16, Protected)´
Peripheral Frame 2
(4K 16, Protected)´
L0 SARAM (3K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
0x00 2000
0x00 6000
0x00 7000
0x00 8000
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 0E00
0x00 0D00 PIE Vector - RAM
(256 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
´
0x3D 7C80 Calibration Data
0x3D 7CC0 Get_mode function
0x3D 7CE0 Reserved
0x3D 7FFF PARTID
Reserved
Reserved
0x3D 7EB0 Reserved
0x3D 7E80 Calibration Data
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
Figure 9-3. 28021 Memory Map
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K 16, 0-Wait)´
M1 SARAM (1K 16, 0-Wait)´
0x00 0000
0x00 0040
0x00 0400
Data Space Prog Space
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 0E00
0x00 0D00
Reserved
Reserved
User OTP (1K 16, Secure Zone + ECSL)´
Reserved
0x00 8400
0x3D 7800
0x3D 7C00
Reserved
FLASH
(16K 16, 4 Sectors, Secure Zone + ECSL)´
128-Bit Password
L0 SARAM (1K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
Reserved
Boot ROM (8K 16, 0-Wait)´
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 8000
0x3F 4000
0x3F 7FF8
0x3F 8000
0x3F 8400
0x3F E000
0x3F FFC0
Reserved
Peripheral Frame 1
(4K 16, Protected)´
Peripheral Frame 2
(4K 16, Protected)´
L0 SARAM (1K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
0x00 2000
0x00 6000
0x00 7000
0x00 8000
Reserved
PIE Vector - RAM
(256 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
´
0x3D 7C80 Calibration Data
0x3D 7CC0 Get_mode function
0x3D 7CE0 Reserved
0x3D 7FFF PARTID
0x3D 7EB0 Reserved
0x3D 7E80 Calibration Data
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
Figure 9-4. 28020 Memory Map
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 47
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K 16, 0-Wait)´
M1 SARAM (1K 16, 0-Wait)´
0x00 0000
0x00 0040
0x00 0400
Data Space Prog Space
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 0E00
0x00 0D00
Reserved
Reserved
L0 SARAM (1K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
User OTP (1K 16, Secure Zone + ECSL)´
Reserved
0x00 8400
0x3D 7800
0x3D 7C00
Reserved
FLASH
(8K 16, 2 Sectors, Secure Zone + ECSL)´
128-Bit Password
Reserved
Boot ROM (8K 16, 0-Wait)´
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 8000
0x3F 6000
0x3F 7FF8
0x3F 8000
0x3F 8400
0x3F E000
0x3F FFC0
Reserved
Peripheral Frame 1
(4K 16, Protected)´
Peripheral Frame 2
(4K 16, Protected)´
0x00 2000
0x00 6000
0x00 7000
0x00 8000
Reserved
PIE Vector - RAM
(256 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
´
0x3D 7C80 Calibration Data
0x3D 7CC0 Get_mode function
0x3D 7CE0 Reserved
0x3D 7EB0 Reserved
0x3D 7E80 Calibration Data
0x3D 7FFF PARTID
L0 SARAM (1K 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
´
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
Figure 9-5. 280200 Memory Map
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 9-3. Addresses of Flash Sectors in F28021/28023-Q1/28027-Q1
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 0000 to 0x3F 1FFF Sector D (8K × 16)
0x3F 2000 to 0x3F 3FFF Sector C (8K × 16)
0x3F 4000 to 0x3F 5FFF Sector B (8K × 16)
0x3F 6000 to 0x3F 7F7F Sector A (8K × 16)
0x3F 7F80 to 0x3F 7FF5 Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 to 0x3F 7FF7 Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 to 0x3F 7FFF Security Password (128-Bit)
(Do not program to all zeros)
Table 9-4. Addresses of Flash Sectors in F28020/28022-Q1/28026-Q1
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 4000 to 0x3F 4FFF Sector D (4K × 16)
0x3F 5000 to 0x3F 5FFF Sector C (4K × 16)
0x3F 6000 to 0x3F 6FFF Sector B (4K × 16)
0x3F 7000 to 0x3F 7F7F Sector A (4K × 16)
0x3F 7F80 to 0x3F 7FF5 Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 to 0x3F 7FF7 Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 to 0x3F 7FFF Security Password (128-Bit)
(Do not program to all zeros)
Table 9-5. Addresses of Flash Sectors in F280200
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 6000 to 0x3F 6FFF Sector B (4K × 16)
0x3F 7000 to 0x3F 7F7F Sector A (4K × 16)
0x3F 7F80 to 0x3F 7FF5 Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 to 0x3F 7FF7 Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 to 0x3F 7FFF Security Password (128-Bit)
(Do not program to all zeros)
Note
• When the code-security passwords are programmed, all addresses from 0x3F 7F80 to 0x3F 7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be used for code
or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and should not contain program
code.
Table 9-6 shows how to handle these memory locations.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 9-6. Impact of Using the Code Security Module
ADDRESS FLASH
CODE SECURITY ENABLED CODE SECURITY DISABLED
0x3F 7F80 to 0x3F 7FEF Fill with 0x0000 Application code and data
0x3F 7FF0 to 0x3F 7FF5 Reserved for data only
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written.
Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in
reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where
the user expected the write to occur first (as written). The CPU supports a block protection mode where a region
of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align
the operations). This mode is programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 9-7 .
Table 9-7. Wait States
AREA WAIT STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
L0 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed through the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed through the Flash registers.
0-wait Paged min
1-wait Random min
Random ≥ Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
9.3 Register Maps
The devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 9-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 9-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 9-10.
Table 9-8. Peripheral Frame 0 Registers
NAME(1) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2)
Device Emulation Registers 0x00 0880 to 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 to 0x00 0987 3 Yes
FLASH Registers(3) 0x00 0A80 to 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 to 0x00 0AEF 16 Yes
ADC registers (0 wait read only) 0x00 0B00 to 0x00 0B0F 16 No
CPU–TIMER0/1/2 Registers 0x00 0C00 to 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 to 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 to 0x00 0DFF 256 No
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 9-9. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
Comparator 1 registers 0x00 6400 to 0x00 641F 32 (1)
Comparator 2 registers 0x00 6420 to 0x00 643F 32 (1)
ePWM1 + HRPWM1 registers 0x00 6800 to 0x00 683F 64 (1)
ePWM2 + HRPWM2 registers 0x00 6840 to 0x00 687F 64 (1)
ePWM3 + HRPWM3 registers 0x00 6880 to 0x00 68BF 64 (1)
ePWM4 + HRPWM4 registers 0x00 68C0 to 0x00 68FF 64 (1)
eCAP1 registers 0x00 6A00 to 0x00 6A1F 32 No
GPIO registers 0x00 6F80 to 0x00 6FFF 128 (1)
(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Technical Reference
Manual .
Table 9-10. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
System Control Registers 0x00 7010 to 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 to 0x00 704F 16 No
SCI-A Registers 0x00 7050 to 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 to 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 to 0x00 707F 16 Yes
ADC Registers 0x00 7100 to 0x00 717F 128 (1)
I2C-A Registers 0x00 7900 to 0x00 793F 64 (1)
(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Technical Reference
Manual .
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 9-11 .
Table 9-11. Device Emulation Registers
NAME ADDRESS
RANGE SIZE (x16) DESCRIPTION EALLOW
PROTECTED
DEVICECNF 0x0880
0x0881 2 Device Configuration Register Yes
PARTID 0x3D 7FFF 1 Part ID Register TMS320F280200PT 0x00C1
No
TMS320F280200DA 0x00C0
TMS320F28027PT 0x00CF
TMS320F28027DA 0x00CE
TMS320F28027FPT 0x00CF
TMS320F28027FDA 0x00CE
TMS320F28026PT 0x00C7
TMS320F28026DA 0x00C6
TMS320F28026FPT 0x00C7
TMS320F28026FDA 0x00C6
TMS320F28023PT 0x00CD
TMS320F28023DA 0x00CC
TMS320F28022PT 0x00C5
TMS320F28022DA 0x00C4
TMS320F28021PT 0x00CB
TMS320F28021DA 0x00CA
TMS320F28020PT 0x00C3
TMS320F28020DA 0x00C2
CLASSID 0x0882 1 Class ID Register TMS320F280200PT/DA 0x00C7
No
TMS320F28027PT/DA 0x00CF
TMS320F28027FPT/DA 0x00CF
TMS320F28026PT/DA 0x00C7
TMS320F28026FPT/DA 0x00C7
TMS320F28023PT/DA 0x00CF
TMS320F28022PT/DA 0x00C7
TMS320F28021PT/DA 0x00CF
TMS320F28020PT/DA 0x00C7
REVID 0x0883 1 Revision ID
Register
0x0000 - Silicon Rev. 0 - TMS
No
0x0001 - Silicon Rev. A - TMS
0x0002 - Silicon Rev. B - TMS
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.5 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage
regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a
second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out
reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
9.5.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are
required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate
the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the
application.
9.5.1.1 Using the On-chip VREG
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating
voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic
will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper
regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. Driving an
external load with the internal VREG is not supported.
9.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
fl TEXAS INSTRUMENTS
9.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden
of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a
clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point
than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is
present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on
VDDIO at all times, and on VDD when the internal VREG is enabled ( VREGENZ pin is tied low). Both functions tie
the XRS pin low when one of the voltages is below their respective trip point. VDD BOR and overvoltage trip
points are outside of the recommended operating voltages. Proper device operation cannot be ensured. If
overvoltage or undervoltage conditions affecting the system is a concern for an application, an external voltage
supervisor should be added. Figure 9-6 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO
BOR functions, a bit is provided in the BORCFG register. For details, see the System Control chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
I/O Pin
In
Out
DIR (0 = Input, 1 = Output)
(Force Hi-Z When High)
SYSRS
C28
Core
Sync RS
PLL
+
Clocking
Logic
MCLKRS
VREGHALT
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
POR/BOR
Generating
Module
XRS
Pin
SYSCLKOUT
WDRST(A)
JTAG
TCK
Detect
Logic
PBRS(B)
Internal
Weak PU
Deglitch
Filter
WDRST
A. WDRST is the reset signal from the CPU watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 9-6. VREG + POR + BOR + Reset Signal Connectivity
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.6 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power modes.
Table 9-12. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low-Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
(1) All registers in this table are EALLOW protected.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Figure 9-7 shows the various clock domains that are discussed. Figure 9-8 shows the various clock sources
(both internal and external) that can provide a clock for device operation.
Peripheral
Registers
SPI-A,SCI-A
I/O PF2
ClockEnables
ClockEnables
PCLKCR0/1/3
(SystemCtrlRegs)
LOSPCP
(SystemCtrlRegs)
LSPCLK
SYSCLKOUT
Peripheral
Registers
eCAP1
I/O PF1
ClockEnables
ClockEnables
Peripheral
Registers
ePWM1/.../4
I/O PF1
ClockEnables
ClockEnables
Peripheral
Registers
I2C-A
I/O PF2
ClockEnables
ClockEnables
ADC
Registers
12-Bit ADC
16Ch PF2
ClockEnables
PF0
ClockEnables
COMP
Registers
COMP1/2
PF1
ClockEnables
6
GPIO
Mux
Analog
GPIO
Mux
C28xCore CLKIN
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
Figure 9-7. Clock and Reset Domains
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS ("7 CLKCTLMDCLKSRCSEL] Intemal o i (A, osc1 oscmx 1 INToscnRIM Reg 110 my oschKsnc1 \—> CPU Watchdog (05mm on XRS reset) fuse: ‘ CLKCTLllNYOSmOFF] 1 = Tum use on CLKCTLUNTOSC1HALT] :7" CLKCTL[OSCELKSRCSEL] WAKEosc 3 1 = \gnvre HALY 3 m Internal OSCZCLK n ‘ INTOSCZYRIM Reg use 1 osccm PLL ‘5) [10 MHz) “35515“ a" st use.) Missmgcluck-netut Eircml OTCE CLKCTL[TRMZCLKPRESCALE] i CLKCTL[TMRZCLKSRCSEL] 1 = Tum osc on 3 j. cmcmwwsczom New” svm: § H. mm, a Edge » 1 , l8,l16 Deled n1. 1:), 11 1 \gnare HALT 1 D1 CPUTMRZCLK * ' on CLKCTLUNTOSC2HAL1] - { osccmsncz SVSCLKWT o i 0 = GPIDJB L," CLKCTL[OSCCLKSRCZSEL] XCLK[XCLKINSEL] 1: 6mm CLKCTL[XCLKINOFF] 04> 3 XCLKIN (mow J 4. o! GPIOSB XELKIN H» EXTCLK 1mm” XML :I 050 WWW: x1 {Oscwllators enabled whan (ms swgnal is high] a = 050 on {delault on reset) CLKCTLlXTALOSCOFF] 1 = Tum use 0"
A. Register loaded from TI OTP-based calibration function.
B. See Section 9.6.4 for details on missing clock detection.
Figure 9-8. Clock Tree
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.6.1 Internal Zero Pin Oscillators
The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are turned
on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused
oscillators may be powered down by the user. The center frequency of these oscillators is determined by their
respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See
Section 8, Electrical Specifications, for more information on these oscillators.
9.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals
applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to
the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with
X2 and a crystal.
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table
9-13. Furthermore, ESR range = 30 to 150 Ω.
Table 9-13. Typical Specifications for External Quartz Crystal (1)
FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF)
5 2200 18 18
10 470 15 15
15 0 15 15
20 0 12 12
(1) Cshunt should be less than or equal to 5 pF.
X2X1
Crystal
XCLKIN/GPIO19/38
Turn off
XCLKIN path
in CLKCTL
register
Rd
CL1 CL2
A. X1/X2 pins are available in 48-pin package only.
Figure 9-9. Using the On-chip Crystal Oscillator
Note
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and
crystal. The value is usually approximately twice the value of the crystal's load capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the operation of
their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to
tune the tank circuit. The vendor can also advise the customer regarding the proper tank
component values that will produce proper start-up and stability over the entire operating range.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS fl
ExternalClockSignal
(Toggling0−VDDIO)
XCLKIN/GPIO19/38 X2
NC
X1
Figure 9-10. Using a 3.3-V External Oscillator
9.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) is at least 50 MHz.
Table 9-14. PLL Settings
PLLCR[DIV] VALUE(2) (3) SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 0 or 1(1) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
0000 (PLL bypass) OSCCLK/4 (Default)(2) OSCCLK/2 OSCCLK
0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1
0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1
0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1
0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1
0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1
0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1
0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1
1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1
1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1
1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1
1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1
1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(3) This register is EALLOW protected. See the System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference
Manual for more information.
Table 9-15. CLKIN Divide Options
PLLSTS [DIVSEL] CLKIN DIVIDE
0 /4
1 /4
2 /2
3 /1
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
The PLL-based clock module provides four modes of operation:
•INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock
for the Watchdog block, core and CPU-Timer 2
•INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock
for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen
for the Watchdog block, core and CPU-Timer 2.
•Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/
resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2
pins. Some devices may not have the X1/X2 pins. See Section 7.2.1 for details.
•External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be
bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. The
XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or
GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input
(forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable
at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock
source must be disabled (using the CLKCTL register) before switching clocks.
Table 9-16. Possible PLL Configuration Modes
PLL MODE REMARKS PLLSTS[DIVSEL] CLKIN AND
SYSCLKOUT
PLL Off
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low-
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Enable Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
3
OSCCLK * n/4
OSCCLK * n/2
OSCCLK * n/1
9.6.4 Loss of Input Clock (NMI Watchdog Function)
The 2802x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the
on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and
PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This
limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or
the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status
(MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and
initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a
shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 9-11 shows the interrupt mechanisms involved.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS fl
NMIFLG[NMINT]
1
0
Generate
Interrupt
Pulse
When
Input = 1
NMINT
Latch
Clear
Set Clear
NMIFLGCLR[NMINT]
XRS
0
NMICFG[CLOCKFAIL]
Latch
Clear
Set
Clear
XRS
NMIFLG[CLOCKFAIL]
NMI Watchdog
SYSCLKOUT
SYSRS
NMIRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
NMIFLGCLR[CLOCKFAIL]
SYNC?
NMIFLGFRC[CLOCKFAIL]
SYSCLKOUT
See System
Control Section
CLOCKFAIL
Figure 9-11. NMI Watchdog
9.6.5 CPU Watchdog Module
The CPU watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx devices. This
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user must disable the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter.
Figure 9-12 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU watchdog counter decrements to initiate a CPU watchdog
reset or WDINT interrupt. However, when the external input clock fails, the CPU watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock).
Note
The CPU watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all
28x devices.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully
charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from
getting fully charged. Such a circuit would also help in detecting failure of the flash memory.
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TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
ITEXAs INSTRUMENTS WDCR (wnpsp 0]) wow (wows) + WDCNTRU or OSCCLKSRU ur 2 Watchdog WDCLK arm [5‘2 Presca‘er V Wa|chdog Counter CLR scsmwoongRmE) C‘ear Cnunlar f \ntema‘ + F'uHuD WDKEVU n) 7 Generme WORST WWW :D * ow. Me WW 55 ‘ AA Good K ey (512 OSCCLKS) Key Detector x :7 m 41:} ‘7_) uh WDCR (wncHKp an WDRSTW )’ Bad WDCHK Key SCSR (WDEN‘NT)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 9-12. CPU Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the CPU watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can
wake the device from STANDBY (if enabled). See Section 9.7, Low-power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU watchdog can be used to wake up the device through a device reset.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.7 Low-power Modes Block
Table 9-17 summarizes the various modes.
Table 9-17. Low-power Modes
MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1)
IDLE 00 On On On XRS, CPU watchdog interrupt, any
enabled interrupt
STANDBY 01 On
(CPU watchdog still running) Off Off XRS, CPU watchdog interrupt, GPIO
Port A signal, debugger(2)
HALT(3) 1X
Off
(on-chip crystal oscillator and PLL
turned off, zero-pin oscillator and
CPU watchdog state dependent
on user code.)
Off Off XRS, GPIO Port A signal, debugger(2),
CPU watchdog
(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits
the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-
power mode will not be exited and the device will go back into the indicated low-power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block
performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode: CPU watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT
mode. The user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the System Control
chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual for more details.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.8 Interrupts
Figure 9-13 shows how the various interrupt sources are multiplexed.
CPU TIMER 2
CPU TIMER 0
Peripherals
(SPI, SCI, ePWM, I C, HRPWM, eCAP, ADC)
2
TINT0
XINT1
Interrupt Control
XINT1
XINT1CR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
GPIO
MUX
INT1
to
INT12
NMI
XINT1CTR(15:0)
XINT2CTR(15:0)
CPU TIMER 1
TINT2
MUX
XINT2
XINT3
ADC XINT2SOC
GPIOXINT1SEL(4:0)
GPIOXINT2SEL(4:0)
GPIOXINT3SEL(4:0)
Interrupt Control
XINT3
XINT3CR(15:0)
XINT3CTR(15:0)
NMI interrupt with watchdog function
(See the NMI Watchdog section.) NMIRS
System Control
(See the System
Control section.)
INT14
INT13
GPIO0.int
GPIO31.int
CLOCKFAIL
CPUTMR2CLK
C28
Core
MUX
MUX
TINT1
PIE
Up to 96 Interrupts
Watchdog
WDINT
Low-Power Modes
LPMINT
WAKEINT Sync
SYSCLKOUT
Figure 9-13. External and PIE Interrupt Sources
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS |NT1 V L ; INTZ L L _ I I I I I I I I —D I I I I |NT11 V V # |NT12 _ L V / 4 07A : INTx.1 ‘ C 4 4 INTX.2 : : INTX.3 7 ‘ C 4 4 INDIA 4 4 4 INTx.5 ‘ ‘ INTx.6 4 : |NTx.7 ‘ INTX.8
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. Table 9-18 shows the interrupts used by 2802x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. The TRAP #0 instruction attempts to transfer program control to the address pointed to by
the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, the TRAP #0
instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the interrupt
service routine corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction
fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.
INT12
MUX
INT11
INT2
INT1
CPU
(Enable)(Flag)
INTx
INTx.8
PIEIERx[8:1] PIEIFRx[8:1]
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals
or
External
Interrupts
(Enable) (Flag)
IER[12:1]IFR[12:1]
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
Figure 9-14. Multiplexing of Interrupts Using the PIE Block
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 9-18. PIE MUXed Peripheral Interrupt Vector Table
INTx.8(1) INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y Reserved Reserved Reserved Reserved EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
– – – – (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50
INT3.y Reserved Reserved Reserved Reserved EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
– – – – (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60
INT4.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT
– – – – – – – (eCAP1)
0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70
INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80
INT6.y Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA
– – – – – – (SPI-A) (SPI-A)
0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90
INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A
– – – – – – (I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA
– – – – – – (SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0
INT11.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved XINT3
– – – – – – – Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
a. No peripheral within the group is asserting interrupts.
b. No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 9-19. PIE Configuration and Control Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA –
0x0CFF
6 Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
W TEXAS INSTRUMENTS $ b Vvvvovv' tdohfitfitof‘
9.8.1 External Interrupts
Table 9-20. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT2CR 0x00 7071 1 XINT2 configuration register
XINT3CR 0x00 7072 1 XINT3 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control chapter in the TMS320F2802x,TMS320F2802xx
Technical Reference Manual .
9.8.1.1 External Interrupt Electrical Data/Timing
9.8.1.1.1 External Interrupt Timing Requirements
MIN(1) MAX UNIT
tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles
With qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
9.8.1.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN(1) MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
XINT1,XINT2,XINT3
tw(INT)
InterruptVector
td(INT)
Addressbus
(internal)
Figure 9-15. External Interrupt Timing
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS m m V—H—‘
9.9 Peripherals
9.9.1 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The
ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing
control of start of conversions. Figure 9-16 shows the interaction of the analog module with the rest of the
F2802x system.
For more information on the ADC, see the Analog-to-Digital Converter and Comparator chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
38-Pin 48-Pin
VDDA VDDA
VREFLO
Tied To
VSSA
VREFLO
Tied To
VSSA
VREFHI
Tied To
A0
VREFHI
Tied To
A0
A1
A2 A2
A3
A4 A4
A6 A6
A7
B1
B2 B2
B3
B4 B4
B6 B6
B7
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
Diff
Interface Reference
Comp1
VREFHI
A0
B0
AIO2
AIO10
A1
B1
10-Bit
DAC
A2
B2
COMP1OUT
A3
B3
Comp2
(See Note A)
AIO4
AIO12
10-Bit
DAC
A4
B4
COMP2OUT
ADC
B5
AIO6
AIO14
A6
B6
A7
B7
Simultaneous Sampling Channels
Signal Pinout
A5
Temperature Sensor
A. Comparator 2 is available only on the 48-pin PT package.
Figure 9-16. Analog Pin Configurations
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS \v REFHI
9.9.1.1 Analog-to-Digital Converter (ADC)
9.9.1.1.1 Features
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-and-
hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 13 analog
input channels. The converter can be configured to run with an internal band-gap reference to create true-
voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-
based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a series of
conversions from a single trigger. However, the basic principle of operation is centered around the configurations
of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
• 12-bit ADC core with built-in dual sample-and-hold (S/H)
• Simultaneous sampling or sequential sampling modes
• Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog
voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external
reference modes.)
0,ValueDigital =
V0inputwhen £
3.3
V
VoltageAnalogInput
4096ValueDigital REFLO
-
´=
V3.3inputV0when <<
4095,ValueDigital =
V3.3inputwhen ³
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when
using either internal or external reference modes.)
0,ValueDigital =
V0inputwhen £
VV
V
VoltageAnalogInput
4096ValueDigital
REFLOREFHI
REFLO
-
-
´=
V
inputV0when REFHI
<<
4095,ValueDigital =
V
inputwhen REFHI
³
• Up to 16-channel, multiplexed inputs
• 16 SOCs, configurable for trigger, sample window, and channel
• 16 result registers (individually addressable) to store conversion values
• Multiple trigger sources
– S/W – software immediate start
– ePWM 1–4
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
• 9 flexible PIE interrupts, can configure interrupt request after any conversion
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-21. ADC Configuration and Control Registers
REGISTER NAME ADDRESS SIZE
(x16)
EALLOW
PROTECTE
D
DESCRIPTION
ADCCTL1 0x7100 1 Yes Control 1 Register
ADCCTL2 0x7101 1 Yes Control 2 Register
ADCINTFLG 0x7104 1 No Interrupt Flag Register
ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register
ADCINTOVF 0x7106 1 No Interrupt Overflow Register
ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register
INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register
INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register
INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register
INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register
INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOCPRICTL 0x7110 1 Yes SOC Priority Control Register
ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register
ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels)
ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels)
ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels)
ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels)
ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels)
ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels)
ADCSOC0CTL to
ADCSOC15CTL
0x7120 –
0x712F
1 Yes SOC0 Control Register to SOC15 Control Register
ADCREFTRIM 0x7140 1 Yes Reference Trim Register
ADCOFFTRIM 0x7141 1 Yes Offset Trim Register
COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register
ADCREV 0x714F 1 No Revision Register
Table 9-22. ADC Result Registers (Mapped to PF0)
REGISTER NAME ADDRESS SIZE
(x16)
EALLOW
PROTECTED DESCRIPTION
ADCRESULT0 to ADCRESULT15 0xB00 to 0xB0F 1 No ADC Result 0 Register to ADC Result 15
Register
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
PF0(CPU)
PF2(CPU)
SYSCLKOUT
ADCENCLK
AIO
MUX
ADC
Channels
ADC
Core
12-Bit
0-Wait
Result
Registers
ADCINT1
ADCINT9
ADCTRIG1 TINT0
PIE
CPUTIMER0
ADCTRIG2 TINT1 CPUTIMER1
ADCTRIG3 TINT2 CPUTIMER2
ADCTRIG4 XINT2SOC XINT2
ADCTRIG5 SOCA 1
ePWM1
ADCTRIG6 SOCB1
ADCTRIG7 SOCA 2
ePWM2
ADCTRIG8 SOCB2
ADCTRIG9 SOCA 3
ePWM3
ADCTRIG10 SOCB3
ADCTRIG11 SOCA 4
ePWM4
ADCTRIG12 SOCB4
Figure 9-17. ADC Connections
ADC Connections if the ADC is Not Used
TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
• VDDA – Connect to VDDIO
• VSSA – Connect to VSS
• VREFLO – Connect to VSS
• ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSSA).
Note
Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to analog
ground. They should be grounded through a 1-kΩ resistor. This is to prevent an errant code from
configuring these pins as AIO outputs and driving grounded pins to a logic-high state.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS AD E
9.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
9.9.1.1.2.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO) cycles
ADCSOCAO
ADCSOCBO
or
tw(ADCSOCL)
Figure 9-18. ADCSOCAO or ADCSOCBO Timing
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
9.9.1.1.3.1 ADC Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 60-MHz device 0.001 60 MHz
Sample Window 28027/26/23/22 7 64 ADC
Clocks
28021/20/200 14 64
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz(1) –4 4 LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz,
no missing codes –1 1 LSB
Offset error (2) Executing Device_Cal
function –20 0 20
LSB
Executing periodic self-
recalibration(3) –4 0 4
Overall gain error with internal reference –60 60 LSB
Overall gain error with external reference –40 40 LSB
Channel-to-channel offset variation –4 4 LSB
Channel-to-channel gain variation –4 4 LSB
ADC temperature coefficient with internal reference –50 ppm/°C
ADC temperature coefficient with external reference –20 ppm/°C
VREFLO –100 µA
VREFHI 100 µA
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference VREFLO VREFHI V
VREFLO input voltage(4) VSSA VSSA V
VREFHI input voltage(5) with VREFLO = VSSA 1.98 VDDA V
Input capacitance 5 pF
Input leakage current ±5 μA
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be
performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset
Calibration" section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2802x,TMS320F2802xx Technical
Reference Manual .
(4) VREFLO is always connected to VSSA .
(5) VREFHI must not exceed VDDA when using either internal or external reference modes. Because VREFHI is tied to ADCINA0 , the input
signal on ADCINA0 must not exceed VDDA.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS \ com/emu" —‘—/—
9.9.1.1.3.2 ADC Power Modes
ADC OPERATING MODE CONDITIONS IDDA UNITS
Mode A – Operating Mode
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
13 mA
Mode B – Quick Wake Mode
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
4 mA
Mode C – Comparator-Only Mode
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
1.5 mA
Mode D – Off Mode
ADC Clock Enabled
Band gap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
0.075 mA
9.9.1.1.3.3 Internal Temperature Sensor
9.9.1.1.3.3.1 Temperature Sensor Coefficient
PARAMETER(1) MIN TYP MAX UNIT
TSLOPE Degrees C of temperature movement per measured ADC LSB change
of the temperature sensor 0.18(3) (2) °C/LSB
TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
(3) ADC temperature coeffieicient is accounted for in this specification
9.9.1.1.3.4 ADC Power-Up Control Bit Timing
9.9.1.1.3.4.1 ADC Power-Up Delays
PARAMETER(1) MIN MAX UNIT
td(PWD) Delay time for the ADC to be stable after power up 1 ms
(1) Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
Requestfor ADC
Conversion
td(PWD)
Figure 9-19. ADC Conversion Timing
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 75
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
ac
RsADCIN
C
5 pF
pC
1.6 pF
h
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (R ): 3.4 k
on W
Sampling Capacitor (C ): 1.6 pF
h
Parasitic Capacitance (C ): 5 pF
p
Source Resistance (R ): 50
sW
28x DSP
Source
Signal
3.4 kW
Ron
Figure 9-20. ADC Input Impedance Model
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS lflflflflflfl. fl: F in / kt EL
9.9.1.1.3.5 ADC Sequential and Simultaneous Timings
SOC0
ADCCLK
ADCRESULT 0
S/HWindowPulsetoCore
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
9 15 22 24 3720
Result 0 Latched
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
Conversion 0
13 ADCClocks
Minimum
7 ADCCLKs
6
ADCCLKs
Conversion 1
13 ADCClocks
Minimum
7 ADCCLKs
2 ADCCLKs
1 ADCCLK
AnalogInput
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
Figure 9-21. Timing Example for Sequential Mode / Late Interrupt Pulse
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
fl TEXAS INSTRUMENTS
Conversion 0
13 ADCClocks
Minimum
7 ADCCLKs
SOC0
ADCCLK
ADCRESULT 0
S/HWindowPulsetoCore
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
9 15 22 24 37
6
ADCCLKs
20
Result 0 Latched
Conversion 1
13 ADCClocks
Minimum
7 ADCCLKs
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
2 ADCCLKs
AnalogInput
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
Figure 9-22. Timing Example for Sequential Mode / Early Interrupt Pulse
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS Bl:
Conversion 0 (A)
13 ADCClocks
Minimum
7 ADCCLKs
SOC0 (A/B)
ADCCLK
ADCRESULT 0
S/HWindowPulsetoCore
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG .ADCINTx
SOC2 (A/B)
9 22 24 37
19
ADCCLKs
20
Result 0 (A) Latched
Conversion 0 (B)
13 ADCClocks
Minimum
7 ADCCLKs
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1 Result 0 (B) Latched
Conversion 1 (A)
13 ADCClocks
ADCRESULT 2
50
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
1 ADCCLK
2 ADCCLKs
2 ADCCLKs
AnalogInputB
SOC0 Sample
BWindow
SOC2 Sample
BWindow
AnalogInput A
SOC0 Sample
A Window
SOC2 Sample
A Window
Figure 9-23. Timing Example for Simultaneous Mode / Late Interrupt Pulse
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
w TEXAS INSTRUMENTS #1 J ,‘ 13ADC mocks W ADCCLKS ADCCLKs
ADCCLK
2
0 9
SOC0 Sample
B Window
Analog Input B
Analog Input A
SOC0 Sample
A Window
37 50
SOC2 Sample
B Window
SOC2 Sample
A Window
2422
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 Result 0 (A) Latched
2 ADCCLKs
Result 0 (B) Latched
ADCRESULT 1
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks 2 ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
ADCINTFLG.ADCINTx
19
ADCCLKs
Figure 9-24. Timing Example for Simultaneous Mode / Early Interrupt Pulse
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS AIOXDIR
9.9.1.2 ADC MUX
To COMPy A or B input
To ADC Channel X
1
0
AIOx Pin
AIOxIN
AIOxINE
SYNC
SYSCLK
Logic implemented in GPIO MUX block
AIODAT Reg
(Read)
AIODAT Reg
(Latch)
AIOSET,
AIOCLEAR,
AIOTOGGLE
Regs
AIOMUX 1 Reg
1
0
AIOxDIR
(1 = Input,
0 = Output)
(0 = Input, 1 = Output)
AIODIR Reg
(Latch)
0
Figure 9-25. AIOx Pin Multiplexing
The ADC channel and Comparator functions are always available. The digital I/O function is available only when
the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin
state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading
the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to
prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO
function disabled for that pin.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.1.3 Comparator Block
Figure 9-26 shows the interaction of the Comparator modules with the rest of the system.
AIO
MUX
COMP x A
COMP xB
COMP x
+
DACx
Wrapper
DAC
Core
10-Bit
+
-
COMP
COMPxOUT
GPIO
MUX
TZ1/2/3
ePWM
Figure 9-26. Comparator Block Diagram
Table 9-23. Comparator Control Registers
REGISTER NAME COMP1
ADDRESS
COMP2
ADDRESS(1)
SIZE
(x16)
EALLOW
PROTECTED DESCRIPTION
COMPCTL 0x6400 0x6420 1 Yes Comparator Control Register
COMPSTS 0x6402 0x6422 1 No Comparator Status Register
DACCTL 0x6404 0x6424 1 Yes DAC Control Register
DACVAL 0x6406 0x6426 1 No DAC Value Register
RAMPMAXREF_ACTIVE 0x6408 0x6428 1 No Ramp Generator Maximum
Reference (Active) Register
RAMPMAXREF_SHDW 0x640A 0x642A 1 No Ramp Generator Maximum
Reference (Shadow) Register
RAMPDECVAL_ACTIVE 0x640C 0x642C 1 No Ramp Generator Decrement Value
(Active) Register
RAMPDECVAL_SHDW 0x640E 0x642E 1 No Ramp Generator Decrement Value
(Shadow) Register
RAMPSTS 0x6410 0x6430 1 No Ramp Generator Status Register
(1) Comparator 2 is available only on the 48-pin PT package.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
INSTRUMENTS 11m]
9.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
9.9.1.3.1.1 Electrical Characteristics of the Comparator/DAC
PARAMETER MIN TYP MAX UNITS
Comparator
Comparator Input Range VSSA – VDDA V
Comparator response time to PWM Trip Zone (Async) 30 ns
Input Offset ±5 mV
Input Hysteresis(1) 35 mV
DAC
DAC Output Range VSSA – VDDA V
DAC resolution 10 bits
DAC settling time See Figure 9-27
DAC Gain –1.5%
DAC Offset 10 mV
Monotonic Yes
INL ±3 LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback
resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual for more information on this option if needed in your system.
Settling Time (ns)
0
100
200
300
400
500
600
700
800
900
1000
1100
0 50 100 150 200 250 300 350 400 450 500
DAC Step Size (Codes)
15 Codes 7 Codes 3 Codes 1 Code
DAC Accuracy
Figure 9-27. DAC Settling Time
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS 6.02
9.9.2 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The
point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level
one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code
to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
6.02
1.76)(SINAD
N
-
=
it is possible to get a measure of performance expressed as N, the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.3 Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
1)(SPIBRR
LSPCLK
rateBaud
+
=
127to3SPIBRRwhen =
4
LSPCLK
rateBaud =
21,0,SPIBRRwhen =
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• Nine SPI module control registers: In control register frame beginning at address 7040h.
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bidirectional 3 wire SPI mode support
The SPI port operation is configured and controlled by the registers listed in Table 9-24 .
Table 9-24. SPI-A Registers
NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Figure 9-28 is a block diagram of the SPI in slave mode.
S
SPICTL.0
SPIINTFLAG
SPIINT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPIBitRate
StateControl
SPIRXBUF
BufferRegister
Clock
Phase
Receiver
OverrunFlag
SPICTL.4
Overrun
INTENA
SPICCR.3-0
SPIBRR.6-0 SPICCR.6 SPICTL.3
SPIDAT.15-0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
DataRegister
M
S
SPICTL.2
SPIChar
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
ToCPU
M
SW1
SPITXBUF
BufferRegister
RXFIFO_0
RXFIFO_1
-----
RXFIFO_3
TXFIFORegisters
TXFIFO_0
TXFIFO_1
-----
TXFIFO_3
RXFIFORegisters
16
16
16
TXInterrupt
Logic
RXInterrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TXFIFOInterrupt
RXFIFOInterrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
0
12
3
0
12
3
4
5
6
TW
SPIPRI.0
TW
TW
TRIWIRE
A. SPISTE is driven low by the master for a slave device.
Figure 9-28. SPI Module Block Diagram (Slave Mode)
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS \ 1 1 1 ‘ F 4‘ i u o no u N o o 29292929292029” ’ofofofofofotofoMfotofofofof92029202929202 ‘ W at ; ‘ 1 ‘ 1 o o totofotofotofofofotofdo‘ fiofiofofofiofiofiofi‘ofotofofofofotofofototofofofof 4F a‘w \1 h 1/ l
9.9.3.1 SPI Master Mode Electrical Data/Timing
Section 9.9.3.1.1 lists the master mode timing (clock phase = 0) and Section 9.9.3.1.2 lists the master mode
timing (clock phase = 1). Figure 9-29 and Figure 9-30 show the timing waveforms.
9.9.3.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(1)
(2) (3) (4)
(5)
PARAMETER
BRR EVEN BRR ODD
UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
2 tw(SPC1)M
Pulse duration, SPICLK first
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10 ns
3 tw(SPC2)M
Pulse duration, SPICLK second
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10 ns
4 td(SIMO)M
Delay time, SPICLK to
SPISIMO valid 10 10 ns
5 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
8 tsu(SOMI)M
Setup time, SPISOMI before
SPICLK 26 26 ns
9 th(SOMI)M
Hold time, SPISOMI valid after
SPICLK 0 0 ns
23 td(SPC)M
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M –
3tc(SYSCLK) – 10
1.5tc(SPC)M –
3tc(SYSCLK) – 10 ns
24 td(STE)M
Delay time, SPICLK to SPISTE
inactive 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
8
Master Out Data Is Valid
3
2
1
SPISTE
5
23 24
Figure 9-29. SPI Master Mode External Timing (Clock Phase = 0)
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS \ \ \ WWW 4‘ Be Vahd W
9.9.3.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
(2) (3) (4)
(5)
PARAMETER
BRR EVEN BRR ODD
UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
2 tw(SPC1)M
Pulse duration, SPICLK first
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10 ns
3 tw(SPC2)M
Pulse duration, SPICLK second
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10 ns
6 td(SIMO)M
Delay time, SPISIMO valid to
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M +
0.5tc(LSPCLK) – 10 ns
7 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M –
0.5tc(LSPCLK) – 10 ns
10 tsu(SOMI)M
Setup time, SPISOMI before
SPICLK 26 26 ns
11 th(SOMI)M
Hold time, SPISOMI valid after
SPICLK 0 0 ns
23 td(SPC)M
Delay time, SPISTE active to
SPICLK
2tc(SPC)M –
3tc(SYSCLK) – 10
2tc(SPC)M –
3tc(SYSCLK) – 10 ns
24 td(STE)M
Delay time, SPICLK to SPISTE
inactive 0.5tc(SPC) – 10 0.5tc(SPC) –
0.5tc(LSPCLK) – 10 ns
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data Must
Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
23 24
SPISTE
Figure 9-30. SPI Master Mode External Timing (Clock Phase = 1)
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS Ha: 1 ‘Pa: \ H 1 a \ m \ >+ #1 1 ‘ 1 H a VVVVVVVVVVVV o‘o‘o‘o‘o‘vo‘o‘o‘o‘vo‘ww '«VVVVVVVVVV' 2.2.2.2.2.2.2.2.2.2.2.2¢-'¢.2.2.2.2.2.2.2.2.2.2.2.2.2¢.2.32.2.2.2.”.32.”2 4;? a1 w w r
9.9.3.2 SPI Slave Mode Electrical Data/Timing
Section 9.9.3.2.1 lists the slave mode timing (clock phase = 0) and Section 9.9.3.2.2 lists the slave mode timing
(clock phase = 1). Figure 9-31 and Figure 9-32 show the timing waveforms.
9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
(4) (3)
(5)
PARAMETER MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 21 ns
16 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
25
16
14
12
SPISTE
26
13
Figure 9-31. SPI Slave Mode External Timing (Clock Phase = 0)
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS
9.9.3.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
(3) (4)
PARAMETER MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
17 td(SOMI)S Delay time, SPICLK to SPISOMI valid 21 ns
18 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
21 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
22 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21 18
17
SPISTE
Data ValidData Valid
14
13
12
25 26
Figure 9-32. SPI Slave Mode External Timing (Clock Phase = 1)
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS 16
9.9.4 Serial Communications Interface (SCI) Module
The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
8*1)(BRR
LSPCLK
rateBaud
+
=
0BRRwhen ¹
16
LSPCLK
rateBaud =
0BRRwhen =
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (nonreturn-to-zero) format
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
The SCI port operation is configured and controlled by the registers listed in Table 9-25.
Table 9-25. SCI-A Registers
NAME(1) ADDRESS SIZE (x16) EALLOW
PROTECTED DESCRIPTION
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
For more information on the SCI, see the Serial Communications Interface (SCI) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
Figure 9-33 shows the SCI module block diagram.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
w TEXAS INSTRUMENTS
TXSHF
Register
TX FIFO_0
TX FIFO_1
TX FIFO_N
8
8
Transmit Data
Buffer Register
SCITXBUF.7-0
RXSHF
Register
RX FIFO_0
RX FIFO_1
RX FIFO_N
8
Receive Data
Buffer Register
SCIRXBUF.7-0
RXENA
SCICTL1.0
8
TX FIFO Interrupts
RX FIFO Interrupts
Baud Rate
MSB/LSB
Registers
SCIHBAUD.15-8
SCILBAUD.7-0
LSPCLK
Frame
Format and Mode
Parity
SCICCR.6
SCICCR.5
Even/Odd
Enable
SCICTL1.3
TXWAKE
WUT
SCICTL1.1
TXENA
RXENA
SCICTL2.6
TXEMPTY
RXFFOVF
SCICTL2.7
TXRDY SCICTL2.0
TXINTENA
SCIRXST.6
RXRDY
SCIRXST.5
BRKDT
SCICTL2.1
RXBKINTENA
TX Interrupt
Logic
RX Interrupt
Logic
SCIRXST.7
RXERROR
SCICTL1.6
RXERRINTENA
SCI RX Interrupt Select Logic
8
8
8
8
8
8
01
01
01
01
SCIFFENA
SCIFFTX.14
RXWAKE
SCIRXST.1
Auto Baud Detect Logic
TXINT
To CPU
RXINT
To CPU
SCITXD
SCIRXD
BRKDT FE OE PE
SCIRXST.5-2
8
SCICTL1.0
SCIFFRX.15
SCI TX Interrupt Select Logic
Figure 9-33. Serial Communications Interface (SCI) Module Block Diagram
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.5 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 9-34 shows how the I2C peripheral module interfaces within the
device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
I2CXSR I2CDXR
I2CRSR I2CDRR
Clock
Synchronizer
Prescaler
Noise Filters
Arbitrator
I2C INT
Peripheral Bus
Interrupt to
CPU/PIE
SDA
SCL
Control/Status
Registers CPU
I2C Module
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 9-34. I2C Peripheral Module Interfaces
The registers in Table 9-26 configure and control the I2C port operation.
Table 9-26. I2C-A Registers
NAME ADDRESS EALLOW
PROTECTED DESCRIPTION
I2COAR 0x7900 No I2C own address register
I2CIER 0x7901 No I2C interrupt enable register
I2CSTR 0x7902 No I2C status register
I2CCLKL 0x7903 No I2C clock low-time divider register
I2CCLKH 0x7904 No I2C clock high-time divider register
I2CCNT 0x7905 No I2C data count register
I2CDRR 0x7906 No I2C data receive register
I2CSAR 0x7907 No I2C slave address register
I2CDXR 0x7908 No I2C data transmit register
I2CMDR 0x7909 No I2C mode register
I2CISRC 0x790A No I2C interrupt source register
I2CPSC 0x790C No I2C prescaler register
I2CFFTX 0x7920 No I2C FIFO transmit register
I2CFFRX 0x7921 No I2C FIFO receive register
I2CRSR – No I2C receive shift register (not accessible to the CPU)
I2CXSR – No I2C transmit shift register (not accessible to the CPU)
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.5.1 I2C Electrical Data/Timing
Section 9.9.5.1.1 shows the I2C timing requirements. Section 9.9.5.1.2 shows the I2C switching characteristics.
9.9.5.1.1 I2C Timing Requirements
MIN MAX UNIT
th(SDA-SCL)START
Hold time, START condition, SCL fall delay
after SDA fall 0.6 µs
tsu(SCL-SDA)START
Setup time, Repeated START, SCL rise
before SDA fall delay 0.6 µs
th(SCL-DAT) Hold time, data after SCL fall 0 µs
tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
tr(SDA) Rise time, SDA Input tolerance 20 300 ns
tr(SCL) Rise time, SCL Input tolerance 20 300 ns
tf(SDA) Fall time, SDA Input tolerance 11.4 300 ns
tf(SCL) Fall time, SCL Input tolerance 11.4 300 ns
tsu(SCL-SDA)STOP
Setup time, STOP condition, SCL rise before
SDA rise delay 0.6 µs
9.9.5.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fSCL SCL clock frequency
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
400 kHz
Vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3-mA sink current 0 0.4 V
tLOW Low period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
1.3 μs
tHIGH High period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
0.6 μs
lI
Input current with an input voltage from
0.1 VDDIO to 0.9 VDDIO MAX –10 10 μA
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS EPWMWIMT EPWMHNY EPWMZINY Epwmmw EPWMxINY cawngm o 2m7 Texas \nslmmcms mmmma
9.9.6 Enhanced PWM Modules (ePWM1/2/3/4)
The devices contain up to four enhanced PWM Modules (ePWM). Figure 9-35 shows a block diagram of multiple
ePWM modules. Figure 9-36 shows the signal interconnections with the ePWM. For more details, see the
Enhanced Pulse Width Modulator (ePWM) chapter in the TMS320F2802x,TMS320F2802xx Technical Reference
Manual .
Table 9-27 shows the complete ePWM register set per module.
EPWM1TZINT
PIE
EPWM1INT
EPWM2TZINT
EPWM2INT
EPWMxTZINT
EPWMxINT
COMPOUT1
COMPOUT2
COMP
SOCA1
ADC SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
EPWM1SYNCI
EPWM2SYNCI
EPWM1SYNCO
EPWM2SYNCO
ePWM1
Module
ePWM2
Module
EPWMxSYNCI
ePWMx
Module
TZ5
TZ6
TZ5
TZ6
TZ5
TZ6
TZ1 TZ3to
CLOCKFAIL
EMUSTOP
CLOCKFAIL
EMUSTOP
EPWM1ENCLK
TBCLKSYNC
EPWM2ENCLK
TBCLKSYNC
EPWMxENCLK
TBCLKSYNC
CLOCKFAIL
EMUSTOP
EPWM1B
C28x CPU
System Control
TZ1 TZ3to
TZ1 TZ3to
EPWM2B
EPWM1SYNCO
eCAPI
H
R
P
W
M
EPWMxB
EPWMxA
EPWM2A
EPWM1A
G
P
I
O
M
U
X
ADCSOCBO
ADCSOCAO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCA1
SOCA2
SPCAx
Peripheral Bus
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
EPWMSYNCI
Copyright © 2017, Texas Instruments Incorporated
Figure 9-35. ePWM
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-27. ePWM Control and Status Registers
NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) /
#SHADOW DESCRIPTION
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1 / 1 Time Base Period High Resolution Register(1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force
Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay
Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay
Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register(1)
HRPWR 0x6821 - - - 1 / 0 HRPWM Power Register
HRMSTEP 0x6826 - - - 1 / 0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1 / 0 High resolution Period Control Register(1)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Compare A HRPWM Register Mirror
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1)
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
Table 9-27. ePWM Control and Status Registers (continued)
NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) /
#SHADOW DESCRIPTION
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCN
T0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCN
T0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter
Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS . QIREZERP. 'H'HHH $$$$$ _EPWMxSVNC_\ DCA‘EW? sync - H "\Ar-
TBPRD Shadow (24)
TBPRD Active (24)
Counter
Up/Down
(16 Bit)
TCBNT
Active (16)
TBCTL[PHSEN]
CTR=PRD
16
Phase
Control
8
CTR=ZERO
CTR_Dir
TBPHSHR (8)
TBPRDHR (8)
8
CTR=ZERO
CTR=CMPB
Disabled
TBCTL[SYNCOSEL]
EPWMxSYNCO
Time-Base (TB)
TBPHS Active (24)
Sync
In/Out
Select
Mux
CTR=PRD
CTR=ZERO
CTR=CMPA
CTR=CMPB
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Event
Trigger
and
Interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
EPWMxSOCB
ADC
Action
Qualifier
(AQ)
EPWMA
Dead
Band
(DB)
EPWMB
PWM
Chopper
(PC)
Trip
Zone
(TZ)
EPWMxA
EPWMxB
CTR=ZERO
EPWMxTZINT
TZ1 TZ3to
EMUSTOP
CLOCKFAIL
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
CTR=CMPA
16
CMPAHR (8)
CTR=CMPB
16
CMPB Active (16)
CMPB Shadow (16)
High-resolution PWM (HRPWM)
CTR=PRD or ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
EPWMxSYNCI
TBCTL[SWFSYNC]
(Software Forced
Sync)
DCAEVT1.sync
DCBEVT1.sync
CMPA Active (24)
CMPA Shadow (24)
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ
signals.
Figure 9-36. ePWM Submodules Showing Critical Internal Signal Interconnections
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I TEXAS INSTRUMENTS
9.9.6.1 ePWM Electrical Data/Timing
PWM refers to PWM outputs on ePWM1–4. Section 9.9.6.1.1 shows the PWM timing requirements and Section
9.9.6.1.2, switching characteristics.
9.9.6.1.1 ePWM Timing Requirements
MIN(1) MAX UNIT
tw(SYCIN) Sync input pulse width
Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
9.9.6.1.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 33.33 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low no pin load 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
9.9.6.2 Trip-Zone Input Timing
9.9.6.2.1 Trip-Zone Input Timing Requirements
MIN(1) MAX UNIT
tw(TZ) Pulse duration, TZx input low
Asynchronous 2tc(TBCLK) cycles
Synchronous 2tc(TBCLK) cycles
With input qualifier 2tc(TBCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
PWM(B)
TZ(A)
SYSCLK
tw(TZ)
td(TZ-PWM)HZ
A. TZ - TZ1, TZ2, TZ3
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 9-37. PWM Hi-Z Characteristics
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.7 High-Resolution PWM (HRPWM)
This module combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
Note
The minimum SYSCLKOUT frequency allowed for HRPWM is 50 MHz.
Note
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output is not
available for use.
9.9.7.1 HRPWM Electrical Data/Timing
Section 9.9.7.1.1 shows the high-resolution PWM switching characteristics.
9.9.7.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz–60 MHz
PARAMETER(1) MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(2) 150 310 ps
(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 50 MHz. Below 50 MHz, with device process variation, the MEP step
size may decrease under cold temperature and high core voltage conditions to such a point that 255 MEP steps will not span an entire
SYSCLKOUT cycle.
(2) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
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TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS Pa‘amv Manual and Capyngm @ 2017. Texas \nstmmems \ncamameu
9.9.8 Enhanced Capture Module (eCAP1)
The device contains an enhanced capture (eCAP) module. Figure 9-38 shows a functional block diagram of a
module.
TSCTR
(counter−32 bit)
RST
CAP1
(APRD active) LD
CAP2
(ACMP active) LD
CAP3
(APRD shadow) LD
CAP4
(ACMP shadow) LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Prescale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
Copyright © 2017, Texas Instruments Incorporated
Figure 9-38. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-28. eCAP Control and Status Registers
NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION
TSCTR 0x6A00 2 Time-Stamp Counter
CTRPHS 0x6A02 2 Counter Phase Offset Value Register
CAP1 0x6A04 2 Capture 1 Register
CAP2 0x6A06 2 Capture 2 Register
CAP3 0x6A08 2 Capture 3 Register
CAP4 0x6A0A 2 Capture 4 Register
Reserved 0x6A0C to 0x6A12 8 Reserved
ECCTL1 0x6A14 1 Capture Control Register 1
ECCTL2 0x6A15 1 Capture Control Register 2
ECEINT 0x6A16 1 Capture Interrupt Enable Register
ECFLG 0x6A17 1 Capture Interrupt Flag Register
ECCLR 0x6A18 1 Capture Interrupt Clear Register
ECFRC 0x6A19 1 Capture Interrupt Force Register
Reserved 0x6A1A to 0x6A1F 6 Reserved
For more information on the eCAP, see the Enhanced Capture (eCAP) Module chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual .
9.9.8.1 eCAP Electrical Data/Timing
Section 9.9.8.1.1 shows the eCAP timing requirement and Section 9.9.8.1.2 shows the eCAP switching
characteristics.
9.9.8.1.1 Enhanced Capture (eCAP) Timing Requirement
MIN(1) MAX UNIT
tw(CAP) Capture input pulse width
Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
9.9.8.1.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
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fl TEXAS INSTRUMENTS
9.9.9 JTAG Port
On the 2802x device, the JTAG port is reduced to 5 pins ( TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and
TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in
Figure 9-39. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/
XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device
during emulation/debug because this pin will be needed for the TCK function.
Note
In 2802x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board
design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of
the JTAG pin function. Any circuitry connected to these pins should not prevent the JTAG debug probe
from driving (or being driven by) the JTAG pins for successful debug.
TRST
1
0
C28x
Core
TCK/GPIO38
TCK
XCLKIN
GPIO38_in
GPIO38_out
TDO
GPIO37_out
TDO/GPIO37
GPIO37_in
1
0
TMS
TMS/GPIO36
GPIO36_out
GPIO36_in
1
1
0
TDI
TDI/GPIO35
GPIO35_out
GPIO35_in
1
TRST
TRST
=0:JTAGDisabled(GPIOMode)
=1:JTAGMode
TRST
Figure 9-39. JTAG/GPIO Multiplexing
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
9.9.10 General-Purpose Input/Output (GPIO) MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to
providing individual pin bit-banging I/O capability.
The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 9-29 shows the GPIO register
mapping.
Table 9-29. GPIO Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pullup Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 38)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 38)
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 38)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 38)
GPBPUD 0x6F9C 2 GPIO B Pullup Disable Register (GPIO32 to 38)
AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 38)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 38)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 38)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 38)
AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15)
AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
Note
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and
GPxQSELn registers occurs to when the action is valid.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-30. GPIOA MUX
DEFAULT AT RESET
PRIMARY I/O
FUNCTION(1) (2)
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPAMUX1 REGISTER
BITS (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
5-4 GPIO2 EPWM2A (O) Reserved Reserved
7-6 GPIO3 EPWM2B (O) Reserved COMP2OUT(3) (O)
9-8 GPIO4 EPWM3A (O) Reserved Reserved
11-10 GPIO5 EPWM3B (O) Reserved ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved
17-16 Reserved Reserved Reserved Reserved
19-18 Reserved Reserved Reserved Reserved
21-20 Reserved Reserved Reserved Reserved
23-22 Reserved Reserved Reserved Reserved
25-24 GPIO12 TZ1 (I) SCITXDA (O) Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
GPAMUX2 REGISTER
BITS (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) SCITXDA (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDA (I) ECAP1 (I/O)
9-8 Reserved Reserved Reserved Reserved
11-10 Reserved Reserved Reserved Reserved
13-12 Reserved Reserved Reserved Reserved
15-14 Reserved Reserved Reserved Reserved
17-16 Reserved Reserved Reserved Reserved
19-18 Reserved Reserved Reserved Reserved
21-20 Reserved Reserved Reserved Reserved
23-22 Reserved Reserved Reserved Reserved
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These functions are not available in the 38-pin package.
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-31. GPIOB MUX
DEFAULT AT RESET
PRIMARY I/O
FUNCTION(1)
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPBMUX1 REGISTER
BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
1-0 GPIO32(2) SDAA(2) (I/OD) EPWMSYNCI(2) (I) ADCSOCAO (2) (O)
3-2 GPIO33(2) SCLA(2) (I/OD) EPWMSYNCO(2) (O) ADCSOCBO (2) (O)
5-4 GPIO34 COMP2OUT (O) Reserved Reserved
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 Reserved Reserved Reserved Reserved
17-16 Reserved Reserved Reserved Reserved
19-18 Reserved Reserved Reserved Reserved
21-20 Reserved Reserved Reserved Reserved
23-22 Reserved Reserved Reserved Reserved
25-24 Reserved Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
(1) I = Input, O = Output, OD = Open Drain
(2) These pins are not available in the 38-pin package.
Table 9-32. Analog MUX for 48-Pin PT Package
DEFAULT AT RESET(1)
AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 ADCINA3 (I) ADCINA3 (I)
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 – –
13-12 AIO6 (I/O) ADCINA6 (I)
15-14 ADCINA7 (I) ADCINA7 (I)
17-16 – –
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 ADCINB3 (I) ADCINB3 (I)
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 – –
29-28 AIO14 (I/O) ADCINB6 (I)
31-30 ADCINB7 (I) ADCINB7 (I)
(1) I = Input, O = Output
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TEXAS INSTRUMENTS
Table 9-33. Analog MUX for 38-Pin DA Package
DEFAULT AT RESET(1)
AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
3-2 – –
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 – –
9-8 AIO4 (I/O) ADCINA4 (I)
11-10 – –
13-12 AIO6 (I/O) ADCINA6 (I)
15-14 – –
17-16 – –
19-18 – –
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 – –
25-24 AIO12 (I/O) ADCINB4 (I)
27-26 – –
29-28 AIO14 (I/O) ADCINB6 (I)
31-30 – –
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the
same (all 0s or all 1s) as shown in Figure 9-42 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS A |:l a V 4» {>—‘ + a —> A E N 7 GP SET fi—l GPXDAT (\atch) A ‘7 k, k, F i «r F D g
GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low-Power
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific variations, see the
System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual .
Figure 9-40. GPIO Multiplexing
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS \ «er ”’1 “7
9.9.10.1 GPIO Electrical Data/Timing
9.9.10.1.1 GPIO - Output Timing
9.9.10.1.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 13(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 13(1) ns
tfGPO Toggling frequency 15 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Section 9.9.10.1.1.1 are applicable for a 40-pF load on
I/O pins.
GPIO
tr(GPO)
tf(GPO)
Figure 9-41. General-Purpose Output Timing
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS MMMMMMMMMMM
9.9.10.1.2 GPIO - Input Timing
9.9.10.1.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
tw(SP) Sampling period QUALPRD = 0 1tc(SCO) cycles
QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SCO) cycles
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
GPIO Signal
1
Sampling Window
Output From
Qualifier
1 1 1111111110000000 000
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(A)
GPxQSELn = 1,0 (6 samples)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ]
(C)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
(D)
tw(SP)
tw(IQSW)
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 9-42. Sampling Mode
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
fl TEXAS INSTRUMENTS /\_/\+/\_/\_/\_ X X \ \ H 4" * Ti ”7
9.9.10.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
GPIOxn
SYSCLK
tw(GPI)
Figure 9-43. General-Purpose Input Timing
VDDIO
VSS VSS
2 pF
> 1 MS
Figure 9-44. Input Resistance Model for a GPIO Pin With an Internal Pullup
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.10.1.4 Low-Power Mode Wakeup Timing
Section 9.9.10.1.4.1 shows the timing requirements, Section 9.9.10.1.4.2 shows the switching characteristics,
and Figure 9-45 shows the timing diagram for IDLE mode.
9.9.10.1.4.1 IDLE Mode Timing Requirements
MIN(1) MAX UNIT
tw(WAKE-INT) Pulse duration, external wake-up signal Without input qualifier 2tc(SCO) cycles
With input qualifier 5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
9.9.10.1.4.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN MAX UNIT
td(WAKE-IDLE)
Delay time, external wake signal to program execution resume (2) cycles
• Wake up from Flash
– Flash module in active state
Without input qualifier 20tc(SCO) cycles
With input qualifier 20tc(SCO) + tw(IQSW)
• Wake up from Flash
– Flash module in sleep state
Without input qualifier 1050tc(SCO)
cycles
With input qualifier 1050tc(SCO) +
tw(IQSW)
• Wake up from SARAM Without input qualifier 20tc(SCO) cycles
With input qualifier 20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 9.9.10.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
WAKE INT(A)(B)
XCLKOUT
Address/Data
(internal)
td(WAKE−IDLE)
tw(WAKE−INT)
A. WAKE INT can be any enabled interrupt, WDINT or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 9-45. IDLE Entry and Exit Timing
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
9.9.10.1.4.3 STANDBY Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-INT)
Pulse duration, external
wake-up signal
Without input qualification 3tc(OSCCLK) cycles
With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
9.9.10.1.4.4 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
td(WAKE-STBY)
Delay time, external wake signal to program execution
resume(1) cycles
• Wake up from flash
– Flash module in active state
Without input qualifier 100tc(SCO) cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
• Wake up from flash
– Flash module in sleep state
Without input qualifier 1125tc(SCO) cycles
With input qualifier 1125tc(SCO) + tw(WAKE-INT)
• Wake up from SARAM Without input qualifier 100tc(SCO) cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
{5‘ TEXAS INSTRUMENTS
td(IDLE−XCOL)
Wake-up
Signal(H)
X1/X2 or
XCLKIN
XCLKOUT
Flushing Pipeline
(A)
Device
Status STANDBY Normal ExecutionSTANDBY
(G)(B)
(C)
(D)(E)
(F)
tw(WAKE-INT)
td(WAKE-STBY)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 9-46. STANDBY Entry and Exit Timing Diagram
9.9.10.1.4.5 HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal toscst + 8tc(OSCCLK) cycles
9.9.10.1.4.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tpPLL lock-up time 1 ms
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
• Wake up from flash
– Flash module in sleep state
1125tc(SCO) cycles
• Wake up from SARAM 35tc(SCO) cycles
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
fl TEXAS INSTRUMENTS
td(IDLE−XCOL)
X1/X2 or
XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
td(WAKE−HALT
Device
Status
PLL Lock-up Time Normal
Execution
tw(WAKE-GPIO)
GPIOn(I)
Oscillator Start-up Time
(A)
(G)
(C)
(D)(E)
(F)
(B)
(H)
)
tp
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off
and the CLKIN to the core is stopped:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to
keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. This is done by writing to the
appropriate bits in the CLKCTL register.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 9-47. HALT Mode Wakeup Using GPIOn
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
10 Applications, Implementation, and Layout
Note
Information in the following sections is not part of the TI component specification, and TI does not
warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to
confirm system functionality.
10.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
36V/1kW Brushless DC Motor Drive with Stall Current Limit of <1us Response Time Reference Design
This reference design is a power stage for brushless motors in battery-powered garden and power tools rated up
to 1 kW, operating from a 10-cell lithium-ion battery with a voltage range from 36 V to 42 V. The design uses 60-
V, N-channel NexFET™ technology featuring a very low drain-to-source resistance (RDS_ON) of 1.8 mΩ in a
SON5x6 SMD package, which results in a very small PCB form factor of 57 mm × 59 mm. The 3-phase gate-
driver is used to drive a 3-phase MOSFET bridge, which can operate from 6 V to 60 V and supports
programmable gate current with a maximum setting of 2.3-A sink/1.7-A source. The C2000 F28027 LaunchPad™
development kit (LAUNCHXL-F28027) is used with this power stage, and 120-degree trapezoidal control of
BLDC motor with Hall sensors is implemented in software. The cycle-by-cycle current limit feature in the gate-
driver protects the board from excessive current that is caused during motor stalls, by limiting the maximum
current allowed in the power stage to a safe level.
Single-Ended Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for single-ended SAR ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative measurement
circuit with external SAR ADCs as well as circuits for high-speed overcurrent and earth fault detection. Proper
signal conditioning improves noise immunity on critical current measurements in motor drives. This reference
design can help increase the effective resolution of the analog-to-digital conversion, improving motor drive
efficiency.
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 119
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
11 Device and Documentation Support
11.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28023). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PT) and temperature range (for example, S). Figure 11-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2802x,
TMS320F2802xx MCUs Silicon Errata .
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
120 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS Generic Fan Number: TMS 320 F 23023 -01 Orderable Fan Number TMS 320 F 23023 FT S R PREFIX —J L SHIPPING OPTIONS TMX : expenmemaI devIce wank : my 1MP : meonpe devIce TMS : quaIified devIce R = Tape and Reel 7 QUALIFICATION (in Generic Part Number) BIank : NanrAqumotII/e DEVICE FAMILY -Q1 = Q1 refers (0 Au‘omollve AEC 0100 Grade 1 qualIfICalIon 320 = Tmsszo Mcu FamIIy 7 TEMPERATURE RANGE (in Orderable Pan Number) T : —40“cm105"c s *AODC10125DC Q : ’AODC10125DC TECHNOLOGY PACKAGE TVFE F : Flash 48er PT LowrProme Quad Flatpack (LQFP) aa-Pm DA Thm Shrmk SmaII-Ouume Package (TSSOP) DEWCE 28027 28027F 28026 28026F 28023 28022 28021 25020 280200
A. For more information on peripheral, temperature, and package availability for a specific device, see Table 6-1.
Figure 11-1. Device Nomenclature
11.2 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step
of the application development flow. Familiar tools and interfaces allow users to get started faster than ever
before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug
capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
C2000 F28027 LaunchPad™ development kit
The C2000 F28027 LaunchPad™ development kit is an inexpensive, modular, and fun evaluation platform,
enabling you to dive into real-time, closed-loop control development with Texas Instruments’ C2000 32-bit
microcontroller family. This platform provides a great starting point for development of many common power
electronics applications, including motor control, digital power supplies, solar inverters, digital LED lighting,
precision sensing, and more.
To view all available C2000 LaunchPad development kits and BoosterPack™ plug-in modules, visit the
Embedded development hardware kits & boards site.
Software Tools
powerSUITE - Digital Power Supply Design Software Tools for C2000™ MCUs
powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-time
microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce development time
as they design digitally-controlled power supplies based on C2000 real-time control MCUs.
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 121
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific TMS320F2802x hands-on training resources can be found at C2000™ MCU Device Workshops.
InstaSPIN-FOC LaunchPad and BoosterPack
This 6-part series provides information about the C2000 InstaSPIN-FOC Motor Control LaunchPad Development
Kit and BoosterPack Plug-in Module.
The InstaSPIN-FOC enabled C2000 F28027 LaunchPad™ development kit is an inexpensive evaluation
platform designed to help you leap right into the world of sensorless motor control using the InstaSPIN-FOC
solution.
•Part 1: Introduction and Overview
•Part 2: Identifying Your Motor
•Part 3: Zero Speed, Low Speed, & Tuning
•Part 4: Accelerations & Speed Reversals with Texas Instruments
•Part 5: High, Higher, Highest Speeds with Texas Instruments
•BOOSTXL-DRV8301 BoosterPack with Texas Instruments
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
122 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
11.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2802x, TMS320F2802xx MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F2802x,TMS320F2802xx Technical Reference Manual details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the device.
InstaSPIN Technical Reference Manuals
InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPIN-
MOTION devices.
TMS320F28026F, TMS320F28027F InstaSPIN™-FOC Software Technical Reference Manual describes the
TMS320F28026F and TMS320F28027F InstaSPIN-FOC software.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This reference
guide also describes emulation features available on these DSPs.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
digital signal processors (DSPs).
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Calculating FIT for a Mission Profile explains how use TI’s reliability de-rating tools to calculate a component
level FIT under power on conditions for a system mission profile.
Oscillator Compensation Guide describes a factory supplied method for compensating the internal oscillators for
frequency drift caused by temperature.
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 123
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
l TEXAS INSTRUMENTS
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
InstaSPIN-FOC™, TMS320C2000™, NexFET™, LaunchPad™, TMS320™, BoosterPack™, InstaSPIN-MOTION™,
and TI E2E™ are trademarks of Texas Instruments.
I2C-bus® is a registered trademark of NXP B.V. Corporation.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021 www.ti.com
124 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 125
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2022
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320F280200DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F280200DAS
S320
TMS320F280200DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F280200DAT
S320
TMS320F280200PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F280200PTT
TMS320F28020DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28020DAS
S320
TMS320F28020DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28020DAT
S320
TMS320F28020PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
F28020PTS
TMS320F28020PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28020PTT
TMS320F28021DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28021DAS
S320
TMS320F28021DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28021DAT
S320
TMS320F28021PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
F28021PTS
TMS320F28021PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28021PTT
TMS320F28022DAQ ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28022DAQ
S320
TMS320F28022DAQR ACTIVE TSSOP DA 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR F28022DAQ
S320
TMS320F28022DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28022DAS
S320
TMS320F28022DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28022DAT
S320
TMS320F28022PTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (S320, S320 980)
F28022PTQ
TMS320F28022PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2022
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
F28022PTS
TMS320F28022PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28022PTT
TMS320F28023DAQ ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28023DAQ
S320
TMS320F28023DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28023DAS
S320
TMS320F28023DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28023DAT
S320
TMS320F28023PTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (S320, S320 980)
F28023PTQ
TMS320F28023PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
F28023PTS
TMS320F28023PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 (S320, S320 980)
F28023PTT
TMS320F28026DAQ ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28026DAQ
S320
TMS320F28026DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28026DAS
S320
TMS320F28026DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28026DAT
S320
TMS320F28026FPTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320F 980
28026FPTQ
TMS320F28026FPTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28026FPTT
TMS320F28026PTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (S320, S320 980)
F28026PTQ
TMS320F28026PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
F28026PTS
TMS320F28026PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28026PTT
TMS320F28027DAQ ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28027DAQ
S320
TMS320F28027DAS ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28027DAS
S320
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2022
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320F28027DASR ACTIVE TSSOP DA 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 F28027DAS
S320
TMS320F28027DAT ACTIVE TSSOP DA 38 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28027DAT
S320
TMS320F28027DATR ACTIVE TSSOP DA 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 F28027DAT
S320
TMS320F28027FPTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320
F28027FPTQ
TMS320F28027FPTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28027FPTT
TMS320F28027FPTTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28027FPTT
TMS320F28027PTQ ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (S320, S320 980)
F28027PTQ
TMS320F28027PTQR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320
F28027PTQ
TMS320F28027PTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28027PTT
TMS320F28027PTS ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
F28027PTS
TMS320F28027PTT ACTIVE LQFP PT 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
F28027PTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2022
Addendum-Page 4
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F28022, TMS320F28022-Q1, TMS320F28023, TMS320F28023-Q1, TMS320F28026, TMS320F28026-Q1, TMS320F28026F,
TMS320F28026F-Q1, TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1 :
•Catalog : TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28026F, TMS320F28027, TMS320F28027F
•Automotive : TMS320F28022-Q1, TMS320F28023-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28027-Q1, TMS320F28027F-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TMS320F28022DAQR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
TMS320F28027DASR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
TMS320F28027DATR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMS320F28022DAQR TSSOP DA 38 2000 350.0 350.0 43.0
TMS320F28027DASR TSSOP DA 38 2000 350.0 350.0 43.0
TMS320F28027DATR TSSOP DA 38 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TMS320F280200DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F280200DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28020DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28020DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28021DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28021DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28022DAQ DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28022DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28022DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28023DAQ DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28023DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28023DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28026DAQ DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28026DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28026DAT DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28027DAQ DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28027DAS DA TSSOP 38 40 530 11.89 3600 4.9
TMS320F28027DAT DA TSSOP 38 40 530 11.89 3600 4.9
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2022
Pack Materials-Page 3
l TEXAS INSTRUMENTS L - Outer tray length without tabs J: K0 - Outer tray height +++++++++++++++ +++++++++++++++ +++++++++++++++ am, +++++++++++++++ rm. +++++++++++++++ i+++++trgr+++++++ | P1 - Tray unit pocket pitch CW - Measurement tor tray edge (Y direction) to comer pocket center — CL - Measurement for tray edge (X direction) to corner pocket center
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device Package
Name Package
Type Pins SPQ Unit array
matrix Max
temperature
(°C)
L (mm) W
(mm) K0
(µm) P1
(mm) CL
(mm) CW
(mm)
TMS320F280200PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28020PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28021PTS PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28021PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28022PTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28022PTS PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28022PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28023PTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28023PTS PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28023PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28026FPTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28026FPTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28026PTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28026PTS PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28026PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28027FPTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28027FPTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2022
Pack Materials-Page 4
l TEXAS INSTRUMENTS
Device Package
Name Package
Type Pins SPQ Unit array
matrix Max
temperature
(°C)
L (mm) W
(mm) K0
(µm) P1
(mm) CL
(mm) CW
(mm)
TMS320F28027PTQ PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28027PTS PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TMS320F28027PTT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2022
Pack Materials-Page 5
PT0048A N1234
www.ti.com
PACKAGE OUTLINE
0.25
GAGE PLANE
0 -7
7.2
6.8
7.2
6.8
9.2
8.8
4X 5.5
44X 0.5
9.2
8.8
48X 0.27
0.17
1.6 MAX
0.5 MIN
1.45
1.35
0.75
0.45
LQFP - 1.6 mm max heightPT0048A
LOW PROFILE QUAD FLATPACK
4215159/A 12/2021
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
0.08 C A B
SEATING PLANE
SEE DETAIL A
A15.000
DETAIL A
SCALE 2.000
A
B
C
0000000 LEHHHHHfiEHHHHE/é f§ § # % EB CC] 5% ; § E % $ CF W HHLH 1%
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALLAROUND
0.05 MIN
ALL AROUND
(8.2)
(8.2)
48X (1.6)
48X (0.3)
44X (0.5)
(R0.05) TYP
LQFP - 1.6 mm max heightPT0048A
LOW PROFILE QUAD FLATPACK
4215159/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE 10.000
PKG SYMM
PKG
SYMM
1
12
13 24
25
36
37
48 SEE SOLDER MASK
DETAILS
EXPOSED METAL
METAL EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
0000000 fiflflflufim LJEIEr E #43714 ,,,,,,, E, 5% ; § E ; E HEHHHHHHHHHH
www.ti.com
EXAMPLE STENCIL DESIGN
(8.2)
(8.2)
48X (1.6)
48X (0.3)
44X (0.5)
(R0.05) TYP
LQFP - 1.6 mm max heightPT0048A
LOW PROFILE QUAD FLATPACK
4215159/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 10X
PKG SYMM
PKG
SYMM
1
12
13 24
25
36
37
48
MECHANICAL DATA DA (R—PDSO—G**) PLASTlC SMALL—OUTL‘NE PACKAGE 35 PIN SHOWN <— a="" —=""> 38 207 HHHHHHHHHHHHHHHHHHH M 6.00 5,30 0,15 NOM 7,90 0 A HHHHHHHHHHHHHHHHHHH L 4L2; Seating Piane 1,20 MAX m 0,05 DIM PM" 30 32 35 A MAX 11,10 11,10 12,60 A MW 1090 10.90 12.40 A $743 DB—‘i DC 00—1 4040066/F 01/2009 NOTES: A. Ail linear dimensions are in miilirneters, a. inis drawing is subject 10 cnange wiinoui noiice. C. Body dimensions do not inciude mold flash or protrusion Moid flash and pm‘rusion shali n01 exceed 0.15 per side. 1% Falis within JEDEC 140—155, excepi 30 pin body iengin. ”11-3055 ”.100!“
LAND PATTERN DATA Star-CH 0pm 5 Examrfle Board Layou: Based on a stem mmess 0" 0 127m (0 005mm) J3+HHHHHHHH~HHHH€HHH~HM HMELHHHHHHHHHHHH / ' \_ Example Solder Mask Opening {See \ute D) Pcd Geo'netry NOTES. A AH hneur dxrrensiows are m rrHHmeters E m dmwmg is subject [a change thhout wth c .oser » g apermes wnh :mpezcnm WM and 250 'cuncwq comevs wH (fer bener pads ve‘ense (luskmers shoud comcc ,her boc'd cssemby Ste (0r stencfl deswg'v recummendchuns anmp‘e stem deswgr based m u 53% voumet'c men ma so‘de' pcste Refer «a \PC77575 (or other new recnmmerdaimr‘s D Comm the boom mbncnhon sue my recommenced so‘demcsk te‘emnces will TEXAS INSTRUMENTS www.li.com
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