Fiche technique pour TPS211(2,3)A de Texas Instruments

I TEXAS INSTRUMENTS 0—H,
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4RL
RILIM
CL
0.1 Fm
0.1 Fm
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
R1
Switch
Status
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
AUTOSWITCHING POWER MUX
Check for Samples: TPS2112A,TPS2113A
1FEATURES APPLICATIONS
2• Two-Input, One-Output Power Multiplexer with • PCs
Low rDS(on) Switches: • PDAs
– 84 mΩTyp (TPS2113A) • Digital Cameras
– 120 mΩTyp (TPS2112A) • Modems
• Reverse and Cross-Conduction Blocking • Cell Phones
• Wide Operating Voltage: 2.8 V to 5.5 V • Digital Radios
• Low Standby Current: 0.5 μA Typ • MP3 Players
• Low Operating Current: 55 μA Typ DESCRIPTION
• Adjustable Current Limit The TPS211xA family of power multiplexers enables
• Controlled Output Voltage Transition Time: seamless transition between two power supplies
– Limits Inrush Current (such as a battery and a wall adapter), each
– Minimizes Output Voltage Hold-Up operating at 2.8 V to 5.5 V and delivering up to 2 A,
depending on package. The TPS211xA family
Capacitance includes extensive protection circuitry, including user-
• CMOS- and TTL-Compatible Control Inputs programmable current limiting, thermal protection,
• Auto-Switching Operating Mode inrush current control, seamless supply transition,
• Thermal Shutdown cross-conduction blocking, and reverse-conduction
blocking. These features greatly simplify designing
• Available in TSSOP-8 and 3-mm × 3-mm SON-8 power multiplexer applications.
Packages space
TYPICAL APPLICATION
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
FEATURE TPS2110A TPS2111A TPS2112A TPS2113A TPS2114A TPS2115A
0.31 A to 0.63 A to 0.31 A to 0.31 A to
Current Limit Adjustment Range 0.63 A to 2 A 0.63 A to 2 A
0.75 A 1.25 A 0.75 A 0.75 A
Manual Yes Yes No No Yes Yes
Switching Modes Automatic Yes Yes Yes Yes Yes Yes
Switch Status Output No No Yes Yes Yes Yes
DEVICE INFORMATION(1)
TAPACKAGE IOUT (A) ORDERING NUMBER PACKAGE MARKING
0.75 TPS2112APW 2112A
TSSOP-8 (PW)
−40°C to +85°C 1.25 TPS2113APW 2113A
SON-8 (DRB) 2 TPS2113ADRB PTOI
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over recommended junction temperature range, unless otherwise noted.
TPS2112A, TPS2113A UNIT
Input voltage range at pins IN1, IN2, EN, VSNS, ILIM(2) −0.3 to 6 V
Output voltage range, VO(OUT), VO(STAT)(2) −0.3 to 6 V
Output sink current, IO(STAT) 5 mA
TPS2112APW 0.9 A
Continuous output current, IOTPS2113APW 1.5 A
TPS2113ADRB, TJ≤105°C 2.5 A
Continuous total power dissipation See Dissipation Ratings table
Junction temperature Internally Limited
Human body model (HBM) 2 kV
ESD Charged device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATION RATINGS
DERATING FACTOR TA≤25°C POWER TA= 70°C POWER TA= 85°C POWER
PACKAGE ABOVE TA= 25°C RATING RATING RATING
TSSOP-8 (PW) 3.9 mW/°C 387 mW 213 mW 155 mW
SON-8 (DRB)(1) 25.0 mW/°C 2.50 mW 1.38 mW 1.0 W
(1) See TI application note SLMA002 for mounting recommendations.
2Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
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SBVS045C –MARCH 2004–REVISED MAY 2012
RECOMMENDED OPERATING CONDITIONS
TPS2112A, TPS2113A
MIN NOM MAX UNIT
VI(IN2) ≥2.8 V 1.5 5.5
Input voltage at IN1, VI(IN1) V
VI(IN2) < 2.8 V 2.8 5.5
VI(IN1) ≥2.8 V 1.5 5.5
Input voltage at IN2, VI(IN2) V
VI(IN1) < 2.8 V 2.8 5.5
Input voltage: VI(EN), VI(VSNS) 0 5.5 V
TPS2112APW 0.31 0.75 A
Nominal current limit adjustment range, TPS2113APW 0.63 1.25
IO(OUT)(1)
TPS2113ADRB, TJ≤105°C 0.63 2 A
Operating virtual junction temperature, TJ–40 125 °C
(1) Minimum recommended current limit is based on accuracy considerations.
ELECTRICAL CHARACTERISTICS: Power Switch
Over recommended operating junction temperature, RILIM = 400 Ω, unless otherwise noted.
TPS2112A TPS2113A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110
TJ= 25°C, VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 mΩ
IL= 500 mA
Drain-source VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110
on-state rDS(on)(1)
resistance VI(IN1) = VI(IN2) = 5.0 V 220 150
(INx−OUT) TJ= 125°C, VI(IN1) = VI(IN2) = 3.3 V 220 150 mΩ
IL= 500 mA VI(IN1) = VI(IN2) = 2.8 V 220 150
(1) The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
ELECTRICAL CHARACTERISTICS
Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted.
TPS2112A, TPS2113A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS (EN)
High-level input voltage VIH 2 V
Low-level input voltage VIL 0.7 V
EN = High, sink current 1
Input current μA
EN = Low, source current 0.5 1.4 5
SUPPLY AND LEAKAGE CURRENTS
VI(VSNS) = 1.5 V, EN = Low (IN1 active), 55 90
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
VI(VSNS) = 1.5 V, EN = Low (IN1 active), 1 12
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
Supply current from IN1 (operating) μA
VI(VSNS) = 0 V, EN = Low (IN2 active), 75
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
VI(VSNS) = 0 V, EN = Low (IN2 active), 1
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
VI(VSNS) = 1.5 V, EN = Low (IN1 active), 1
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
VI(VSNS) = 1.5 V, EN = Low (IN1 active), 75
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
Supply current from IN2 (operating) μA
VI(VSNS) = 0 V, EN = Low (IN2 active), 1 12
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
VI(VSNS) = 0 V, EN = Low (IN2 active), 55 90
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
Copyright © 2004–2012, Texas Instruments Incorporated 3
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted.
TPS2112A, TPS2113A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY AND LEAKAGE CURRENTS, Continued
EN = High (inactive), VI(IN1) = 5.5 V, 0.5 2
VI(IN2) = 3.3 V
Quiescent current from IN1 (standby) μA
EN = High (inactive), VI(IN1) = 3.3 V, 1
VI(IN2) = 5.5 V
EN = High (inactive), VI(IN1) = 5.5 V, 1
VI(IN2) = 3.3 V
Quiescent current from IN2 (standby) μA
EN = High (inactive), VI(IN1) = 3.3 V, 0.5 2
VI(IN2) = 5.5 V
Forward leakage current from IN1 EN = High (inactive), VI(IN1) = 5.5 V, IN2 open, 0.1 5 μA
(measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ= 25°C
Forward leakage current from IN2 EN = High (inactive), VI(IN2) = 5.5 V, IN1 open, 0.1 5 μA
(measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ= 25°C
Reverse leakage current to INx (measured EN = High (inactive), VI(INx) = 0 V, 0.3 5 μA
from INx to GND) VO(OUT) = 5.5 V, TJ= 25°C
STAT OUTPUT
Leakage current VO(STAT) = 5.5 V 0.01 1 μA
Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 V
Deglitch time (falling edge only) 150 μs
CURRENT LIMIT CIRCUIT
RILIM = 400 Ω0.51 0.63 0.80
TPS2112A A
RILIM = 700 Ω0.30 0.36 0.50
Current limit accuracy RILIM = 400 Ω0.95 1.25 1.56
TPS2113A A
RILIM = 700 Ω0.47 0.71 0.99
Time for short-circuit output current to settle
Current limit settling time td1 ms
within 10% of its steady state value.
Input current at ILIM VI(ILIM) = 0 V –15 0 μA
VSNS COMPARATOR
VI(VSNS) ↑0.78 0.80 0.82
VSNS threshold voltage V
VI(VSNS) ↓0.735 0.755 0.775
VSNS comparator hysteresis 30 60 mV
Deglitch of VSNS comparator (both ↑↓) 90 150 220 μs
Input current 0 V ≤VI(VSNS) ≤5.5 V –1 1 μA
UVLO
Falling edge 1.15 1.25
IN1 and IN2 UVLO V
Rising edge 1.30 1.35
IN1 and IN2 UVLO hysteresis 30 57 65 mV
Falling edge 2.4 2.53
Internal VDD UVLO (the higher of IN1 and V
IN2) Rising edge 2.58 2.8
Internal VDD UVLO hysteresis 30 50 75 mV
UVLO deglitch for IN1, IN2 Falling edge 110 μs
4Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
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SBVS045C –MARCH 2004–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted.
TPS2112A, TPS2113A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REVERSE CONDUCTION BLOCKING
EN = high, VI(IN1) = 3.3 V and VI(IN2) = VI(VSNS)
Minimum output-to-input = 0 V. Connect OUT to a 5-V supply through
voltage difference to block ΔVO(I_block) a series 1-kΩresistor. Let EN = low. Slowly 80 100 120 mV
switching decrease the supply voltage until OUT
connects to IN1.
THERMAL SHUTDOWN
Thermal shutdown threshold TPS211xA is in current limit. 135 °C
Recovery from thermal shutdown TPS211xA is in current limit. 125 °C
Hysteresis 10 °C
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator 0.1 0.2 V
Deglitch of IN2−IN1 comparator (both ↑ ↓) 10 20 50 μs
SWITCHING CHARACTERISTICS
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2112A TPS2113A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
TJ= 25°C,
Output rise VI(IN1) = VI(IN2) = 5 V, CL= 1 μF,
tRtime from an 0.5 1.0 1.5 1 1.8 3 ms
VI(SNS) = 1.5 V IL= 500 mA; see
enable Figure 1(a).
TJ= 25°C,
Output fall VI(IN1) = VI(IN2) = 5 V, CL= 1 μF,
tFtime from a 0.35 0.5 0.7 0.5 1 2 ms
VI(SNS) = 1.5 V IL= 500 mA; see
disable Figure 1(a).
TJ= 125°C,
CL= 10 μF,
IN1 to IN2 transition, IL= 500 mA; measure
Transition VI(IN1) = 3.3 V, transition time as 10%
tT40 60 40 60 μs
time VI(IN2) = 5 V, to 90% rise time or
VI(EN) = 0 V from 3.4 V to 4.8 V on
VO(OUT). See
Figure 1(b).
Turn-on VI(IN1) = VI(IN2) = 5 V TJ= 25°C,
propagation Measured from enable to CL= 10 μF,
tPLH1 0.5 1 ms
delay from an 10% of VO(OUT), VI(SNS) = IL= 500 mA; see
enable 1.5 V Figure 1(a).
Turn-off VI(IN1) = VI(IN2) = 5 V TJ= 25°C,
propagation Measured from disable to CL= 10 μF,
tPHL1 3 5 ms
delay from a 90% of VO(OUT), VI(SNS) = IL= 500 mA; see
disable 1.5 V Figure 1(a).
Logic 1 to Logic 0
transition on VSNS,
Switch-over TJ= 25°C,
VI(IN1) = 1.5 V,
rising CL= 10 μF,
tPLH2 VI(IN2) = 5 V, 40 100 40 100 μs
propagation IL= 500 mA; see
VI(EN) = 0 V,
delay Figure 1(c).
Measured from VSNS to
10% of VO(OUT)
Logic 0 to Logic 1
transition on VSNS,
Switch-over TJ= 25°C,
VI(IN1) = 1.5 V,
falling CL= 10 μF,
tPHL2 VI(IN2) = 5 V, 2 3 10 2 5 10 ms
propagation IL= 500 mA; see
VI(EN) = 0 V,
delay Figure 1(c).
Measured from VSNS to
90% of VO(OUT)
Copyright © 2004–2012, Texas Instruments Incorporated 5
‘5‘ TEXAS INSTRUMENTS
(c)
1.5V 1.85V
4.65V
5V
VO(OUT)
tPLH2 tPHL2
VSNS
Switch#1Enabled Switch#1EnabledSwitch#2Enabled
(b)
3.3V
5V
4.8V
3.4V
VO(OUT)
tT
VSNS
Switch#1Enabled Switch#2Enabled
10%
90% 90%
10%
tR
VO(OUT)
tPLH1 tPHL1
tF
0V
EN
SwitchOff
SwitchOff SwitchEnabled
(a)
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
TIMING WAVEFORMS
Figure 1. Propagation Delays and Transition Timing Waveforms
6Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS flflflfl HUUU
IN1
IN2
OUT
GND
6
7
8
5
4
STAT
EN
VSNS
ILIM
GND
1
2
3
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
DEVICE INFORMATION
TRUTH TABLE
EN VI(VSNS) > 0.8 V(1) VI(IN2) > VI(IN1) STAT OUT(2)
0 Yes X 0 IN1
0 No No 0 IN1
0 No Yes Hi-Z IN2
1 X X 0 Hi-Z
(1) X = Don’t care.
(2) The undervoltage lockout circuit causes the output (OUT) to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal VDD UVLO.
PIN CONFIGURATIONS
PW PACKAGE DRB PACKAGE
TSSOP-8 SON-8
(TOP VIEW) (TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
TTL- and CMOS-compatible input with a 1-μA pull-up. The Truth Table illustrates the
EN 2 I functionality of EN.
GND 5 Power Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
IN1 8 I the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
IN2 6 I above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
A resistor (RILIM) from ILIM to GND sets the current limit (IL) to 250/RILIM and 500/RILIM for
ILIM 4 I the TPS2112A and TPS2113A, respectively.
OUT 7 O Power switch output
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1
STAT 1 O switch is ON or if OUT is Hi-Z (that is, EN is equal to logic '0')
An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V.
VSNS 3 I Otherwise, the FET connects OUT to the higher of IN1 and IN2. The Truth Table illustrates
the functionality of VSNS.
DRB package only. Connect to GND. Must be connected to large copper area in order to
Pad — Power meet stated package dissipation ratings.
Copyright © 2004–2012, Texas Instruments Incorporated 7
,,,,,,,,,,,,,,
Thermal
Sense
Charge
Pump
Q ison
2
Q ison
2
Q ison
1
UVLO(V )
DD
UVLO(IN2)
UVLO(IN1)
VI(SNS) >0.8V
VO(OUT) >VI(INx)
EN2 EN1
Control
Logic
+
+
100mV
0.8V
0.6V
Cross-Conduction
Detector
0.5V
k IO(OUT)
´
IO(OUT)
TPS2112A:k=0.2%
TPS2113A:k=0.1%
IN2
UVLO
VDD
UVLO
IN1
UVLO
V =0V
fV =0V
f
1 AmInternal VDD
IN1 8
IN2 6
EN 2
VSNS 3
GND 5
IN1
IN2
EN1
Q1
Q2
4
7OUT
ILIM
STAT
1
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
8Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
V
2V/div
I(VSNS)
V
2V/div
O(OUT)
OUTPUTSWITCHOVERRESPONSE
OutputSwitchoverResponseTestCircuit
t Time 1ms/div--
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
0.1 Fm
5V
3.3V
400 W
f=28Hz
22%DutyCycle
1 Fm
NC
V
2V/div
I( )EN
V
2V/div
O(OUT)
OUTPUTTURN-ONRESPONSE
t Time 2ms/div-- OutputTurn-OnResponseTestCircuit
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
1 Fm
0.1 Fm
5V
400 W
f=28Hz
78%DutyCycle NC
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS
Figure 2.
Figure 3.
Copyright © 2004–2012, Texas Instruments Incorporated 9
l TEXAS INSTRUMENTS
V
2V/div
I(VSNS)
V
2V/div
O(OUT)
t Time 40 s/div- m-
OUTPUTSWITCHOVERVOLTAGEDROOP
CL=1 Fm
CL=0 Fm
OutputSwitchoverVoltageDroopTestCircuit
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
1kW
0.1 Fm
0.1 Fm
5V
400 W
f=580Hz
90%DutyCycle
CL
NC
SW1
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 4.
Note: To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the 5-V supply, and then turn on switch
SW1.
10 Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS U W
TPS2112A
TPS2113A
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SBVS045C –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
Figure 5.
Note: To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the VIsupply, and then turn on switch
SW1.
Copyright © 2004–2012, Texas Instruments Incorporated 11
l TEXAS INSTRUMENTS
V
2V/div
I(IN1)
V
2V/div
O(OUT)
AutoSwitchoverVoltageDroopTestCircuit
t Time 250 s/div- m-
AUTOSWITCHOVERVOLTAGEDROOP
75%lessoutputvoltage
droopcomparedtoTPS2113
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
0.1 Fm
5V
400 W
1kW
f=220Hz
20%DutyCycle
10 Fm
3.3V
VOUT
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
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TYPICAL CHARACTERISTICS (continued)
Figure 6.
12 Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
INRUSHCURRENT
vs
LOADCAPACITANCE
300
250
200
150
100
50
0
0 40 80 100
C LoadCapacitance F- - m
L
VI=5V
VI=3.3V
20 60
I InrushCurrent mA- -
I
OutputCapacitorInrushCurrentTestCircuit
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
VI
400 W
f=28Hz
90%DutyCycle
0.1 Fm1 Fm10 Fm47 Fm100 Fm
NC ToOscilloscope
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
Figure 7.
Copyright © 2004–2012, Texas Instruments Incorporated 13
l TEXAS INSTRUMENTS
180
160
140
120
100
80
60
r Switch-OnResistance m- W
DS(on) -
-50 0 50 100 150
T JunctionTemperature C- -
J°
TPS2112A
TPS2113A
120
115
110
105
100
95
90
85
80
r Switch-OnResistance m- W
DS(on) -
2 3 4 5 6
V SupplyVoltage V- -
I(INx)
TPS2113A
TPS2112A
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
I IN1SupplyCurrent A- - m
I(IN1)
2 3 4 5 6
V IN1SupplyVoltage V
I(IN1) - -
DeviceDisabled
V =0V
I =0A
I(IN2)
O(OUT)
60
58
56
54
52
50
48
46
44
42
40
I IN1SupplyCurrent A- - m
I(IN1)
2 3 4 5 6
V SupplyVoltage V
I(IN1) - -
IN1SwitchisOn
V =0V
I =0A
I(IN2)
O(OUT)
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE
vs vs
JUNCTION TEMPERATURE SUPPLY VOLTAGE
Figure 8. Figure 9.
IN1 SUPPLY CURRENT IN1 SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11.
14 Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
-50 0 50 100 150
T JunctionTemperature C- -
J°
1.2
1.0
0.8
0.6
0.4
0.2
0
I SupplyCurrent A- - m
I(INx)
DeviceDisabled
V =5.5V
V =3.3V
I =0A
I(IN1)
I(IN2)
O(OUT)
I =3.3V
I(IN2)
I =5.5V
I(IN1)
-50 0 50 100 150
T JunctionTemperature C- -
J°
I SupplyCurrent A- - m
I(INx)
IN1SwitchisOn
V =5.5V
V =3.3V
I =0A
I(IN1)
I(IN2)
O(OUT)
II(IN2)
II(IN1)
80
70
60
50
40
30
20
10
0
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 12. Figure 13.
Copyright © 2004–2012, Texas Instruments Incorporated 15
l TEXAS INSTRUMENTS “H% 0—H,
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4
RILIM
0.1 Fm
0.1 Fm
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
R2
R1
R3
Switch
Status
RL
CL
TPS2113A
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4RL
RILIM
CL
0.1 Fm
0.1 Fm
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
R1
Switch
Status
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS2112A/3A will select the higher of the two supplies. This usually
means that the TPS2112A/3A will swap to IN2.
Figure 14. Auto-Selecting for a Dual Power-Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the VSNS logic signal. OUT
connects to IN1 if VSNS is logic '1'; otherwise, OUT connects to IN2 if VIN2 is greater than VIN1. The logic
thresholds for the VSNS terminal are compatible with both TTL and CMOS logic.
Figure 15. Manually Switching Power Sources
16 Copyright © 2004–2012, Texas Instruments Incorporated
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
www.ti.com
SBVS045C –MARCH 2004–REVISED MAY 2012
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
The TPS2112A/3A only supports the auto-switching mode. In this mode, OUT connects to IN1 if VI(VSNS) is
greater than 0.8 V, otherwise OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75% to 7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-
input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the
output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2112A and
TPS2113A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2112A/3A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see the Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS2112A/3A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
Copyright © 2004–2012, Texas Instruments Incorporated 17
l TEXAS INSTRUMENTS
TPS2112A
TPS2113A
SBVS045C –MARCH 2004–REVISED MAY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2010) to Revision C Page
• Changed description of power supplies in Description section ............................................................................................ 1
• Changed Current Limit Adjustment Range parameter TPS2113A and TPS2115A specifications in Available Options
table ...................................................................................................................................................................................... 2
• Added IOUT column to Device Information table, changed table name ................................................................................. 2
• Changed Continuous output current parameter in Absolute Maximum Ratings table .......................................................... 2
• Changed Current limit adjustment range parameter in Recommended Operating Conditions table ................................... 3
• Added footnote 1 to Recommended Operating Conditions table ......................................................................................... 3
• Changed second paragraph in Application Information section ......................................................................................... 16
Changes from Revision A (February, 2006) to Revision B Page
• Updated document to current format .................................................................................................................................... 1
• Deleted package information from Available Options table .................................................................................................. 2
• Revised Ordering Information table ...................................................................................................................................... 2
• Deleted storage temperature,operating virtual junction temperature range, and lead temperature specifications
from, added electrostatic discharge and junction temperature specifications to Absolute Maximum Ratings table;
deleted ESD Protection table ................................................................................................................................................ 2
• Added DRB package information and footnote to Dissipation Ratings table ....................................................................... 2
18 Copyright © 2004–2012, Texas Instruments Incorporated
TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 14-Nov-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS2112APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2112A
TPS2112APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2112A
TPS2113ADRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PTOI
TPS2113ADRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PTOI
TPS2113APW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2113A
TPS2113APWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2113A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Nov-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2112APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2113ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2113ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2113APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2112APWR TSSOP PW 8 2000 356.0 356.0 35.0
TPS2113ADRBR SON DRB 8 3000 367.0 367.0 35.0
TPS2113ADRBT SON DRB 8 250 210.0 185.0 35.0
TPS2113APWR TSSOP PW 8 2000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS2112APW PW TSSOP 8 150 530 10.2 3600 3.5
TPS2113APW PW TSSOP 8 150 530 10.2 3600 3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW DRB 8 VSON - 1 mm max heigfl PLASTIC SMALL OUTLINE , N0 LEAD Images above are JUSI a representation of me package family, aclual package may vary. Refer lo the product data sheel for package details, 4203462/L ' TEXAS INSTRUMENTS
SM“ 1 w““‘+“‘ \\
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
2.4 0.05
2X
1.95
1.65 0.05
6X 0.65
1 MAX
8X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
T» h
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(2.4)
(2.8)
6X (0.65)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
8X (0.6)
(R0.05) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.3)
8X (0.6)
(1.47)
(1.06)
(2.8)
(0.63)
6X (0.65)
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
45
8
METAL
TYP
SYMM
PW0008A '
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
PW0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PW0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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