Fiche technique pour LTC1412 de Analog Devices Inc.

L7L|nl I‘D LTC1412 TECHNOLOGY [7
1
LTC1412
12-Bit, 3Msps,
Sampling A/D Converter
The LTC
®
1412 is a 12-bit, 3Msps, sampling A/D con-
verter. This high performance device includes a high
dynamic range sample-and-hold and a precision refer-
ence. Operating from ±5V supplies it draws only 150mW.
The ±2.5V input range is optimized for low noise and low
distortion. Most high performance op amps also perform
best over this range, allowing direct coupling to the analog
inputs and eliminating the need for special translation
circuitry. Outstanding AC performance includes 72dB
S/(N + D) and 82dB SFDR at the Nyquist input frequency
of 1.5MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 40MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has a high speed 12-bit parallel output port. There
is no pipeline delay in the conversion results. A separate
convert start input and converter status signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors. A
digital output driver power supply pin allows direct con-
nection to 3V logic.
DESCRIPTION
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FEATURES
TYPICAL APPLICATION
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12-BIT ADC
12
5V OPTIONAL
3V LOGIC
SUPPLY
10µF
AV
DD
DV
DD
OV
DD
OGND
1412 TA01
DGND
D11 (MSB)
D0 (LSB)
BUSY
S/H
BUFFER
LTC1412
4.0625V
2k
–5V
2.5V
REFERENCE TIMING AND
LOGIC
OUTPUT
BUFFERS
•
•
•
CS
CONVST
AGNDV
SS
10µF
10µF
V
REF
COMP
A
IN–
A
IN+
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
INPUT FREQUENCY (Hz)
2
EFFECTIVE NUMBER OF BITS
4
6
8
10
1k 100k 1M 10M
1412 G01
010k
12
S/(N + D) (dB)
62
74
56
68
■
Telecommunications
■
Digital Signal Processing
■
Mulitplexed Data Acquisition Systems
■
High Speed Data Acquisition
■
Spectrum Analysis
■
Imaging Systems
APPLICATIONS
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Sample Rate: 3Msps
■
72dB S/(N + D) and 82dB SFDR at Nyquist
■
±0.35LSB INL and ±0.25LSB DNL (Typ)
■
Power Dissipation: 150mW
■
External or Internal Reference Operation
■
True Differential Inputs Reject Common Mode Noise
■
40MHz Full Power Bandwidth Sampling
■
±2.5V Bipolar Input Range
■
No Pipeline Delay
■
28-Pin SSOP Package
HBSOLUTE flXI U flflTl G 33333333333333 CCCCCCCCEEEEEE
2
LTC1412
ABSOLUTE MAXIMUM RATINGS
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PACKAGE/ORDER INFORMATION
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AVDD = DVDD = VDD (Notes 1, 2)
Supply Voltage (V
DD
)................................................. 6V
Negative Supply Voltage (V
SS
) ................................ –6V
Total Supply Voltage (V
DD
to V
SS
) .......................... 12V
Analog Input Voltage
(Note 3) .........................(V
SS
– 0.3V) to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ..........(V
SS
– 0.3V) to 10V
Digital Output Voltage........(V
SS
– 0.3V) to (V
DD
+ 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1412C ............................................... 0°C to 70°C
LTC1412I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
T
JMAX
= 110°C, θ
JA
= 95°C/ W
Consult factory for Military grade parts.
LTC1412CG
LTC1412IG
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 9) 4.75V ≤ V
DD
≤ 5.25V, –5.25V ≤ V
SS
≤ –4.75V ●±2.5 V
I
IN
Analog Input Leakage Current CS = High ●±1µA
C
IN
Analog Input Capacitance Between Conversions 10 pF
During Conversions 4 pF
t
ACQ
Sample-and-Hold Acquisition Time ●20 50 ns
t
AP
Sample-and-Hold Aperture Delay Time –0.5 ns
t
jitter
Sample-and-Hold Aperture Delay Time Jitter 1 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio –2.5V < (A
IN–
= A
IN
) < 2.5V 63 dB
With internal reference (Notes 5, 6)
CCHARA TERISTICS
CO
U
VERTER
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●12 Bits
Integral Linearity Error (Note 7) ●±0.35 ±1 LSB
Differential Linearity Error ●±0.25 ±1 LSB
Offset Error (Note 8) ±2±6 LSB
●±8 LSB
Full-Scale Error ±15 LSB
Full-Scale Tempco I
OUT(REF)
= 0 ●±15 ppm/°C
PUT
U
IA
A
U
LOG
(Note 5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
IN+
A
IN–
V
REF
REFCOMP
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
AV
DD
DV
DD
V
SS
BUSY
CS
CONVST
OGND
OV
DD
DV
DD
DGND
D0
D1
D2
D3
3
LTC1412
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 72.5 dB
1.465MHz Input Signal 70 72 dB
THD Total Harmonic Distortion 100kHz Input Signal, First 5 Harmonics –90 dB
1.465MHz Input Signal, First 5 Harmonics –80 dB
SFDR Spurious Free Dynamic Range 1.465MHz Input Signal 82 dB
IMD Intermodulation Distortion f
IN1
= 29.37kHz, f
IN2
= 32.446kHz –84 dB
Full Power Bandwidth 40 MHz
Full Linear Bandwidth S/(N + D) ≥ 68dB 4 MHz
ACCURACY
IC
DY
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W
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage (Note 10) 4.75 5.25 V
V
SS
Negative Supply Voltage (Note 10) –4.75 –5.25 V
I
DD
Positive Supply Current CS High ●12 16 mA
I
SS
Negative Supply Current CS High ●18 28 mA
P
D
Power Dissipation ●150 220 mW
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
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PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 2.480 2.500 2.520 V
V
REF
Output Tempco I
OUT
= 0 ±15 ppm/°C
V
REF
Line Regulation 4.75V ≤ V
DD
≤ 5.25V 0.01 LSB/V
–5.25V ≤ V
SS
≤ –4.75V 0.01 LSB/V
V
REF
Output Resistance 0.1mA ≤ I
OUT
≤ 0.1mA 2 kΩ
COMP Output Voltage I
OUT
= 0 4.06 V
POWER REQUIRE E TS
W
U
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 1.4 pF
V
OH
High Level Output Voltage V
DD
= 4.75V, I
O
= –10µA 4.75 V
V
DD
= 4.75V, I
O
= –200µA●4.0 4.71 V
V
OL
Low Level Output Voltage V
DD
= 4.75V, I
O
= 160µA 0.05 V
V
DD
= 4.75V, I
O
= 1.6mA ●0.10 0.4 V
I
OZ
Hi-Z Output Leakage D11 to D0 V
OUT
= 0V to V
DD
, CS High ●±10 µA
C
OZ
Hi-Z Output Capacitance D11 to D0 CS High (Note 9) 7 pF
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
(Note 5)
DIGITAL I PUTS AND OUTPUTS
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4
LTC1412
TI I G CHARACTERISTICS
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(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency ●3 MHz
t
THROUGHPUT
Throughput Time (Acquisition + Conversion) ●333 ns
t
CONV
Conversion Time ●240 283 ns
t
ACQ
Acquisition Time ●20 50 ns
t
1
CS↓ to CONVST↓ Setup Time (Notes 9, 10) ●5ns
t
2
CONVST Low Time (Note 10) ●20 ns
t
3
CONVST to BUSY Delay C
L
= 25pF 5 ns
●20 ns
t
4
Data Ready Before BUSY↑–20 0 20 ns
●–25 25 ns
t
5
Delay Between Conversions (Note 10) ●50 ns
t
6
Data Access Time After CS↓C
L
= 25pF 10 35 ns
●45 ns
t
7
Bus Relinquish Time 830 ns
LTC1412C ●35 ns
LTC1412I ●40 ns
t
8
CONVST High Time ●20 ns
t
9
Aperture Delay of Sample-and-Hold –1 ns
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4: When these pin voltages are taken below V
SS
they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 3MHz and t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended A
IN
input with A
IN–
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
TI I G DIAGRA
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DATA (N – 1)
DB11 TO DB0
CONVST
BUSY
CS
1412 TD
t
2
t
CONV
t
3
t
1
t
5
t
4
t
6
t
7
DATA N
DB11 TO DB0 DATA (N + 1)
DB11 TO DB0
DATA
5
LTC1412
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT FREQUENCY (Hz)
10
–120
DISTORTION (dB)
–40
–20
0
100 1k 10k
1412 G03
–60
–80
–100 3RD
THD
2ND
Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
INPUT FREQUENCY (Hz)
2
EFFECTIVE NUMBER OF BITS
4
6
8
10
1k 100k 1M 10M
1412 G01
010k
12
S/(N + D) (dB)
62
74
56
68
S/(N + D) and Effective Number of
Bits vs Input Frequency
FREQUENCY (Hz)
10K
–60
SPURIOUS-FREE DYNAMIC RANGE (dB)
–50
–40
–30
–20
100K 1M 10M
1412 G04
–70
–80
–90
–100
–10
0
Signal-to-Noise Ratio
vs Input Frequency
INPUT FREQUENCY (Hz)
10k
40
SIGNAL-TO-NOISE RATIO (dB)
60
80
100k 1M 10M
1412 G02
20
30
50
70
10
0
Integral Nonlinearity
vs Output Code
OUTPUT CODE
0
–1.0
INL (LSBs)
–0.5
0
0.5
1.0
512 1024 1536 2048
1412 G07
2560 3072 3584 4096
Intermodulation Distortion Plot
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–110
AMPLITUDE (dB)
–100
–80
–70
–90
–60
–50
–40
–30
0
1412 G05
–20
–10 fSMPL = 3MHz
fIN1 = 85.693359kHz
fIN2 = 114.990234kHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
–1.0
DNL (LSBs)
–0.5
0
0.5
1.0
512 1024 1536 2048
1412 G06
2560 3072 3584 4096
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–120
AMPLITUDE (dB)
–100
–80
–60
–40
0
1412 F02a
–20
fSMPL = 3Msps
fIN = 97.412kHz
SFDR = 93.3dB
SINAD = 73dB
Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–120
AMPLITUDE (dB)
–100
–80
–60
–40
0
1412 F02B
–20
fSMPL = 3Msps
fIN = 1.419kHz
SFDR = 83dB
SINAD = 72.5dB
SNR = 73db
Nonaveraged, 4096 Point FFT,
Input Frequency = 1.45kHz
6
LTC1412
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RIPPLE FREQUENCY (Hz)
–80
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
–40
0
–100
–60
–20
10k 100k 1M 10M
1412 G08
–1201k
VSS VDD
DGND
Power Supply Feedthrough
vs Ripple Frequency
INPUT FREQUENCY (Hz)
20
COMMON MODE REJECTION (dB)
40
50
70
80
1k 100k 1M 10M
1412 G09
010k
60
30
10
Input Common Mode Rejection
vs Input Frequency
PIN FUNCTIONS
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A
IN+
(Pin 1):
Positive Analog Input. ±2.5V input range
when A
IN–
is grounded. ±2.5V differential if A
IN–
is
driven.
A
IN–
(Pin 2): Negative Analog Input. Can be grounded or
driven differentially with A
IN+
.
V
REF
(Pin 3): 2.5V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Bypass Pin.
Bypass to AGND with 10µF ceramic (or 10µF tantalum in
parallel with 0.1µF ceramic).
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
DGND (Pin 19): Digital Ground for Internal Logic.
DV
DD
(Pin 20): 5V Positive Supply. Tie to Pin 28. Bypass
to AGND with 0.1µF ceramic.
OV
DD
(Pin 21):
Positive Supply for the Output Drivers. Tie
to Pin 28 when driving 5V logic. Tie to 3V when driving
3V logic.
OGND (Pin 22): Digital Ground for the Output Drivers.
CONVST (Pin 23): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. This input must be low for the
ADC to recognize the CONVST inputs.
BUSY (Pin 25): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
V
SS
(Pin 26): –5V Negative Supply. Bypass to AGND with
10µF ceramic (or 10µF tantalum in parallel with 0.1µF
ceramic).
DV
DD
(Pin 27): 5V Positive Supply. Tie to Pin 28.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND with
10µF ceramic (or 10µF tantalum in parallel with 0.1µF
ceramic).
fit 3?? L7 Lam/“5‘2
7
LTC1412
FUNCTIONAL BLOCK DIAGRA
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12-BIT CAPACITIVE DAC COMPREF AMP
2.5V REF
2k
REFCOMP
(4.06V)
C
SAMPLE
C
SAMPLE
•
•
•
D11
D0
BUSY
CONTROL LOGIC
INTERNAL
CLOCK
CONVST CS
ZEROING SWITCHES
OV
DD
OGND
AV
DD
DV
DD
A
IN+
A
IN–
V
REF
AGND
DGND
12
1412 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER OUTPUT
LATCHES
TEST CIRCUITS
1k CLCL
DBN
A) HI-Z TO VOH AND VOL TO VOH
DBN
1k
5V
B) HI-Z TO VOL AND VOH TO VOL
1412 TC01
1k 100pF
DBN
A) V
OH
TO HI-Z
100pF
DBN
1k
5V
B) V
OL
TO HI-Z
1412 TC02
Load Circuits for Access Timing Load Circuits for Output Float Delay
APPLICATIONS INFORMATION
WUUU
Conversion Details
The LTC1412 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the A
IN+
and A
IN–
inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 50ns will provide enough time for the
4.. A %># a 7;. kg,
8
LTC1412
APPLICATIONS INFORMATION
WUUU
COMP
C
SAMPLE+
C
DAC–
•
•
•
D11
D0
ZEROING SWITCHES
HOLD
HOLD
A
IN+
A
IN–
C
DAC+
C
SAMPLE–
12
1412 F01
+
–
OUTPUT
LATCHES
V
DAC+
V
DAC–
HOLD
SAMPLE
SAMPLE
HOLD
SAR
Figure 1. Simplified Block Diagram
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–120
AMPLITUDE (dB)
–100
–80
–60
–40
0
1412 F02a
–20
f
SMPL
= 3Msps
f
IN
= 97.412kHz
SFDR = 93.3dB
SINAD = 73dB
Figure 2a. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–120
AMPLITUDE (dB)
–100
–80
–60
–40
0
1412 F02B
–20
f
SMPL
= 3Msps
f
IN
= 1.419kHz
SFDR = 83dB
SINAD = 72.5dB
SNR = 73db
Figure 2b. LTC1412 Nonaveraged, 4096 Point FFT,
Input Frequency = 1.45MHz
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 3MHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 1.5MHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 3MHz the LTC1412 maintains near ideal ENOBs up
to the Nyquist input frequency of 1.5MHz. Refer to
Figure␣ 3.
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
SAMPLE
capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the A
IN+
and A
IN–
input
charges. The SAR contents (a 12-bit data word) which
represents the difference of A
IN+
and A
IN–
are loaded into
the 12-bit output latches.
Dynamic Performance
The LTC1412 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1412 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
9
LTC1412
APPLICATIONS INFORMATION
WUUU
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
IMD f f f
Amplitude at
ab b
+
()
=±
()
20 log Amplitude at f
f
a
a
INPUT FREQUENCY (Hz)
2
EFFECTIVE NUMBER OF BITS
4
6
8
10
1k 100k 1M 10M
1412 G01
010k
12
S/(N + D) (dB)
62
74
56
68
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1412 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD VV
=+++
20
3
24
2
log V . . .V
V
2
2n
2
1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1412 has good distortion
performance up to the Nyquist frequency and beyond.
INPUT FREQUENCY (Hz)
10
–120
DISTORTION (dB)
–40
–20
0
100 1k 10k
1412 G03
–60
–80
–100 3RD
THD
2ND
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
FREQUENCY (kHz)
0 200 400 600 800 1000 1200 1400
–110
AMPLITUDE (dB)
–100
–80
–70
–90
–60
–50
–40
–30
0
1412 G05
–20
–10 f
SMPL
= 3MHz
f
IN1
= 85.693359kHz
f
IN2
= 114.990234kHz
Figure 5. Intermodulation Distortion Plot
10
LTC1412
APPLICATIONS INFORMATION
WUUU
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1412 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the A
IN–
input is grounded). The A
IN+
and
A
IN–
inputs are sampled at the same instant. Any unwanted
signal that is common mode to both inputs will be reduced
by the common mode rejection of the sample-and-hold
circuit. The inputs draw only one small current spike while
charging the sample-and-hold capacitors at the end of
conversion. During conversion, the analog inputs draw
only a small leakage current. If the source impedance of
the driving circuit is low then the LTC1412 inputs can be
driven directly. As source impedance increases so will
acquisition time (see Figure 6). For minimum acquisition
time, with high source impedance, a buffer amplifier must
be used. The only requirement is that the amplifier driving
the analog input(s) must settle after the small current
spike before the next conversion starts (settling time must
be 50ns for full throughput rate).
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
The best choice for an op amp to drive the LTC1412 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica-
tions are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1412. More detailed information is
available in the Linear Technology Databooks and on the
LinearView
TM
CD-ROM.
LT
®
1223: 100MHz Video Current Feedback Amplifier.
6mA supply current. ±5V to ±15V supplies. Low Noise.
Good for AC applications.
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current. ±5V to ±15V supplies. Low Noise. Best for
AC applications.
LT1229/LT1230: Dual and Quad 100MHz Current Feed-
back Amplifiers. ±2V to ±15V supplies. Low Noise. Good
AC specifications, 6mA supply current each amplifier.
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA sup-
ply current. ±5V to ±15V supplies. Good AC and DC
specifications. 70ns settling to 0.5LSB.
LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply cur-
rent. Good AC and DC specifications. 60ns settling to
0.5LSB.
LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op
Amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1412 noise and distortion. The small-signal band-
SOURCE RESISTANCE (Ω)
10
0.01
ACQUISITION TIME (µs)
0.1
1
10
100 1k
1412 F06
10k 100k
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth LinearView is a trademark of Linear Technology Corporation.
T}; 5.. 0;ng
11
LTC1412
APPLICATIONS INFORMATION
WUUU
width of the sample-and-hold circuit is 40MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
For example, Figure 7 shows a 500pF capacitor from A
IN+
to ground and a 100Ω source resistor to limit the input
bandwidth to 3.2MHz. The 500pF capacitor also acts as a
charge reservoir for the input sample-and-hold and iso-
lates the ADC input from sampling glitch-sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO and
silver mica type dielectric capacitors have excellent linear-
ity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resis-
tors are much less susceptible to both problems.
When high amplitude unwanted signals are close in
frequency to the desired signal frequency, a multiple pole
filter is required. Figure 7b shows a simple implementa-
tion using an LTC1560-1 fifth-order elliptic continuous
time filter.
Input Range
The ±2.5V input range of the LTC1412 is optimized for low
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the ana-
log inputs and eliminating the need for special translation
circuitry.
Some applications may require other input ranges. The
LTC1412 differential inputs and reference circuitry can ac-
commodate other input ranges often with little or no addi-
tional circuitry. The following sections describe the reference
and input circuitry and how they affect the input range.
Internal Reference
The LTC1412 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at V
REF
(Pin 3), see Figure 8a. A
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other cir-
cuitry, see Figure 8b. The reference amplifier gains the
voltage at the V
REF
pin by 1.625 to create the required
internal reference voltage. This provides buffering be-
tween the V
REF
pin and the high speed capacitive DAC. The
reference amplifier compensation pin, REFCOMP (Pin 4)
must be bypassed with a capacitor to ground. The refer-
ence amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 10µF ceramic or 10µF
tantalum in parallel with a 0.1µF ceramic is recommended.
Figure 7b. 1MHz Fifth-Order Elliptic Lowpass Filter
LTC1412
A
IN+
A
IN–
V
REF
REFCOMP
AGND
LTC1560-1
1412 F07b
1
2
3
4
1
2
3
4
8
7
6
5
5
10µF
V
IN
–5V 5V
0.1µF 0.1µF
Figure 7a. RC Input Filter
LTC1412
A
IN+
A
IN–
V
REF
REFCOMP
AGND
1412 F07a
1
2
3
4
5
10µF
500pF
100Ω
ANALOG INPUT
Figure 8a. LTC1412 Reference Circuit
R2
40k
R3
64k
REFERENCE
AMP
10µF
REFCOMP
AGND
V
REF
R1
2k
3
4
5
2.500V
4.0625V
LTC1412
1412 F08a
BANDGAP
REFERENCE
D‘F
12
LTC1412
APPLICATIONS INFORMATION
WUUU
LTC1412
A
IN+
ANALOG INPUT
5V A
IN–
V
REF
REFCOMP
AGND
1412 F08b
1
2
3
4
5
10µF
V
IN
V
OUT
LT1019A-2.5
RIPPLE FREQUENCY (Hz)
–80
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
–40
0
–100
–60
–20
10k 100k 1M 10M
1412 G08
–1201k
V
SS
V
DD
DGND
mode voltage. THD will degrade as the inputs approach
either power supply rail, from –86dB with a common
mode of 0V to –75dB with a common mode of 2.5V
or –2.5V.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1412. The code transitions occur midway between
successive integer LSB values (i.e., –FS/2 + 0.5LSB,
–FS/2 + 1.5LSB, –FS/2 + 2.5LSB,...FS/2 – 1.5LSB, FS/2 –
0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/4096 = 5V/4096 = 1.22mV.
Differential Inputs
The LTC1412 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of A
IN+
– (A
IN–
) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 10. The
only requirement is that both inputs cannot exceed the
AV
DD
or AV
SS
power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the A
IN–
input. For zero offset error apply
Figure 10. CMRR vs Input Frequency
Figure 8b. Using the LT1019-2.5 as an External Reference
The V
REF
pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1412 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
LTC1412
A
IN+
ANALOG INPUT
1.25V TO 3V
DIFFERENTIAL A
IN–
V
REF
REFCOMP
AGND
1412 F09
1
2
3
4
5
10µF
LTC1450 1.25V TO 3V
Figure 9. Driving VREF with a DAC
INPUT VOLTAGE (V)
OUTPUT CODE
1412 F11a
111...111
111...110
111...101
000...000
000...001
000...010
FS – 1LSBFS – 1LSB
Figure 11a. LTC1412 Transfer Characteristics
3 _|A L7 Lflfl
13
LTC1412
APPLICATIONS INFORMATION
WUUU
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN+
and A
IN–
leads
will be rejected by the input CMRR. The A
IN–
input can be
used as a ground sense for the A
IN+
input; the LTC1412
will hold and convert the difference voltage between A
IN+
and A
IN–
. The leads to A
IN+
(Pin 1) and A
IN–
(Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A
IN+
and A
IN–
traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the V
DD
and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10µF tantalum capacitors
in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
Figure 12. Power Supply Grounding Practice
LTC1412
A
IN+
ANALOG INPUT
A
IN–
V
REF
REFCOMP
AGND
1412 F11b
1
2
3
R4
100Ω
R2
50k
R3
24k
–5V
R6
24k
R1
50k
R5
47k
4
5
10µF
Figure 11b. Offset and Full-Scale Adjust Circuit
–0.61mV (i.e., –0.5LSB) at A
IN+
and adjust the offset at
the A
IN–
input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to A
IN+
and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 19 and 14 (DGND) and Pin 22 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capaci-
tor and the DV
DD
bypass capacitor should also be con-
nected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
1412 F12
A
IN+
AGNDREFCOMP V
SS
AV
DD
LTC1412 DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
54
226
OV
DD
DV
DD
21 20, 2728
OGND
DGND
14, 19 22
POWER
SUPPLY
GROUND
1
0.1µF
A
IN–
0.1µF0.1µF
10µF
ANALOG GROUND PLANE
+
–+
10µF10µF
++
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14
LTC1412
APPLICATIONS INFORMATION
WUUU
OV
DD
OV
DD
–
+
E3
7V TO
15V
E2
GND
E4
OPTIONAL
A
+
A
–
V
CC
V
CC
V
SS
JP7 U1
LTC1412
B[00:11]
U6
74HC574
U7
74HC574
56
U5F
74HC14
U5C
74HC14 9 8 RDY
U5D
74HC14
D11
D1
D3
D5
D7
D9
D11
D10
D8
D6
D4
D2
D0
D11
JP1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D[0:11] R1, 1.2k
R2, 1.2k
R3, 1.2k
R4, 1.2k
R5, 1.2k
R6, 1.2k
R7, 1.2k
R9, 1.2k
R8, 1.2k
R10, 1.2k
R11, 1.2k
R12, 1.2k
11 10
U5E
74HC14
R13
1k
1213
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D10
D9
D8
D7
D6
D5
D4
D0
D1
D2
D3
D11
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0E
0E
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES 1/8W, 5% SMT
2. ALL CAPACITOR VALUES 50V, 20% SMT
V
SS
V
CC
CLK
J3
V
IN
U2
LT1121-5
U4
LT1175
D13
SS12
R17
10k
R18
10k
R19
51Ω
R16
51Ω
R15
51Ω
U5A
74HC14
JP8
U5B
74HC14
C6
470pF
C10
1µF
16V
C11
10µF
16V
C13
0.1µF
C20
15pF
C14
0.1µF
C1
22µF
10V
TAB GND
1
42
3
C2
0.1µF
C9
0.1µF
U3
LT1363
3
2
123 4
6
7
1
8
5
4
J1
J2
JP6
V
OUT
1
2
3
4
5
14
23
24
25
20
19
26
27
28
6
7
8
9
10
11
12
13
15
16
17
18
22
21
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B0
B1
B2
B3
B11
B10
B9
B8
B7
B6
B5
B4
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
OV
DD
+A
IN
–A
IN
V
REF
REFCOMP
AGND
DGND
CONVST
CS
BUSY
DV
DD
DGND
V
SS
DV
DD
AV
DD
JP5
V
CC
3.3V
3.3V
+
OV
DD
C5
10µF
10V
C4
0.1µF
+
1412 F13a
JP2
HEADER
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
C8
0.1µF
OV
DD
C7
0.1µF
GND
GND
12
+
C3
0.1µF
JP3
JP4
R14
20Ω
SHDN
INPUT
INPUT
LIM2
SENSE
OUT
LIM4
GND
1
8
4
3
27
65
E1
–7V TO
–15V
D14
SS12
+
C12
22µF
10V
V
SS
OV
DD
C19
0.1µF
U5
DECOUPLING
CLK
CLK
20
10
20
10
21
21
12
12
2
1
Figure 13a. LTC1412 Demonstration Board Features Analog Input Signal Buffer, 3Msps, Parallel Data Output 12-Bit ADC,
Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 16-Pin Header, P2
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15
LTC1412
APPLICATIONS INFORMATION
WUUU
Figure 13b. Component Side Silkscreen
Figure 13c. Component Side Figure 13d. Solder Side
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
u 337 7 0 our HHHHHHHHHHHHWT I canvas“ 0 \ HHHHHHHHHHHHHHi <¥n2usium‘, nueaiums="" ‘1="" ‘7}="" 7777777777777774,="" 5,="" a="" t'="" “mil,""hhh="" 7="" "00="" 0m="" ‘="" p="" ominous="" ominm="">
16
LTC1412
LINEAR TECHNOLOGY CORPORATION 1998
sn1412 1412fs LT/TP 0798 4K • PRINTED IN
USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
PART NUMBER RESOLUTION SPEED COMMENTS
16-Bit
LTC1604 16 333ksps ±2.5V Input Range, ±5V Supply
LTC1605 16 100ksps ±10V Input Range, Single 5V Supply
14-Bit
LTC1419 14 800ksps 150mW, 81.5dB SINAD and 95dB SFDR
LTC1416 14 400ksps 75mW, Low Power with Excellent AC Specs
LTC1418 14 200ksps 15mW, Single 5V, Serial/Parallel I/O
12-Bit
LTC1410 12 1.25Msps 150mW, 71.5dB SINAD and 84dB THD
LTC1415 12 1.25Msps 55mW, Single 5V Supply
LTC1409 12 800ksps 80mW, 71.5dB SINAD and 84dB THD
LTC1279 12 600ksps 60mW, Single 5V or ±5V Supply
LTC1404 12 600ksps High Speed Serial I/O in SO-8 Package
LTC1278-5 12 500ksps 75mW, Single 5V or ±5V Supply
LTC1278-4 12 400ksps 75mW, Single 5V or ±5V Supply
LTC1400 12 400ksps High Speed Serial I/O in SO-8 Package
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
RELATED PARTS
G28 SSOP 0694
0.005 – 0.009
(0.13 – 0.22)
0° – 8°
0.022 – 0.037
(0.55 – 0.95)
0.205 – 0.212**
(5.20 – 5.38)
0.301 – 0.311
(7.65 – 7.90)
12345678 9 10 11 12 1413
0.397 – 0.407*
(10.07 – 10.33)
2526 22 21 20 19 18 17 16 1523242728
0.068 – 0.078
(1.73 – 1.99)
0.002 – 0.008
(0.05 – 0.21)
0.0256
(0.65)
BSC 0.010 – 0.015
(0.25 – 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**