Fiche technique pour SM72482 de Texas Instruments

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I TEXAS INSTRUMENTS

OUT A

4 5

IN_A

VEE

IN_B

VCC

OUT_B

SM72482

www.ti.com

SNVS696C –JANUARY 2011–REVISED APRIL 2013

Dual 5A Compound Gate Driver

Check for Samples: SM72482

1FEATURES DESCRIPTION

The SM72482 Dual Gate Driver replaces industry

2• Renewable Energy Grade standard gate drivers with improved peak output

• Independently Drives Two N-Channel current and efficiency. Each “compound” output driver

MOSFETs stage includes MOS and bipolar transistors operating

• Compound CMOS and Bipolar Outputs Reduce in parallel that together sink more than 5A peak from

capacitive loads. Combining the unique

Output Current Variation characteristics of MOS and bipolar devices reduces

• 5A Sink, 3A Source Current Capability drive current variation with voltage and temperature.

• Two Channels Can be Connected in Parallel to Under-voltage lockout protection is also provided.

Double the Drive Current The drivers can be operated in parallel with inputs

and outputs connected to double the drive current

• Independent Inputs (TTL Compatible) capability. This device is available in the SOIC

• Fast Propagation Times (25 ns Typical) package.

• Fast Rise and Fall Times (14 ns Rise, 12 ns

Fall With 2 nF Load) Connection Diagram

• Available in Dual Noninverting, Dual Inverting,

and Combination Configurations

• Supply Rail Under-Voltage Lockout Protection

(UVLO)

• SM72482 UVLO Configured to Drive PFET

Through OUT_A and NFET Through OUT_B

• Pin Compatible With Industry Standard Gate

Drivers

• Packages

– SOIC

– Thermally Enhanced VSSOP

APPLICATIONS

• Synchronous Rectifier Gate Drivers Figure 1. 8-Lead SOIC or VSSOP

• Switch-mode Power Supply Gate Driver See D or DGN Package

• Solenoid and Motor Drivers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

l TEXAS INSTRUMENTS

SM72482

SNVS696C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

PIN DESCRIPTIONS

Pin Name Description Application Information

1 NC No Connect

2 IN_A ‘A’ side control input TTL compatible thresholds.

3 VEE Ground reference for both inputs and Connect to power ground.

outputs

4 IN_B ‘B’ side control input TTL compatible thresholds.

5 OUT_B Output for the ‘B’ side driver. Voltage swing of this output is from VCC to VEE. The output stage is

capable of sourcing 3A and sinking 5A.

6 VCC Positive output supply Locally decouple to VEE.

7 OUT_A. Output for the ‘A’ side driver. Voltage swing of this output is from VCC to VEE. The output stage is

capable of sourcing 3A and sinking 5A.

8 NC No Connect

Table 1. Configuration Table

Part Number “A” Output Configuration “B” Output Configuration Package

SM72482MY-1 Non-Inverting (Low in UVLO) Non-Inverting (Low in UVLO) VSSOP

SM72482MA-4 Inverting (High in UVLO) Non-Inverting (Low in UVLO) SOIC

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)

VCC to VEE −0.3V to 15V

IN to VEE −0.3V to 15V

Storage Temperature Range, (TSTG)−55°C to +150°C

Maximum Junction Temperature, (TJ(max)) +150°C

Operating Junction Temperature +125°C

ESD Rating 2kV

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

Electrical Characteristics

TJ=−40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

VCC Operating Range VCC−VEE 3.5 14 V

VCCR VCC Under Voltage Lockout (rising) VCC−VEE 2.3 2.9 3.5 V

VCCH VCC Under Voltage Lockout 230 mV

Hysteresis

ICC VCC Supply Current (ICC) IN_A = IN_B = 0V (SM72482MY-1) 1 2

IN_A = VCC, IN_B = 0V 1 2

(SM72482MA-4)

CONTROL INPUTS

VIH Logic High 2.2 V

VIL Logic Low 0.8 V

VthH High Threshold 1.3 1.75 2.2 V

VthL Low Threshold 0.8 1.35 2.0 V

HYS Input Hysteresis 400 mV

Product Folder Links: SM72482

*9 TEXAS INSTRUMENTS

INPUT

OUTPUT

tD1

tD2

90%

10%

50%

INPUT

OUTPUT

tD1

tD2

90%

10%

50%

SM72482

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SNVS696C –JANUARY 2011–REVISED APRIL 2013

Electrical Characteristics (continued)

TJ=−40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

IIL Input Current Low IN_A=IN_B=VCC −1 0.1 1

IIH Input Current High IN_A=IN_B=VCC(SM72482MY-1) 10 18 25 µA

IN_B=VCC (SM72482MA-4) 10 18 25

IN_A=VCC (SM72482MA-4) -1 0.1 1

OUTPUT DRIVERS

ROH Output Resistance High IOUT =−10 mA(1) 30 50 Ω

ROL Output Resistance Low IOUT = + 10 mA(1) 1.4 2.5 Ω

ISource Peak Source Current OUTA/OUTB = VCC/2, 3 A

200 ns Pulsed Current

ISink Peak Sink Current OUTA/OUTB = VCC/2, 5 A

200 ns Pulsed Current

SWITCHING CHARACTERISTICS

td1 Propagation Delay Time Low to CLOAD = 2 nF, see Figure 2 and 25 40 ns

High, IN rising (IN to OUT) Figure 3

td2 Propagation Delay Time High to CLOAD = 2 nF, see Figure 2 and 25 40 ns

Low, IN falling (IN to OUT) Figure 3

trRise Time CLOAD = 2 nF, see Figure 2 and 14 25 ns

Figure 3

tfFall Time CLOAD = 2 nF, see Figure 2 and 12 25 ns

Figure 3

LATCHUP PROTECTION

AEC - Q100, Method 004 TJ= 150°C 500 mA

THERMAL RESISTANCE

θJA Junction to Ambient, SOIC Package 170 °C/W

0 LFPM Air Flow VSSOP Package 60

θJC Junction to Case SOIC Package 70 °C/W

VSSOP Package 4.7

(1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and

Bipolar devices.

TIMING WAVEFORMS

Figure 2. Inverting Figure 3. Non-Inverting

Product Folder Links: SM72482

l TEXAS INSTRUMENTS

46 8 10 12 14 16

SUPPLY VOLTAGE (V)

17.5

22.5

27.5

32.5

TIME (ns)

tD2

tD1

TA = 25°C

CL = 2200pF

100 1k 10k

CAPACITIVE LOAD (pF)

TIME (ns)

TA = 25°C

VCC = 12V

-75 -50 -25 0 25 50 75 100 125 150 175

TIME (ns)

TEMPERATURE (°C)

VCC = 12V

CL = 2200pF

46910 12 13 16

TIME (ns)

SUPPLY VOLTAGE (V)

57811 14 15

TA = 25°C

CL = 2200pF

110 100 1000

FREQUENCY (kHz)

0.1

100

SUPPLY CURRENT (mA)

VCC = 15V

VCC = 10V

VCC = 5V

TA = 25°C

CL = 2200pF

100

10k

CAPACITIVE LOAD (pF)

0.1

1000

SUPPLY CURRENT (mA)

f = 500kHz

f = 100kHz

f = 10kHz

TA = 25°C

VCC = 12V

SM72482

SNVS696C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics

Supply Current vs Frequency Supply Current vs Capacitive Load

Figure 4. Figure 5.

Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature

Figure 6. Figure 7.

Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage

Figure 8. Figure 9.

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l TEXAS INSTRUMENTS \ //

-75 -50 -25 0 25 50 75 100 125 150 175

1.600

1.900

2.200

2.500

2.800

3.100

UVLO THRESHOLDS (V)

TEMPERATURE (°C)

0.150

0.210

0.270

0.330

0.450

0.390

HYSTERESIS (V)

VCCR

VCCF

VCCH

-75 -50 -25 0 25 50 75 100 125 150 175

17.5

22.5

27.5

32.5

TIME (ns)

TEMPERATURE (°C)

tD2

tD1

VCC = 12V

CL = 2200pF

03 6 9 12 15 18

SUPPLY VOLTAGE (V)

0.75

1.25

1.75

2.25

2.75

3.25

ROL (:)

ROH (:)

ROH

ROL

TA = 25°C

IOUT = 10mA

SM72482

www.ti.com

SNVS696C –JANUARY 2011–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Delay Time vs Temperature RDSON vs Supply Voltage

Figure 10. Figure 11.

UVLO Thresholds and Hysteresis vs Temperature

Figure 12.

Product Folder Links: SM72482

UVLO

VEE

IN_A

VCC

OUT_A

VEE

OUT_B

VEE

IN_B

SM72482

SNVS696C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

BLOCK DIAGRAM

Figure 13. Block Diagram of SM72482

Product Folder Links: SM72482

l TEXAS INSTRUMENTS

SM72482

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SNVS696C –JANUARY 2011–REVISED APRIL 2013

DETAILED OPERATING DESCRIPTION

The SM72482 dual gate driver consists of two independent and identical driver channels with TTL compatible

logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver

output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current

capability over a wide output voltage and operating temperature range. The bipolar device provides high peak

current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output

swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power

ground potential at the VEE pin.

The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The

SM72482 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver

applications.

The input stage of each driver should be driven by a signal with a short rise and fall time. Slow rising and falling

input signals, although not harmful to the driver, may result in the output switching repeatedly at a high

frequency.

The two driver channels of the SM72482 are designed as identical cells. Transistor matching inherent to

integrated circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical.

Closely matched propagation delays allow the dual driver to be operated as a single with inputs and output pins

connected. The drive current capability in parallel operation is precisely 2X the drive of an individual channel.

Small differences in switching speed between the driver channels will produce a transient current (shoot-through)

in the output stage when two output pins are connected to drive a single load. Differences in input thresholds

between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast

transition input signals are especially important while operating in a parallel configuration. The efficiency loss for

parallel operation has been characterized at various loads, supply voltages and operating frequencies. The

power dissipation in the SM72482 increases less than 1% relative to the dual driver configuration when operated

as a single driver with inputs/ outputs connected.

An Under Voltage Lock Out (UVLO) circuit is included in the SM72482, which senses the voltage difference

between VCC and the chip ground pin, VEE. When the VCC to VEE voltage difference falls below 2.8V both driver

channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver will

resume normal operation when the VCC to VEE differential voltage exceeds approximately 3.0V.

The SM72482MY –1 device hold both outputs in the low state in the under-voltage lockout (UVLO) condition. The

SM72482MA–4 has an active high output state of OUT_A during UVLO. When VCC is less than the UVLO

threshold voltage, OUT_A will be locked in the high state while OUT_B will be disabled in the low state. This

configuration allows the SM72482MY –4 to drive a PFET through OUT_A and an NFET through OUT_B with

both FETs safely turned off during UVLO.

Layout Considerations

Attention must be given to board layout when using SM72482. Some important considerations include:

1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support

high peak currents being drawn from VCC during turn-on of the MOSFET.

2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground

avoiding inductive loops. The two paths for returning current to ground are a) between SM72482 VEE pin and

the ground of the circuit that controls the driver inputs, b) between SM72482 VEE pin and the source of the

power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as

wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid

coupling between the high current output paths and the logic signals that drive the SM72482. A good method

is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.

3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current

carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the

SM72482.

4. The SM72482 footprint is compatible with other industry standard drivers including the TC4426/27/28 and

UCC27323/4/5.

5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE

or VCC to avoid spurious output signals.

Product Folder Links: SM72482

‘5‘ TEXAS INSTRUMENTS

VHIGH

VGATE

VTRIG CIN

SM72482

SNVS696C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

Thermal Performance

INTRODUCTION

The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below

a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJof IC

components in worst case operating conditions. The junction temperature is estimated based on the power

dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board

and environment. The θJA is not a given constant for the package and depends on the printed circuit board

design and the operating environment.

DRIVE POWER REQUIREMENT CALCULATIONS IN SM72482

The SM72482 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short

intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are

required to switch the MOSFET gate very quickly for operation at high frequencies.

The schematic above shows a conceptual diagram of the SM72482 output and MOSFET load. Q1 and Q2 are

the switches within the gate driver. RGis the gate resistance of the external MOSFET, and CIN is the equivalent

gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected.

The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to

source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants

and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge

QGin coloumbs. QGcombines the charge required by CGS and CGD for a given gate drive voltage VGATE.

Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is

approximated by

PDRIVER = VGATE x QGx FSW

where

• FSW = switching frequency of the MOSFET (1)

For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V.

The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching

frequency of 300 kHz and VGATE of 12V is equal to

PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. (2)

If both channels of the SM72482 are operating at equal frequency with equivalent loads, the total losses will be

twice as this value which is 0.216W.

In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output

transitions. When either output of the SM72482 changes state, current will flow from VCC to VEE for a very brief

interval of time through the output totem-pole N and P channel MOSFETs. The final component of power

dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input

stage and Under-voltage lockout sections.

Product Folder Links: SM72482

l TEXAS INSTRUMENTS

ISOURCE (MAX) :=

TJ(MAX) - TA

TJA · VDIODE

ISINK (MAX) := TJ(MAX) - TA

TJA · RDS (ON)

SM72482

www.ti.com

SNVS696C –JANUARY 2011–REVISED APRIL 2013

Characterization of the SM72482 provides accurate estimates of the transient and quiescent power dissipation

components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8

mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power.

Therefore the total power dissipation

PD= 0.216 + 0.008 + 0.012 = 0.236W. (3)

We know that the junction temperature is given by

TJ= PDxθJA + TA(4)

Or the rise in temperature is given by

TRISE = TJ−TA= PDxθJA (5)

For SOIC package, θJA is estimated as 170°C/W for the conditions of natural convection. For VSSOP, θJA is

typically 60°C/W.

Therefore for SOIC TRISE is equal to

TRISE = 0.236 x 170 = 40.1°C (6)

CONTINUOUS CURRENT RATING OF SM72482

The SM72482 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring

continuous load current (resistive or inductive loads), package power dissipation, limits the SM72482 current

capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when

sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be

calculated as:

where

• RDS(on) is the on resistance of lower MOSFET in the output stage of SM72482 (7)

Consider TJ(max) of 125°C and θJA of 170°C/W for an SOIC package under the condition of natural convection

and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the SM72482 output at TJ(max) is

2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents.

Similarly, the maximum continuous source current can be calculated as

where

• VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to

be about 1.1V at TJ(max) of 125°C (8)

Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA.

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l TEXAS INSTRUMENTS

SM72482

SNVS696C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 9

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I TEXAS INSTRUMENTS Sample: Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SM72482MA-4/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S482

SM72482MAE-4/NOPB ACTIVE SOIC D 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S482

SM72482MAX-4/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S482

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SM72482MAE-4/NOPB SOIC D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

SM72482MAX-4/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SM72482MAE-4/NOPB SOIC D 8 250 208.0 191.0 35.0

SM72482MAX-4/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SM72482MA-4/NOPB D SOIC 8 95 495 8 4064 3.05

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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