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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54428
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
TPS54428 4.5-V to 18-V Input, 4-A Synchronous Step-Down Converter With Eco-Mode™
1
1 Features
1• D-CAP2™ Mode Enables Fast Transient
Response
• Low Output Ripple and Allows Ceramic Output
Capacitor
• Wide VIN Input Voltage Range: 4.5 V to 18 V
• Output Voltage Range: 0.76 V to 7.0 V
• Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 70 mΩ(High Side) and 53 mΩ(Low Side)
• High Efficiency, Less Than 10 μA at Shutdown
• High Initial Bandgap Reference Accuracy
• Adjustable Soft Start
• Pre-Biased Soft Start
• 650-kHz Switching Frequency (fSW)
• Cycle By Cycle Over Current Limit
• Auto-Skip Eco-mode™ for High Efficiency at Light
Load
2 Applications
• Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
3 Description
The TPS54428 is an adaptive on-time D-CAP2™
mode synchronous buck converter.
The TPS54428 enables system designers to
complete the suite of various end-equipment power
bus regulators with a cost effective, low component
count, low standby current solution.
The main control loop for the TPS54428 uses the D-
CAP2™ mode control that provides a fast transient
response with no external compensation
components.
The adaptive on-time control supports seamless
transition between PWM mode at higher load
conditions and Eco-mode™ operation at light loads.
Eco-mode™ allows the TPS54428 to maintain high
efficiency during lighter load conditions.
The TPS54428 also has a proprietary circuit that
enables the device to adopt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
VIN input.
The output voltage can be programmed between
0.76 V and 7.0 V.
The device also features an adjustable soft start time.
The TPS54428 is available in 8-pin DDA package
and 10-pin DRC packages, and is designed to
operate over the ambient temperature range of –40°C
to 85°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54428 SO PowerPAD (8) 4.90 mm × 3.90 mm
VSON (10) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic 1.05-V Load Transient Response
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
7 Detailed Description.............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 16
10.3 Thermal Considerations........................................ 17
11 Device and Documentation Support ................. 18
11.1 Documentation Support ........................................ 18
11.2 Community Resources.......................................... 18
11.3 Trademarks........................................................... 18
11.4 Electrostatic Discharge Caution............................ 18
11.5 Glossary................................................................ 18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2015) to Revision D Page
• Updated Figure 20................................................................................................................................................................ 16
Changes from Revision B (March 2013) to Revision C Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (January 2012) to Revision B Page
• Changed the Description text to include the DRC package................................................................................................... 1
• Added Figure 21................................................................................................................................................................... 16
Changes from Original (November 2011) to Revision A Page
• Deleted TA= –20ºC to 85ºC from ELEC CHARA table, CURRENT LIMIT section, Test Conditions statement.................... 5
‘5‘ TEXAS INSTRUMENTS
PowerPAD
TPS54428
SW
VBST
SS
VFB
GND
8
2
3
4
1EN
VREG5
7
6
5
VIN
EN
VFB
VREG5
SS
GND
VIN
VIN
VBST
SW
SW
Exposed
Thermal
Die PAD
on
Underside
PGND
1
2
3
4
5
10
9
8
7
6
3
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5 Pin Configuration and Functions
DDA Package with Thermal Pad
8-Pin SO PowerPAD
Top View
DRC Package with Thermal Pad
10-Pin VSON
Top View
Pin Functions
PIN DESCRIPTION
NAME DDA DRC
EN 1 1 Enable input control. Active high.
VFB 2 2 Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5 3 3 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND.
VREG5 is not active when EN is low.
SS 4 4 Soft-start control. An external capacitor should be connected to GND.
GND 5 Ground pin. Power ground return for switching circuit. Connect sensitive SS and
VFB returns to GND at a single point.
GND 5 Ground pin. Connect sensitive SS and VFB returns to GND at a single point.
SW 6 6, 7 Switch node connection between high-side NFET and low-side NFET.
VBST 7 8 Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor
between VBST and SW pins. An internal diode is connected between VREG5 and
VBST.
VIN 8 9, 10 Input voltage supply pin.
Exposed Thermal
Pad Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation.
Must be connected to GND.
Exposed Thermal
Pad Back side Thermal pad of the package. PGND power ground return of internal low-side FET.
Must be soldered to achieve appropriate dissiapation.
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage
VIN, EN –0.3 20 V
VBST –0.3 26 V
VBST (10 ns transient) –0.3 28 V
VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5 V
SW –2 20 V
SW (10 ns transient) –3 22 V
Output voltage VREG5 –0.3 6.5 V
GND –0.3 0.3 V
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500 V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 4.5 18 V
VIInput voltage range
VBST –0.1 24 V
VBST (10 ns transient) -0.1 27 V
VBST(vs SW) –0.1 5.7 V
SS –0.1 5.7 V
EN –0.1 18 V
VFB –0.1 5.5 V
SW –1.8 18 V
SW (10 ns transient) –3 21 V
GND –0.1 0.1 V
VOOutput voltage range VREG5 –0.1 5.7 V
IOOutput Current range IVREG5 0 10 mA
TAOperating free-air temperature –40 85 °C
TJOperating junction temperature –40 150 °C
l TEXAS INSTRUMENTS
5
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1)
TPS54428
UNIT
DDA (SO
POWERPAD) DRC (VSON)
8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 42.1 43.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 50.9 53.8 °C/W
RθJB Junction-to-board thermal resistance 31.8 18.2 °C/W
ψJT Junction-to-top characterization parameter 5 0.6 °C/W
ψJB Junction-to-board characterization parameter 13.5 18.3 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 7.1 4.7 °C/W
(1) Not production tested.
6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN Operating - non-switching supply current VIN current, TA= 25°C, EN = 5 V,
VFB = 0.8 V 950 1400 μA
IVINSDN Shutdown supply current VIN current, TA= 25°C, EN = 0 V 3.0 10 μA
LOGIC THRESHOLD
VENH EN high-level input voltage EN 1.6 V
VENL EN low-level input voltage EN 0.6 V
REN EN pin resistance to GND VEN = 12 V 225 450 900 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH VFB threshold voltage
TA= 25°C, VO= 1.05 V, IO= 10 mA,
Eco-mode™ operation 771
mV
TA= 25°C, VO= 1.05 V, continuous mode
operation 757 765 773
TA= –40°C to 85°C , VO= 1.05V, continuous
mode operation(1) 751 765 779
IVFB VFB input current VFB = 0.8 V, TA= 25°C 0 ±0.1 μA
VREG5 OUTPUT
VVREG5 VREG5 output voltage TA= 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA 5.2 5.5 5.7 V
VLN5 Line regulation 6 V < VIN < 18 V, IVREG5 = 5 mA 25 mV
VLD5 Load regulation 0 mA < IVREG5 < 5 mA 100 mV
IVREG5 Output current VIN = 6 V, VREG5 = 4.0 V, TA= 25°C 60 mA
MOSFET
RDS(on)h High side switch resistance, DDA 25°C, VBST - SW = 5.5 V 70 mΩ
RDS(on)h High side switch resistance, DRC 25°C, VBST - SW = 5.5 V 74 mΩ
RDS(on)l Low side switch resistance 25°C 53 mΩ
CURRENT LIMIT
Iocl Current limit L out = 1.5 µH (1) 4.6 5.3 6.8 A
l TEXAS INSTRUMENTS H EM Innm wag: .v
0510 15 20
EN Input Voltage - V
V = 18 V
I
0
5
10
15
20
25
30
35
40
45
50
EN Input Current - Am
0
5
10
15
20
-50 0 50 100 150
T Junction Temperature - °C
J
Ivccsdn - Shutdown Current - Am
0
200
400
600
800
1000
1200
-50 0 50 100 150
T - Junction Temperature - °C
J
I - Supply Current - A
CC m
6
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature(1) 170 °C
Hysteresis(1) 35
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO= 1.05 V 150 ns
tOFF(MIN) Minimum off time TA= 25°C, VFB = 0.7 V 260 310 ns
SOFT START
ISSC SS charge current VSS = 0 V 4.2 6.0 7.8 μA
ISSD SS discharge current VSS = 1 V 0.1 0.2 mA
UVLO
UVLO UVLO threshold Wake up VREG5 voltage 3.45 3.75 4.05 V
Hysteresis VREG5 voltage 0.19 0.32 0.45
6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted)
Figure 1. VIN Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
Figure 3. EN Current vs EN Voltage Figure 4. 1.05-V Output Voltage vs Output Current
l TEXAS INSTRUMENTS ‘ ua mu / -l / —/ mo sun Hon um
0.75
0.755
0.76
0.765
0.77
0.775
0.78
-50 0 50 100 150
T - Junction Temperature - °C
J
Vfb - Voltage - V
0
100
200
300
400
500
600
700
800
0 1 2 3 4
I - Output Current - A
O
V = 1.8 V
O
V = 1.05 V
O
f - Switching Frequency - kHz
sw
V = 3.3 V
O
400
450
500
550
600
650
700
750
800
850
900
0510 15 20
V - Input Voltage - V
I
fsw - Switching Frequency - kHz
V = 5 V
OV = 2.5 V
OV = 1.8 V
O
V = 1.5 V
OV = 1.2 V
O
V = 1.05 V
O
V = 3.3 V
O
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1
Efficiency - %
I - Output Current - A
O
V = 3.3 V
O
V = 2.5 V
O
V = 1.8 V
O
40
50
60
70
80
90
100
Efficiency - %
V = 1.8 V
OV = 2.5 V
OV = 3.3 V
O
1 2 3 45
I - Output Current - A
O
0
1.04
1.05
1.06
1.07
1.08
0510 15 20
V - Input Voltage - V
I
V - Output Voltage - V
O
I = 10 mA
O
I = 1 A
O
7
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
Figure 5. 1.05-V Output Voltage vs VIN Voltage Figure 6. Efficiency vs Output Current
Figure 7. Light Load Efficiency vs Output Current Figure 8. Switching Frequency vs Input Voltage
Figure 9. Switching Frequency vs Output Current Figure 10. VFB Voltage vs Junction Temperature
SW
VBST
EN
VFB
GND
VO
4
5
6
2
1
7
VIN
SS
VIN
5VREG
EN
Logic
SW
PGND
Protection
Logic
Ref
SS
UVLO
UVLO
Softstart
SS
REF
TSD
Ref
VREG5
8
VIN
Ceramic
Capacitor
3
SGND
SGND
PGND
SW
PGND
ZC
VREG5
VREG5
Control Logic
1 shot
XCON
8
TPS54428
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
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7 Detailed Description
7.1 Overview
The TPS54428 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54428 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
l TEXAS INSTRUMENTS SW
6
C6(nF) Vref 1.1 C6(nF) 0.765 1.1
Tss(ms) = =
Iss( A)
´ ´ ´ ´
m
( )
IN OUT OUT
OUT(LL)
SW IN
V V V
1
I = 2 L V
- ´
´
´ ´ f
9
TPS54428
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Feature Description (continued)
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54428 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54428 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Auto-Skip Eco-Mode™ Control
The TPS54428 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
(1)
7.4 Device Functional Modes
7.4.1 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6-uA.
(2)
The TPS54428 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
7.4.2 Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54428 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
l TEXAS INSTRUMENTS
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Device Functional Modes (continued)
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
7.4.3 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54428 is shut off. This protection is non-latching.
7.4.4 Thermal Shutdown
TPS54428 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),
the device is shut off. This is non-latch protection.
TEXAS INSTRUMENTS vom E) VW VIA R5 VFS VBST ”—1; R2 icslce 22 kImFl VRECS SW (nmxm No‘ lnsto‘led
4.5 to 18 V
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Δ
1
11
TPS54428
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54428 is designed to provide up to 4-A output current from an input voltage source of 4.5 V to 17 V. The
output voltage range is from 0.76 V to 6 V.
8.2 Typical Application
Figure 11. Schematic Diagram for This Design Example
8.2.1 Design Requirements
To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple
Table 1. Performance Specifications Summary
SPECIFICATIONS TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range (VIN) 4.5 12 18 V
Output voltage (VOUT) 1.05 V
Operating frequency VIN = 12 V, IOUT = 2 A 650 kHz
Output current range 0 4 A
Line regulation IO= 2.5 A ± 0.33%
l TEXAS INSTRUMENTS
P
OUT OUT
1
F =
2 L C´p
OUT
R1
V = 0.765 1+
R2
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12
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Typical Application (continued)
Table 1. Performance Specifications Summary (continued)
SPECIFICATIONS TEST CONDITIONS MIN TYP MAX UNIT
Load regulation VIN = 12 V +0.9/–
0.1%
Overcurrent limit VIN = 12 V, L = 1.5 µH 4.6 5.3 6.8 A
Output ripple voltage VIN = 12 V, IOUT = 4A 15 mVPP
Maximum efficiency VIN = 5 V, IOUT= 0.7 A 88%
(1) Optional
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
(3)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54428 is an LC circuit. This LC filter has double pole at:
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54428. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 2.
Table 2. Recommended Component Values
Output Voltage (V) R1 (kΩ) R2 (kΩ) C4 (pF)(1) L1 (µH) C8 + C9 (µF)
1 6.81 22.1 1.5 22 - 68
1.05 8.25 22.1 1.5 22 - 68
1.2 12.7 22.1 1.5 22 - 68
1.5 21.5 22.1 1.5 22 - 68
1.8 30.1 22.1 5 - 22 2.2 22 - 68
2.5 49.9 22.1 5 - 22 2.2 22 - 68
3.3 73.2 22.1 5 - 22 2.2 22 - 68
5 124 22.1 5 - 22 3.3 22 - 68
6.5 165 22.1 5 - 22 3.3 22 - 68
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
l TEXAS INSTRUMENTS SW
( )
Ox IN O UT
CO(RMS)
IN O SW
V V V
I = 12 V L
´ -
´ ´ ´ f
2 2
LO(RMS) O
1
I = I + 12 -P P
Il
P-P
PEA K O
Il
Il = I +
2
IN(MAX) O UT
OUT
P-P
IN(MA X) O SW
V V
V
l = V L
-
´
´
If
13
TPS54428
www.ti.com
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
Product Folder Links: TPS54428
Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
(5)
(6)
(7)
For this design example, the calculated peak current is 4.51 A and the calculated RMS current is 4.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54428 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩeach.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
8.2.2.3 Input Capacitor Selection
The TPS54428 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 8 to ground is optional to provide additional frequency filtering. The capacitor voltage rating
needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor
0
10
20
30
40
50
60
70
80
90
100
0 500 1000 1500 2000 2500 3000 3500 4000
Output Current (mA)
Efficiency (%)
VIN = 12 V
VIN = 5.0 V
G000
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
Output Current (mA)
Efficiency (%)
VIN = 12 V
VIN = 5.0 V
G000
Vo = 1.5 V VIN (50 mV/div)
SW (5 V/div)
500 ns/div
Vo (10 mV/div)
V = 1.05 V
O
SW (5 V/div)
1 ms/div
EN (10 V/div)
VREG5 (5 V/div)
Vout (0.5 V/div)
100 s/divm
Vout (50 mV/div)
Iout (2 A/div)
14
TPS54428
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
www.ti.com
Product Folder Links: TPS54428
Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated
8.2.3 Application Curves
Figure 12. 1.05-V Load Transient Response Figure 13. Start Up Waveform
Figure 14. Voltage Ripple vs Ripple at Output (IO= 4 A) Figure 15. Voltage Ripple vs Ripple at Input (IO= 4 A)
Figure 16. Efficiency Figure 17. Light-Load Efficiency
l TEXAS INSTRUMENTS
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 500 1000 1500 2000 2500 3000 3500 4000
Output Current (mA)
Output Voltage, OUTP (%)
VIN = 12 V
VIN = 5.0 V
G000
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
4.5 6 7.5 9 10.5 12 13.5 15 16.5 18
Input Voltage (V)
Output Voltage, OUTP (%)
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
IOUT = 4 A
G000
15
TPS54428
www.ti.com
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
Product Folder Links: TPS54428
Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
Figure 18. Load Regulation, VIN = 5 V and VIN = 12 V Figure 19. Line Regulation
9 Power Supply Recommendations
The TPS54428 is designed to operate from input supply voltage in the range of 4.5 V to 18 V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO/ 0.65.
10 Layout
10.1 Layout Guidelines
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient vias for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
15. The TPS54428 can supply relatively large current up to 4A. So heat dissipation may be a concern. The top-
side area adjacent to the TPS54428 should be filled with ground as much as possible to dissipate heat.
16. The bottom-side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad using vias as shown. The ground area should be as large as practical. Additional internal
layers can be dedicated as ground planes and connected to vias as well.
l TEXAS INSTRUMENTS O )6 COO cm) +1JWWL C (,2 O 000 00 00 AH _N; U {v *5 000 :7 B REOOOw4W - $1 15—; m - LET 080 :: \ 000 0 000 O VIA to Ground Plane
VFB
VREG5
SS
GND
EN VIN
VBST
SW
EXPOSED
THERMAL PAD
AREA
BOOST
CAPACITOR VOUT
VIA to Ground Plane
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS TO ENABLE
CONTROL
POWER GROUND
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
VIN
HIGH FREQUENCY
BYPASS
CAPACITOR
VIN
SW
EN
VFB
VREG5
SS
VIN
VBST
SW
PGND
ANALOG
GROUND
TRACE
SOFT
START
CAP
BIAS
CAP
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITOR
VIN
POWER GROUND
Additional
Thermal
Vias
Additional
Thermal
Vias
BOOST
CAPACITOR
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
VOUT
Connection to
POWER GROUND
on internal or
bottom layer
EXPOSED
POWERPAD
AREA
VIN INPUT
BYPASS
CAPACITOR
16
TPS54428
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
www.ti.com
Product Folder Links: TPS54428
Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated
10.2 Layout Examples
Figure 20. TPS54428 Layout for the DDA Package
Figure 21. PCB Layout for the DRC Package
l TEXAS INSTRUMENTS
8 5
1 4
Exposed Thermal Pad
2,40
1,65
3,10
2,65
17
TPS54428
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SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
Product Folder Links: TPS54428
Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
10.3 Thermal Considerations
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package,SLMA002 and Application Brief,
PowerPAD™ Made Easy,SLMA004.
The exposed thermal pad dimensions for the DDA package are shown in Figure 22.
Figure 22. Thermal Pad Dimensions
l TEXAS INSTRUMENTS
18
TPS54428
SLVSB42D –NOVEMBER 2011–REVISED JANUARY 2016
www.ti.com
Product Folder Links: TPS54428
Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Documentation Support
Technical Brief, PowerPAD™ Thermally Enhanced Package,SLMA002
Application Brief, PowerPAD™ Made Easy,SLMA004.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS54428DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54428
TPS54428DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54428
TPS54428DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54428
TPS54428DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54428
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.' l i 7E OODOOOOO
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54428DDAR SO
PowerPAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TPS54428DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS54428DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54428DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0
TPS54428DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS54428DRCT VSON DRC 10 250 210.0 185.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54428DDA DDA HSOIC 8 75 508 7.77 2540 NA
TPS54428DDA DDA HSOIC 8 75 517 7.87 635 4.25
Pack Materials-Page 3
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
4202561/G
MECHANICAL DATA DC’ Powe’DAD W 3‘ AST‘C SMA‘ \ iOUi N7 {ifinm PAT: 7‘: m w sum mm m 5mm s-«EV VOTES' A AH \meur dime'ysors are n mflhmeiers Dvrensm'vng ard memncmg per ASME “4571994. 5. 'ms drawing is suaject :o mange w‘wom whee. C Body m'r‘ensm'vs co m mcmce mo‘d Hush m provusm'v no‘ to excess 0,15 D ’h‘s package 15 dcsw'gnud {a be smccrcd (a u thavma‘ pad or We bnurd Rafe! to Tuchw'wuu Er'uf‘ PowurFod 'rermauy Enhance: Pucmge, 'exas nsimments {mm M. swwoz m 'nformufmn regurqu reccmmended mm cywk This documeM is cvm‘uh‘e :1 www um See the addwtmnu‘ figue m [we Pronuct Dal: sree: {m detufls 'egc'cmq (he exposen thermo‘ pud {eciures c'vd d'mensmns TM: package comp‘es m JEDEC M57012 va'mfinn EA PowerPAD is a trademavk MTexas \nsuuments. J5 TEXAS INSTRUMENTS wwwxi .com
THERMAL PAD MECHANICAL DATA DDA (R—PDSO—GB) PowerPADm PLASTiC SMALL OUTLiNE THERMAL iNFORMATION This PowerPADl'package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board (PCB). The thermal pad must be soldered directly to the PCB. Alter soldering. the PCB can he used as a heatsink. In addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively. can be attached to a special heatsink structure designed into the PCB, This design optimizes the heat transter trom the integrated circuit (iC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas instruments Literature No. SLMAOOZ and Application Brief, PowerPAD Made Easy, Texas instruments Literature No. SLMAOO4. Both documents are available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration. 8 5 H H H H T '— — —- — 1 Exposed Thermal Pad 2.40 |_ ‘ J 1.65 | ‘ i l L7 ~74 H H H H 1 fl 4 2,55 Top new Exposed Thermal Pad Dimensions 420632276/L 05/12 NOTE: A, All linear dimensions are in millimeters PowerPAD is a trademark of Texas Instruments {I} TEXAS INSTRUMENTS www.ti.com
LAND PATTERN DATA DDA (R—PDSO—GS) PowerPADTM PLASTIC SMALL OUTLINE Example Board Layout o.i27mm Thicx stencil Design Example \fia panern and mm, M 5iZe Reierence table below lor other may vary depending on layout constraints solder slencll thicknesses (Nate E) “LEO NOTES: F, Fame») is a tract solder mask over copper i.27 0,45» <_ it—i»="" l,27="" --------="" —="" 2,i5="" -—-—-—-—-—="" kilo»="" 5,="" 5="" y="" 2.40="" 5,75="" example="" solder="" mosx="" defined="" pad="" (see="" note="" c.="" d)="" mask="" defined="" pad="" xdmple="" solder="" mask="" opening="" \e="" .="" (nate="" f)="" center="" power="" pad="" solder="" stencil="" opening="" stencil="" thickness="" x="" y="" 0.1mm="" 3.3="" 2.6="" 0.l27mm="" 3.1="" 2.4="" 0.152mm="" 2.9="" 2.2="" pad="" geometry="" 0,l78mm="" 2.8="" 2.l="" (note="" c)="" all="" around="" 4208951-6/[1="" 04/12="" all="" linear="" dimensions="" are="" in="" millimeters.="" this="" drawing="" is="" subject="" to="" change="" without="" notice.="" publication="" ch77351="" is="" recommended="" tor="" alternate="" designs.="" this="" package="" is="" designed="" to="" be="" soldered="" to="" a="" thermal="" pad="" on="" the="" board="" reier="" to="" rechnical="" brier.="" pdwerpdd="" thermally="" enhanced="" package.="" texas="" lnstruments="" literature="" no.="" slmaooz,="" slmaoo4.="" and="" also="" the="" product="" data="" sheets="" ior="" specific="" thermal="" inlormation.="" v'la="" requirements,="" and="" recommended="" board="" layout.="" these="" documents="" are="" available="" at="" xwwticom="">. Publication che755l is recommended tar alternate designs. Laser culling apertures with trapezoidal walls and also rounding corners will otter better paste release. Customers should contact their board assembly site for stencil design recommendations. Example stencil design based on a sex volumetric metal load solder paste. Reler to ch—7525 tor other stencil recommendations. Customers should Contact Meir board lubrication sile for solder musk lolerunces between and around signal pads. amwk at Texas lnxlmmenls. {I} TEXAS INSTRUMENTS www.li.cam
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VSON - 1 mm max heightDRC 10
PLASTIC SMALL OUTLINE - NO LEAD
3 x 3, 0.5 mm pitch
4226193/A
--I vfi g C C C C C r1 C I WW‘iTiqu C A 33933
www.ti.com
PACKAGE OUTLINE
C
10X 0.30
0.18
2.4 0.1
2X
2
1.65 0.1
8X 0.5
1.0
0.8
10X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
4X (0.25)
2X (0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
10X (0.24)
(2.4)
(2.8)
8X (0.5)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
10X (0.6)
(R0.05) TYP
(3.4)
(0.25)
(0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
SYMM
1
56
10
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
11
SYMM
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
10X (0.24)
10X (0.6)
2X (1.5)
2X
(1.06)
(2.8)
(0.63)
8X (0.5)
(0.5)
4X (0.34)
4X (0.25)
(1.53)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
56
10
EXPOSED METAL
TYP
11
SYMM
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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