NTZD3152P Datasheet by onsemi

MOSFET , ’ ON Semiconductor@ www.0nsemi.com P-Channel
© Semiconductor Components Industries, LLC, 2016
June, 2019 − Rev. 6
1Publication Order Number:
NTZD3152P/D
NTZD3152P
MOSFET – Dual, P-Channel
with ESD Protection,
Small Signal, SOT-563
-20 V, -430 mA
Features
•Low RDS(on) Improving System Efficiency
•Low Threshold Voltage
•ESD Protected Gate
•Small Footprint 1.6 x 1.6 mm
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Load/Power Switches
•Power Supply Converter Circuits
•Battery Management
•Cell Phones, Digital Cameras, PDAs, Pagers, etc.
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −20 V
Gate−to−Source Voltage VGS ±6.0 V
Continuous Drain Current
(Note 1) Steady
State
TA = 25°C
ID
−430 mA
TA = 85°C−310
Power Dissipation
(Note 1)
Steady State PD250 mW
Continuous Drain Current
(Note 1) t v 5 s
TA = 25°C
ID
−455 mA
TA = 85°C−328
Power Dissipation
(Note 1)
t v 5 s PD280 mW
Pulsed Drain Current tp = 10 msIDM −750 mA
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS−350 mA
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1)
RqJA
500 °C/W
Junction−to−Ambient – t v 5 s (Note 1) 447
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface mounted on FR4 board using 1 in. sq. pad size
(Cu. area = 1.127 in. sq. [1 oz.] including traces).
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V(BR)DSS RDS(on) Typ ID Max
−20 V
0.5 W @ −4.5 V
0.6 W @ −2.5 V −430 mA
1.0 W @ −1.8 V
Device Package Shipping†
ORDERING INFORMATION
NTZD3152PT1G SOT−563
(Pb−Free) 4000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Top View
D1
G2
S2
S1
G1
6
5
4
1
2
3
D2
PINOUT: SOT−563
P−Channel
MOSFET
NTZD3152PT5H SOT−563
(Pb−Free) 8000 / Tape & Reel
D1
S1
G1
D2
S2
G2
TU = Specific Device Code
M = Date Code
G= Pb−Free Package
TU M G
G
1
MARKING DIAGRAM
1
6
SOT−563−6
CASE 463A
(Note: Microdot may be in either location)
NTZD3152PT1H
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NTZD3152P
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted.)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−20 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ18 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = −16 V
TJ = 25°C−1.0 mA
TJ = 125°C−2.0
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "4.5 V"2.0 mA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−0.45 −1.0 V
Negative Threshold
Temperature Coefficient
VGS(TH)/TJ−1.9 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = −4.5 V, ID = −430 mA 0.5 0.9 W
VGS = −2.5 V, ID = −300 mA 0.6 1.2
VGS = −1.8 V, ID = −150 mA 1.0 2.0
Forward Transconductance gFS VDS = −10 V, ID = −430 mA 1.0 S
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1.0 MHz,
VDS = −16 V
105 175 pF
Output Capacitance COSS 15 30
Reverse Transfer Capacitance CRSS 10 20
Total Gate Charge QG(TOT)
VGS = −4.5 V, VDS = −10 V,
ID = −215 mA
1.7 2.5 nC
Threshold Gate Charge QG(TH) 0.1
Gate−to−Source Charge QGS 0.3
Gate−to−Drain Charge QGD 0.4
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(on)
VGS = −4.5 V, VDD = −10 V,
ID = −215 mA, RG = 10 W
10 ns
Rise Time tr12
Turn−Off Delay Time td(off) 35
Fall Time tf19
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = −350 mA
TJ = 25°C−0.8 −1.2 V
Reverse Recovery Time tRR VGS = 0 V, dISD/dt = 100 A/ms,
IS = −350 mA
13 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
3. Switching characteristics are independent of operating junction temperatures.
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3
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−1 V
100°C
0
1
5
0.6
632
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
0.4
0.2
0
1
Figure 1. On−Region Characteristics
0.5
1
21.5 2.5
0.8
0.4
0.2
1
0
0
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.5
35
0.7
0.6
0.4
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
0.1 1.0
0.8
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1
0.8
0.6
50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
24
TJ = −55°C
ID = −0.43 A
TJ = 25°C
1.4
0.5
75 150
TJ = 25°C
ID = −0.43 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
4
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.6
VGS = −1.8 V
−1.2 V
16
−1.4 V
−1.6 V
1.3
0.6
1.1
VGS = −2.5 V
710
VDS ≥ −10 V
0.8
0.2 0.3 0.4
0.9
VGS = −1.8 V
VGS = −2 V
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
24 8
10
2016
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
−IDSS, LEAKAGE (nA)
TJ = 150°C
TJ = 100°C
100
1000
10000
610 1814
0.45
0.65
0.55
0.75
0.7
1.0
1.2
0.5 0.6 0.7 0.8 0.9
0.8
89
0.6
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NTZD3152P
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4
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
VGS = 0 V
−VGS
510
150
100
50
0
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
021
4
1
0
QG, TOTAL GATE CHARGE (nC)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
COSS
CISS
CRSS ID = −0.215 A
TJ = 25°C
250
1.81.6
2
3
−V
DS,
DRAIN−TO−SOURCE VOLTAGE
(
VOLTS
)
10
8
2
0
QGD
101
10
1
100
RG, GATE RESISTANCE (W)
t, TIME (ns)
VDD = −10 V
ID = −0.215 A
VGS = −4.5 V
100
0
200
5
4
6
td(off)
td(on)
tf
tr
−VDS
15 1.40.2 1.2
0.9
0.2
0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
−IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
0.6
0.70.50.3
0.4
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
0.4 0.6 0.8
QT
0.80.60.4
9
3
1
5
7
QGS
Figure 11. Safe Operating Area
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1001010.1
0.001
0.1
1
10
−ID, DRAIN CURRENT (A)
RDS(on) Limit
Thermal Limit
Package Limit
dc
100 ms
10 ms
VGS ≤ 6 V
Single Pulse
TC = 25°C
0.01
0N Semiwndudw" m NDTES: 1. DIMENSIDNING AND TEILERANCING PER ASME Y14.5M. 2009. 2. CDNTREILLING DIMENSIDN: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS DF EASE MATERIAL. kDAE A f—sx L PIN DNE 6 5 4 + INDICATEIR b 1 2 3 LJLJ e» EULEM b *H: TDP VIEW SIDE VIEW 1.30 6X 0.30 MILLIMETERS :[GX 045 DIM MIN. NDM. MAX. D E Di A 0.50 0.55 0.60 k1 0.17 0.22 0.27 c 0.08 0.13 0.18 1.80 D 1.50 1.60 1.70 E 1.10 1.20 1.30 D e 0.50 BSC L 0.10 0.20 0.30 0.50 PITCH H: 1.50 1.60 1.70 RECEIMMENDED MDUNTING FDDTPRINTIIE :- For mamanm lnfornnflan on our Phirrep s‘ro‘tegy and somermq demfls, please download the UN seniconuucmr Soldering and Mowmng Technlquas RBFBrsnca Mnnum, smugnkwn ON Semmunduclm and J are Mademavks a1 Semcanduclur Campunenls lnduslnes Lu: 0173 ON Semmanduclar Dr 115 aaaaaanaa 1n the unnaa Slates andJnv mhev commas ON Semmunduclar vesewes me th| In make changes wurmm mnna. nanaa In any prnduns nanan ON Semwnduc‘nv makes m7 wavvamy represenlalmn m guarantee regardmg the sumammy a1 1L; manuals 1m any pamcu‘av purpase nnv dues ON Semmnnduclm assume any Mammy ansmg 01AM me apphcahan m use a1 any pmdudnv c1rcu1| and saaanaauy mscIam‘s any and au Mammy mcmdmg w1|hw|hmma|mn spasm cansequenha‘ m madenla‘ damages ON Sermmnduclar dues nnl aanyay any hcense under 115 pa|em thls nar xna ngma av n|hers
SOT−563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
SCALE 4:1
1
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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SOT−563, 6 LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOT−563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
XX = Specific Device Code
M = Month Code
G= Pb−Free Package
XX MG
GENERIC
MARKING DIAGRAM*
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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