TPA6133A2 Datasheet by Texas Instruments

V'.‘ ‘F. B I TEXAS INSTRUMENTS 407 407 4H7 407 M9
LEFTINM
LEFTINP
RIGHTINM
RIGHTINP
CPP CPN CPVSS VDD VDD
GND
GND
HPRIGHT
HPLEFT
SD TEST1 TEST2
Audio Source
0.47uF
0.47uF
0.47uF
0.47uF
1uF 1uF
1uF 1uF
VBAT
VBATGPIO
LEFT_OUTM
LEFT_OUTP
RIGHT_OUTM
RIGHT_OUTP
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TPA6133A2
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TPA6133A2 138-mW DirectPath™ Stereo Headphone Amplifier
1 Features 3 Description
The TPA6133A2 is a stereo DirectPath™ headphone
1• DirectPath™ Ground-Referenced Outputs amplifier with GPIO control. The TPA6133A2 has
– Eliminates Output DC Blocking Capacitors minimal quiescent current consumption, with a typical
– Reduces Board Area IDD of 4.2 mA, making it optimal for portable
applications. The GPIO control allows the device to
– Reduces Component Height and Cost be put in a low power shutdown mode.
– Full Bass Response Without Attenuation The TPA6133A2 is a high fidelity amplifier with an
• Power Supply Voltage Range: 2.5 V to 5.5 V SNR of 93 dB. A PSRR greater than 100 dB enables
• High Power Supply Rejection Ratio direct-to-battery connections without compromising
(>100 dB PSRR) the listening experience. The output noise of 12
• Differential Inputs for Maximum Noise Rejection μVrms (typical A-weighted) provides a minimal noise
background during periods of silence. Configurable
(69 dB CMRR) differential inputs and high CMRR allow for maximum
• High-Impedance Outputs When Disabled noise rejection in the noisy environment of a mobile
• Advanced Pop and Click Suppression Circuitry device.
• GPIO Control for Shutdown Device Information(1)
• 20 Pin, 4 mm x 4 mm WQFN Package PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications TPA6133A2 WQFN (20) 4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
• Mobile Phones the end of the datasheet.
• Audio Headsets
• Notebook Computers
• High Fidelity Applications
4 Simplified Application Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.2 Functional Block Diagram....................................... 10
1 Features.................................................................. 18.3 Feature Description................................................. 11
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 12
3 Description ............................................................. 19 Application and Implementation ........................ 13
4 Simplified Application Diagram............................ 19.1 Application Information............................................ 13
5 Revision History..................................................... 29.2 Typical Application ................................................. 13
6 Pin Configuration and Functions......................... 310 Power Supply Recommendations ..................... 16
7 Specification........................................................... 411 Layout................................................................... 17
7.1 Absolute Maximum Ratings ..................................... 411.1 Layout Guidelimes ................................................ 17
7.2 Handling Ratings....................................................... 411.2 Layout Example .................................................... 17
7.3 Recommended Operating Conditions....................... 412 Device and Documentation Support ................. 18
7.4 Thermal Information.................................................. 412.1 Trademarks........................................................... 18
7.5 Electrical Characteristics........................................... 512.2 Electrostatic Discharge Caution............................ 18
7.6 Operating Characteristics.......................................... 512.3 Glossary................................................................ 18
7.7 Typical Characteristics.............................................. 613 Mechanical, Packaging, and Orderable
8 Detailed Description............................................ 10 Information ........................................................... 18
8.1 Overview ................................................................. 10
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2014) to Revision B Page
• Changed "PIN QFN" To: "NUMBER" in the Pin Functions table............................................................................................ 3
• Added a NOTE to the Applications and Implementation section ........................................................................................ 13
• Added new paragraph to the Application Information section.............................................................................................. 13
Changes from Original (June 2013) to Revision A Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Added the Device Information Table ..................................................................................................................................... 1
• Moved "Minimum Load Impedance" From the Absolute Maximum Ratings table To the Recommended Operating
Conditions table...................................................................................................................................................................... 4
• Added the Thermal Information Table ................................................................................................................................... 4
• Changed text in the Overview section From: "toggling the SD pin to logic 1." To: "asserting the SD pin to logic 1." ......... 10
• Changed text in the Headphone Amplifier section From: "the output signal is severely clipped" To: "power
consumption will be higher".................................................................................................................................................. 11
• Added the Optional Test Setup section................................................................................................................................ 15
• Added the Layout Example image ...................................................................................................................................... 17
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Top View
LEFTINM
LEFTINP
GND
RIGHTINP
RIGHTINM
SD
TEST2
TEST1
GND
GND
HPRIGHT
VDD
GND
HPLEFT
CPVSS
CPVSS
CPN
CPP
GND
VDD
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6 Pin Configuration and Functions
RTJ Package
(Top VIEW)
Pin Functions
PIN INPUT,
OUTPUT, DESCRIPTION
NAME NUMBER POWER
Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left
LEFTINM 1 I input to LEFTINM when using single-ended inputs.
Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground
LEFTINP 2 I LEFTINP near signal source while maintaining matched impedance to LEFTINM when using single-
ended inputs.
Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground
RIGHTINP 4 I RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using
single-ended inputs.
Analog ground. Must be connected to common supply GND. It is recommended that this pin be
GND 3, 9, 10, 13 P used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package.
Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the
RIGHTINM 5 I right input to RIGHTINM when using single-ended inputs.
SD 6 I Shutdown. Active low logic. 5V tolerant input.
TEST2 7 I Factory test pins. Pull up to VDD supply. See Applications Diagram.
TEST1 8 I Factory test pins. Pull up to VDD supply. See Applications Diagram.
HPRIGHT 11 O Headphone light channel output. Connect to the right terminal of the headphone jack.
Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-μF capacitor
VDD 12 P to analog ground (pin 13).
HPLEFT 14 O Headphone left channel output. Connect to left terminal of headphone jack.
Negative supply generated by the charge pump. Decouple to pin 19 or a GND plane. Use a 1 μF
CPVSS 15, 16 P capacitor.
CPN 17 P Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN.
CPP 18 P Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP.
Charge pump ground. GND must be connected to common supply GND. It is recommended that
GND 19 P this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN).
Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple
VDD 20 P to GND (pin 19 ) with its own 1 μF capacitor.
Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is
Thermal pad Die Pad P required for mechanical stability and will enhance thermal performance.
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7 Specification
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range, TA= 25°C (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VDD –0.3 6 V
CPVSS-0.2 V to minimum of
RIGHTINx, LEFTINx (3.6 V, VDD+0.2 V)
Input voltage
SD, TEST1, TEST2 –0.3 7 V
Output continuous total power dissipation See the Thermal Information Table
Operating free-air temperature range, TA–40 85 °C
Operating junction temperature range, TJ–40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –3 3 kV
pins(1)
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification –750 750 V
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN MAX UNIT
Supply voltage, VDD 2.5 5.5 V
VIH High-level input voltage TEST1, TEST2, SD 1.3 V
VIL Low-level input voltage SD 0.35 V
Minimum Load Impedance 12.8 Ω
TAOperating free-air temperature –40 85 °C
7.4 Thermal Information
RTJ
THERMAL METRIC(1) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 34.8
RθJC(top) Junction-to-case (top) thermal resistance 32.5
RθJB Junction-to-board thermal resistance 11.6 °C/W
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 11.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 2.5 V to 5.5 V, inputs grounded 135 400 μV
PSRR DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded –101 -85 dB
CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V –69 dB
TEST1, TEST2 1
|IIH| High-level input current VDD = 5.5 V, VI= VDD µA
SD 10
|IIL| Low-level input current VDD = 5.5 V, VI= 0 V SD 1 µA
VDD = 2.5 V to 5.5 V, SD = VDD 4.2 6 mA
IDD Supply current Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V 0.08 1 µA
7.6 Operating Characteristics
VDD = 3.6 V , TA= 25°C, RL= 16 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 2.5V 63
Stereo, Outputs out of phase,
POOutput power VDD = 3.6V 133 mW
THD = 1%, f = 1 kHz, Gain = +4 dB VDD = 5V 142
f = 100 Hz 0.0096%
Total harmonic distortion
THD+N PO= 35 mW f = 1 kHz 0.007%
plus noise f = 20 kHz 0.0021%
200 mVpp ripple, f = 217 Hz -94.3 -85
kSVR Supply ripple rejection ratio 200 mVpp ripple, f = 1 kHz -92 dB
200 mVpp ripple, f = 20 kHz -77.1
AvChannel DC Gain SD = VDD 1.597 V/V
ΔAvGain matching 0.1%
Slew rate 0.4 V/µs
VnNoise output voltage VDD = 3.6V, A-weighted, Gain = +4 dB 12 µVRMS
Charge pump switching
fosc 300 381 500 kHz
frequency
Start-up time from shutdown 4.8 ms
Differential input impedance 36.6 kΩ
SNR Signal-to-noise ratio Po= 35 mW 93 dB
Threshold 180 °C
Thermal shutdown Hysteresis 35 °C
HW Shutdown HP output
ZOSD = 0 V, measured output to ground. 112 Ω
impedance
COOutput capacitance 80 pF
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0.001
0.01
0.1
1
10
0.001 0.01 0.1 1
THD+N (%)
Output Power (W)
VDD = 2.5V
VDD = 3.0V
VDD = 3.6V
VDD = 5.0V
C006
VDD = 2.5V
f = 1kHz
RL = 16
Stereo
0.001
0.01
0.1
1
10
0.001 0.01 0.1 1
THD+N (%)
Output Power (W)
VDD = 2.5V
VDD = 3.0V
VDD = 3.6V
VDD = 5.0V
C006
VDD = 2.5V
f = 1kHz
RL = 32
Stereo
0.001
0.01
0.1
1
10
0.01 0.1 1
THD+N (%)
Output Power (W)
Out of Phase
In Phase
C007
VDD = 3.6V
f = 1kHz
RL = 16
Stereo
0.001
0.01
0.1
1
10
0.01 0.1 1
THD+N (%)
Output Power (W)
Out of Phase
In Phase
C007
VDD = 3.6V
f = 1kHz
RL = 32
Stereo
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7.7 Typical Characteristics
Table 1. Table of Graphs
Figure
Total harmonic distortion + noise versus Output power Figure 1–Figure 4
Total harmonic distortion + noise versus Frequency Figure 5–Figure 12
Supply voltage rejection ratio versus Frequency Figure 13-Figure 14
Common mode rejection ratio versus Frequency Figure 15-Figure 16
Crosstalk versus Frequency Figure 17-Figure 18
C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 μF, CI= 2.2 µF.
All THD + N graphs taken with outputs out of phase (unless otherwise noted).
Figure 1. Total Harmonic Distortion + Noise vs Output Figure 2. Total Harmonic Distortion + Noise vs Output
Power Power
Figure 3. Total Harmonic Distortion + Noise vs Output Figure 4. Total Harmonic Distortion + Noise vs Output
Power Power
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0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 1mW
Po = 4mW
Po = 20mW
C004
VDD = 2.5V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 20mW
Po = 40mW
C004
VDD = 3.0V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 35mW
Po = 70mW
C004
VDD = 3.6V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 50mW
Po = 80mW
C004
VDD = 5.0V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 1mW
Po = 4mW
Po = 20mW
C004
VDD = 2.5V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 20mW
Po = 40mW
C004
VDD = 3.0V
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
Figure 5. Total Harmonic Distortion + Noise vs Frequency Figure 6. Total Harmonic Distortion + Noise vs Frequency
Figure 7. Total Harmonic Distortion + Noise vs Frequency Figure 8. Total Harmonic Distortion + Noise vs Frequency
Figure 9. Total Harmonic Distortion + Noise vs Frequency Figure 10. Total Harmonic Distortion + Noise vs Frequency
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-80
-70
-60
-50
-40
-30
-20
-10
0
20 200 2k 20k
Common-mode Rejection Ratio (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vo = 0.1Vrms
RL = 16
Ci = 1µF
Stereo
-80
-70
-60
-50
-40
-30
-20
-10
0
20 200 2k 20k
Common-mode Rejection Ratio (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vo = 0.1Vrms
RL = 32
Ci = 1µF
Stereo
-120
-100
-80
-60
-40
-20
0
20 200 2k 20k
Supply Voltage Rejection Ratio (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vrip = 0.1VPK
RL = 16
Ci = 1µF
Stereo
-120
-100
-80
-60
-40
-20
0
20 200 2k 20k
Supply Voltage Rejection Ratio (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vrip = 0.1VPK
RL = 32
Ci = 1µF
Stereo
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 35mW
Po = 70mW
C004
VDD = 3.6V
0.001
0.01
0.1
1
20 200 2k 20k
THD+N (%)
Frequency (Hz)
Po = 5mW
Po = 50mW
Po = 80mW
C004
VDD = 5.0V
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
Figure 11. Total Harmonic Distortion + Noise vs Frequency Figure 12. Total Harmonic Distortion + Noise vs Frequency
Figure 13. Supply Voltage Rejection Ratio vs Frequency Figure 14. Supply Voltage Rejection Ratio vs Frequency
Figure 15. Common Mode Rejection Ratio vs Frequency Figure 16. Common Mode Rejection Ratio vs Frequency
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-80
-70
-60
-50
-40
-30
-20
-10
0
20 200 2k 20k
Crosstalk (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vo = 1Vrms
RL = 16
Ci = 1µF
Stereo
-80
-70
-60
-50
-40
-30
-20
-10
0
20 200 2k 20k
Crosstalk (dB)
Frequency (Hz)
VDD = 2.5V
VDD = 3.6V
VDD = 5.0V
C010
Vo = 1Vrms
RL = 32
Ci = 1µF
Stereo
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All THD + N graphs taken with outputs out of phase (unless otherwise noted).
Figure 17. Crosstalk vs Frequency Figure 18. Crosstalk vs Frequency
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*9 TEXAS INSTRUMENTS m m m .on
LEFT
RIGHT
INPUT
STAGE
DEPOP
CHARGE
PUMP
POWER
MANAGEMENT
SHUTDOWN
CONTROL
THERMAL CURRENT
LIMIT
HPLEFT
HPRIGHT
SD
VDD GNDVDD GND
CPP
CPN
CPVSS
RIGHTINP
RIGHTINM
LEFTINP
LEFTINM
TEST1 TEST2
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8 Detailed Description
8.1 Overview
Headphone channels and the charge pump are activated by asserting the SD pin to logic 1. The charge pump
generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating
the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage
occurs. The current limit block prevents the output current from getting high enough to damage the device. The
De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events.
8.2 Functional Block Diagram
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CO+1
2pRLfc
fc+1
2pRLCO
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8.3 Feature Description
8.3.1 Headphone Amplifiers
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because
most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, power consumption
will be higher, and large amounts of dc current rush through the headphones, potentially damaging them. The top
drawing in Figure 19 illustrates the conventional headphone amplifier connection to the headphone jack and
output signal.
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ωor 32
Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between
the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
(1)
COcan be determined using Equation 2, where the load impedance and the cutoff frequency are known.
(2)
If fcis low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
Two different headphone amplifier applications are available that allow for the removal of the output dc blocking
capacitors. The capless amplifier architecture is implemented in the same manner as the conventional amplifier
with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is
connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered.
This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do
not connect the shield to any GND reference or large currents will result. The scenario can happen if, for
example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the
second block diagram and waveform in Figure 19.
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CO
CO
VOUT
VOUT
GND
GND
VDD
VDD
V /2
DD
VBIAS
Conventional
Capless
GND
VDD
VSS
VBIAS
DirectPathTM
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Feature Description (continued)
Figure 19. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by
the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at
zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no
output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and
waveform of Figure 19 illustrate the ground-referenced headphone architecture. This is the architecture of the
TPA6133A2.
8.4 Device Functional Modes
8.4.1 Modes of Operation
The TPA6133A2 supports two modes of operation. When the SD pin is driven to logic 0, the device is in low
power mode where the charge pump is powered down, the headphone channel is disabled and the outputs are
pulled to ground. When the SD pin is driven to logic 1, the device enters an active mode with charge pump
powered up and headphone channel enabled with channel gain of +4dB. The transition from inactive to active
and active to inactive states is done softly to avoid audible artifacts.
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Top View
LEFTINM
LEFTINP
GND
RIGHTINP
RIGHTINM
TEST2
TEST1
GND
GND
HPRIGHT
VDD
GND
HPLEFT
CPVSS
CPVSS
CPN
CPP
GND
VDD
0.47uF
0.47uF
0.47uF
0.47uF
2.2KQ
1uF
1uF
1uF1uF
SD
SD
VDD
VDD
VDD
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPA6133A2 is a stereo DirectPath™ headphone amplifier with GPIO control. The TPA6133A2 has minimal
quiescent current consumption, with a typical IDD of 4.2 mA, making it optimal for portable applications.
9.2 Typical Application
Figure 20 shows a typical application circuit for the TPA6133A2 with a stereo headphone jack and supporting
power supply decupling capacitors.
Figure 20. Simplified Applications Circuit
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fcIN +1
2pRIN CIN CIN +1
2pfcIN RIN
or
C(DCINPUT-BLOCKING)
1
2
CIN =
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 2. Design Parameters
DESIGN PARAMTER EXAMPLE VALUE
Input voltage 2.5 V – 5.5 V
Minimum current limit 4 mA
Maximum current limit 6 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Input-Blocking Capacitors
DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias.
Maximum performance is achieved when the inputs of the TPA6133A2 are properly biased. Performance issues
such as pop are optimized with proper input capacitors.
The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the
input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is
sufficient.
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc
input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For
example, if CIN is equal to 0.22 μF, then C(DCINPUT-BLOCKING) is equal to about 0.47 μF.
(3)
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6133A2. Use
Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of
the TPA6133A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. The
frequency and/or capacitance can be determined when one of the two values are given.
(4)
If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum
impedance would be used in the above equation. The capacitor value by the above equation would be 0.215 μF.
However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.43 μF, which is
close to the standard capacitor value of 0.47 μF. Place 0.47 μF capacitors at each input terminal of the
TPA6133A2 to complete the filter.
9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.
Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.
9.2.2.3 Decoupling Capacitors
The TPA6133A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to
ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance
(ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to
the device VDD lead. Placing the decoupling capacitors close to the TPA6133A2 is important for the performance
of the amplifier. Use a 10 μF or greater capacitor near the TPA6133A2 to filter lower frequency noise signals.
The high PSRR of the TPA6133A2 will make the 10 μF capacitor unnecessary in most applications.
14 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: TPA6133A2
TEXAS INSTRUMENTS TPA6133A2 “7
Audio Precision
Measurement
Output
+
-
LEFTINM
LEFTINP
CI
CI
VDD GND
External Power
Supply
+
-
1 Pf
HPLEFT
Rseries
Load
Low Pass
Filter
Audio Precision
Measurement
Input
+
-
TPA6133A2
TPA6133A2
www.ti.com
SLOS821B –JUNE 2013–REVISED SEPTEMBER 2014
9.2.2.4 Optional Test Setup
Figure 21. Test Setup
NOTE
Separate power supply decoupling caps are used on all VDD and CPVSS Pins
The low pass filter is used to remove harmonic content above the audible range.
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPA6133A2
l TEXAS INSTRUMENTS t-Time-s t-Time-s
1
0.5
0.75
0.25
0
-0.25
-0.5
-0.75
-1
0 2m1m 3m 4m 5m 6m 8m7m 9m 10m
t - Time - s
Voltage - V
Output
SD Enable
1
0.5
0.75
0.25
0
-0.25
-0.5
-0.75
-1
0 400m200m600m800m1m 1.2m 1.6m1.4m 1.8m 2m
t - Time - s
Voltage - V
Output
SD
Disable
TPA6133A2
SLOS821B –JUNE 2013–REVISED SEPTEMBER 2014
www.ti.com
9.2.3 Application Curves
Figure 22. Shutdown Time
Figure 23. Startup Time
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 2.5 V to 5.5 V. Therefore, the output
voltage range of power supply should be within this range and well regulated. The current capability of upper
power should not exceed the max current limit of the power switch.
16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: TPA6133A2
‘5‘ TEXAS INSTRUMENTS It is recommended to place a top \ayer ground pour for %
20
1
19 18 17 16
2
3
4
5
6 7 8 9 10
11
12
13
14
15
Audio
Source
0.47uf
0.47uf
0.47uf
0.47uf
1uf
1uf
1uf
VDD
1uf
VDD
Top Layer Ground Pour and PowerPad
Top Layer Signal Traces
Via to bottom Ground Plane
It is recommended to place a top layer ground pour for
shielding around TPA6130A2 and connect to lower main PCB
ground plane by multiple vias
Pad to top layer ground pour
Place decoupling caps as close to
TPA6120A2 pins as possible
Keep vias to ground plane away from
top layer ground pads to distribute
inductances
TPA6133A2
HPLEFT
HPRIGHT
Minimize charge pump cap series resistance.
Keep close to pins with zero vias.
SD
VDD
TPA6133A2
www.ti.com
SLOS821B –JUNE 2013–REVISED SEPTEMBER 2014
11 Layout
11.1 Layout Guidelimes
11.1.1 Exposed Pad On TPA6133A2RTJ Package
• Solder the exposed metal pad on the TPA6133A2RTJ QFN package to the a pad on the PCB. The pad on
the PCB may be grounded or may be allowed to float (not be connected to ground or power).
• If the pad is grounded, it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See
the layout and mechanical drawings at the end of the datasheet for proper sizing.
• Soldering the thermal pad improves mechanical reliability, improves grounding of the device, and enhances
thermal conductivity of the package.
11.1.2 GND Connections
• The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent
to the Analog VDD pin should be separately decoupled to each other.
11.2 Layout Example
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPA6133A2
l TEXAS INSTRUMENTS
TPA6133A2
SLOS821B –JUNE 2013–REVISED SEPTEMBER 2014
www.ti.com
12 Device and Documentation Support
12.1 Trademarks
DirectPath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: TPA6133A2
I TEXAS INSTRUMENTS Sample: Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
HPA022642RTJR ACTIVE QFN RTJ 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SIZ
TPA6133A2RTJR ACTIVE QFN RTJ 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SIZ
TPA6133A2RTJT ACTIVE QFN RTJ 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SIZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA6133A2RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA6133A2RTJT QFN RTJ 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2019
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA6133A2RTJR QFN RTJ 20 3000 367.0 367.0 35.0
TPA6133A2RTJT QFN RTJ 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2019
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WQFN - 0.8 mm max heightRTJ 20
PLASTIC QUAD FLATPACK - NO LEAD
4 x 4, 0.5 mm pitch
4224842/A
D‘MENSIONS \N MILL‘METERS #TEIASINSTRUMENI‘S
PAGESIZE
SCALE
RELEASED:
APPROVED:
ENGINEER:
SEMICONDUCTOR OPERATIONS 01295
NUMBER
CODE IDENTITY
CHECKER:
DESIGNER:
DRAFTSMAN:
REV
A
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
DATA BOOK
PACKAGE OUTLINE
TEMPLATE INFO: DATE:
EDGE# 4218519 04/07/2016 OF
ePOD, RTJ0020D / WQFN,
20 PIN, 0.5 MM PITCH
4219125
15X A
H. DENG 09/12/2016
V. PAKU & T. LEQUANG 09/12/2016
H. DENG 09/12/2016
T. TANG 09/12/2016
E. REY & D. CHIN 10/06/2016
WDM 10/24/2016
LEADFRAME EXAMPLE
4222370
EA¥/
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PACKAGE OUTLINE
www.ti.com
4219125 / A 10/2016
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RTJ0020D
0.1 C A B
0.05 C
4.1
3.9
4.1
3.9
BA
PIN 1 INDEX AREA
C
0.8 MAX
0.05
0.00
SEATING PLANE
20X 0.29
0.19
20
PIN 1 ID
(OPTIONAL)
EXPOSED
THERMAL PAD
SYMM
SYMM
(A) TYP
0.08 C
16X 0.5

15
1
DIM A
OPT 1 OPT 2
(0.1) (0.2)
16
11
5
6 10
21
4X 2
20X0.5
0.3
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219125 / A 10/2016
www.ti.com
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
LAND PATTERN EXAMPLE
SCALE: 20X
20X (0.6)
(3.8)
(0.5)
TYP
SYMM
20
SYMM
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
2.7)
(R0.05)
TYP

VIA
15
(1.1)
TYP
16
11
6 10
1
5
(3.8)
21
20X (0.24)
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
EXAMPLE STENCIL DESIGN
4219125 / A 10/2016
www.ti.com
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
(0.69)
TYP
(0.69)
TYP
21
20X (0.6)
(3.8)
(0.5)
TYP
SYMM
20
SYMM
(R0.05)
TYP
15
16
11
6 10
1
5
(3.8)
20X (0.24)
4X ( 1.19)
R E V I S I O N S
REV DESCRIPTION ECR DATE ENGINEER / DRAFTSMAN
A RELEASE NEW DRAWING 2160736 10/24/2016 T. TANG / H. DENG
SIZE
SCALE REV
APAGE
OF
5 5
NTS 4219125 A
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