THS4509-Q1 Datasheet by Texas Instruments

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THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
THS4509-Q1 Wideband Low-Noise Low-Distortion Fully Differential Amplifier
1 Features 3 Description
The THS4509-Q1 is a wideband, fully differential
1• Qualified for Automotive Applications operational amplifier designed for 5-V data-
• Fully Differential Architecture acquisition systems. It has very low noise at
• Centered Input Common-Mode Range 1.9 nV/√Hz, and extremely low harmonic distortion of
–75-dBc HD2and –80-dBc HD3at 100 MHz with
• Minimum Gain of 2 V/V (6 dB) 2 Vpp, G = 10 dB, and 1-kΩload. Slew rate is very
• Bandwidth: 1900 MHz high at 6600 V/μs and with settling time of 2 ns to 1%
• Slew Rate: 6600 V/μs(2-V step), it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB but is optimized
• 1% Settling Time: 2 ns for gain of 10 dB.
• HD2: –75 dBc at 100 MHz To allow for dc coupling to analog-to-digital
• HD3: –80 dBc at 100 MHz converters (ADCs), its unique output common-mode
• OIP2: 73 dBm at 70 MHz control circuit maintains the output common-mode
• OIP3: 37 dBm at 70 MHz voltage within 3-mV offset (typical) from the set
• Input Voltage Noise: 1.9 nV/√Hz (f > 10 MHz) voltage, when set within 0.5 V of mid-supply, with
less than 4-mV differential offset voltage. The
• Noise Figure: 17.1 dB common-mode set point is set to mid-supply by
• Output Common-Mode Control internal circuitry, which may be overdriven from an
• Power Supply: external source.
– Voltage: 3 V (±1.5 V) to 5 V (±2.5 V) The input and output are optimized for best
– Current: 37.7 mA performance with their common-mode voltages set to
mid-supply. Along with high-performance at low
• Power-Down Capability: 0.65 mA power-supply voltage, this makes for extremely high-
performance single-supply 5-V data-acquisition
2 Applications systems.
• Adaptive Cruise Control The THS4509-Q1 is offered in a quad 16-pin leadless
• Blind Spot Detection QFN package (RGT) and is characterized for
• Collision Warning operation over the full automotive temperature range
from –40°C to 125°C.
• Industrial
• 5-V Data Acquisition Systems High Linearity ADC Device Information(1)
Amplifier COMMON-MODE
PART NUMBER MINIMUM GAIN
• Test and Measurement RANGE OF INPUT
THS4509-Q1 6 dB 0.75 V to 4.25 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.3 Feature Description................................................. 25
1 Features.................................................................. 17.4 Device Functional Modes........................................ 26
2 Applications ........................................................... 18 Application and Implementation ........................ 27
3 Description ............................................................. 18.1 Application Information............................................ 27
4 Revision History..................................................... 28.2 Typical Applications ................................................ 33
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 35
6 Specifications......................................................... 410 Layout................................................................... 36
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 36
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 39
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support ................. 40
6.4 Thermal Information.................................................. 411.1 Documentation Support ........................................ 40
6.5 Electrical Characteristics: VS+ – VS– = 5 V ............... 511.2 Community Resources.......................................... 40
6.6 Electrical Characteristics: VS+ – VS– = 3 V ............... 711.3 Trademarks........................................................... 40
6.7 Typical Characteristics.............................................. 911.4 Electrostatic Discharge Caution............................ 40
7 Detailed Description............................................ 25 11.5 Glossary................................................................ 40
7.1 Overview ................................................................. 25 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 25 Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2008) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
RGT Package
16-Pin QFN
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CM 4,9 I Common-mode voltage input
NC 1 — No internal connection
Power down, PD = logic low puts part into low-power mode, PD = logic high or
PD 12 I open for normal operation
VIN– 2 I Inverting amplifier input
VIN+ 11 I Noninverting amplifier input
VOUT– 10 O Inverted amplifier output
VOUT+ 3 O Noninverted amplifier output
13, 14,
VS– I Negative amplifier power supply input
15, 16
5, 6,
VS+ I Positive amplifier power-supply input
7, 8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS– to VS+ Supply voltage 6 V
VIInput voltage –VS+VS
VID Differential input voltage 4 V
IOOutput current(2) 200 mA
Continuous power dissipation See Thermal Information
TJMaximum junction temperature 150 °C
TAOperating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS4509-Q1 incorporates a (QFN) exposed thermal pad on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature, which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about
utilizing the QFN thermally enhanced package.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±1500 V
Machine Model (MM) ±100
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Total supply voltage 3 5 V
Operating temperature, TJ–40 25 125 °C
6.4 Thermal Information
THS4509-Q1
THERMAL METRIC(1) RGT (QFN) UNIT
16-PIN
RθJA Junction-to-ambient thermal resistance 50.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.7 °C/W
RθJB Junction-to-board thermal resistance 24.5 °C/W
ψJT Junction-to-top characterization parameter 2 °C/W
ψJB Junction-to-board characterization parameter 24.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: VS+ – VS– = 5 V
test conditions (unless otherwise noted): VS+ = 2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO= 2 Vpp, RF= 349 Ω, RL= 200
Ωdifferential, TA= 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(1)
AC PERFORMANCE
G = 6 dB, VO= 100 mVpp 2 GHz
G = 10 dB, VO= 100 mVpp 1.9
Small-signal bandwidth G = 14 dB, VO= 100 mVpp 600 MHz
G = 20 dB, VO= 100 mVpp 275
Gain-bandwidth product G = 20 dB 3 GHz
Bandwidth for 0.1-dB flatness G = 10 dB, VO= 2 Vpp 300 MHz
Large-signal bandwidth G = 10 dB, VO= 2 Vpp 1.5 GHz
Slew rate (differential) 2-V step 6600 V/μs
Rise time 2-V step 0.5 ns
Fall time 2-V step 0.5 ns
Settling time to 1% 2-V step 2 ns
Settling time to 0.1% 2-V step 10 ns
f = 10 MHz –104
Second-order harmonic distortion f = 50 MHz –80 dBc
f = 100 MHz –68
f = 10 MHz –108
C
Third-order harmonic distortion f = 50 MHz –92 dBc
f = 100 MHz –81
fC= 70 MHz –78
200-kHz tone spacing,
Second-order intermodulation distortion dBc
RL= 499 ΩfC= 140 MHz –64
fC= 70 MHz –95
200-kHz tone spacing,
Third-order intermodulation distortion dBc
RL= 499 ΩfC= 140 MHz –78
200-kHz tone spacing, fC= 70 MHz 78
Second-order output intercept point RL= 100 Ω, referenced dBm
fC= 140 MHz 58
to 50-Ωoutput
200-kHz tone spacing, fC= 70 MHz 43
Third-order output intercept point RL= 100 Ω, referenced dBm
fC= 140 MHz 38
to 50-Ωoutput
fC= 70 MHz 12.2
1-dB compression point dBm
fC= 140 MHz 10.8
Noise figure 50-Ωsystem, 10 MHz 17.1 dB
Input voltage noise f > 10 MHz 1.9 nV/√Hz
Input current noise f > 10 MHz 2.2 pA/√Hz
DC PERFORMANCE
Open-loop voltage gain (AOL) C 68 dB
TA= 25°C 1 4 mV
Input offset voltage A
TA= –40°C to 125°C 1 5 mV
Average input offset voltage drift TA= –40°C to 125°C B 2.6 µV/°C
TA= 25°C 8 15.5
Input bias current A µA
TA= –40°C to 125°C 8 18.5
Average input bias current drift TA= –40°C to 125°C B 20 nA/°C
TA= 25°C 1.6 3.6
Input offset current A µA
TA= –40°C to 125°C 1.6 7
Average input offset current drift TA= –40°C to 125°C B 4 nA/°C
(1) Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
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Electrical Characteristics: VS+ – VS– = 5 V (continued)
test conditions (unless otherwise noted): VS+ = 2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO= 2 Vpp, RF= 349 Ω, RL= 200
Ωdifferential, TA= 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(1)
INPUT
Common-mode input range high 1.75 V
Common-mode input range low B –1.75
Common-mode rejection ratio 90 dB
Differential input impedance C 1.35 || 1.77 MΩ|| pF
Common-mode input impedance C 1.02 || 2.26 MΩ|| pF
OUTPUT
TA= 25°C 1.2 1.4
Each output with 100 Ω
Maximum output voltage high V
to mid-supply TA= –40°C to 125°C 1.1 1.4
A
TA= 25°C –1.4 –1.2
Each output with 100 Ω
Minimum output voltage low V
to mid-supply TA= –40°C to 125°C –1.4 –1.1
4.8 5.6
Differential output voltage swing V
TA= –40°C to 125°C 4.4
Differential output current drive RL= 10 ΩC 96 mA
Output balance error VO= 100 mV, f = 1 MHz –49 dB
Closed-loop output impedance f = 1 MHz 0.3 Ω
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth 700 MHz
Slew rate 110 V/μs
Gain 1 V/V
Output common-mode offset 1.25 V < CM < 3.5 V 5 mV
from CM input C
CM input bias current 1.25 V < CM < 3.5 V ±40 µA
CM input voltage range –1.5 to 1.5 V
CM input impedance 23 || 1 kΩ|| pF
CM default voltage 0 V
POWER SUPPLY
Specified operating voltage C 3 5 5.25 V
TA= 25°C 37.7 40.9
Maximum quiescent current mA
TA= –40°C to 125°C 37.7 41.9
A
TA= 25°C 34.5 37.7
Minimum quiescent current mA
TA= –40°C to 125°C 33.5 37.7
Power-supply rejection (±PSRR) C 90 dB
POWER DOWN Referenced to Vs–
Enable voltage threshold Assured on above 2.1 V + VS– >2.1 + VS– V
C
Disable voltage threshold Assured off below 0.7 V + VS– <0.7 + VS– V
TA= 25°C 0.65 0.9
Powerdown quiescent current A mA
TA= –40°C to 125°C 0.65 1
Input bias current PD = VS– 100 µA
Input impedance 50 || 2 kΩ|| pF
C
Turn-on time delay Measured to output on 55 ns
Turn-off time delay Measured to output off 10 µs
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6.6 Electrical Characteristics: VS+ – VS– = 3 V
test conditions (unless otherwise noted): VS+ = 1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO= 1 Vpp, RF= 349 Ω,
RL= 200 Ωdifferential, TA= 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(1)
AC PERFORMANCE
G = 6 dB, VO= 100 mVpp 1.9 GHz
G = 10 dB, VO= 100 mVpp 1.6
Small-signal bandwidth G = 14 dB, VO= 100 mVpp 625 MHz
G = 20 dB, VO= 100 mVpp 260
Gain-bandwidth product G = 20 dB 3 GHz
Bandwidth for 0.1-dB flatness G = 10 dB, VO= 1 Vpp 400 MHz
Large-signal bandwidth G = 10 dB, VO= 1 Vpp 1.5 GHz
Slew rate (differential) 2-V step 3500 V/μs
Rise time 2-V step 0.25 ns
Fall time 2-V step 0.25 ns
Settling time to 1% 2-V step 1 ns
Settling time to 0.1% 2-V step 10 ns
f = 10 MHz –107
Second-order harmonic distortion f = 50 MHz –83 dBc
f = 100 MHz –60
f = 10 MHz C –87
Third-order harmonic distortion f = 50 MHz –65 dBc
f = 100 MHz –54
fC= 70 MHz –77
200-kHz tone spacing,
Second-order intermodulation distortion dBc
RL= 499 ΩfC= 140 MHz –54
fC= 70 MHz –77
200-kHz tone spacing,
Third-order intermodulation distortion dBc
RL= 499 ΩfC= 140 MHz –62
fC= 70 MHz 72
200-kHz tone spacing
Second-order output intercept point dBm
RL= 100 ΩfC= 140 MHz 52
fC= 70 MHz 38.5
200-kHz tone spacing
Third-order output intercept point dBm
RL= 100 ΩfC= 140 MHz 30
fC= 70 MHz 2.2
1-dB compression point dBm
fC= 140 MHz 0.25
Noise figure 50-Ωsystem, 10 MHz 17.1 dB
Input voltage noise f > 10 MHz 1.9 nV/√Hz
Input current noise f > 10 MHz 2.2 pA/√Hz
DC PERFORMANCE
Open-loop voltage gain (AOL) 68 dB
Input offset voltage TA= 25°C 1 mV
Average input offset voltage drift TA= –40°C to 125°C 2.6 µV/°C
Input bias current TA= 25°C C 6 µA
Average input bias current drift TA= –40°C to 125°C 20 nA/°C
Input offset current TA= 25°C 1.6 µA
Average input offset current drift TA= –40°C to 125°C 4 nA/°C
(1) Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
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Electrical Characteristics: VS+ – VS– = 3 V (continued)
test conditions (unless otherwise noted): VS+ = 1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO= 1 Vpp, RF= 349 Ω,
RL= 200 Ωdifferential, TA= 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(1)
INPUT
Common-mode input range high 0.75 V
Common-mode input range low B –0.75 V
Common-mode rejection ratio 80 dB
Differential input impedance C 1.35 || 1.77 MΩ|| pF
Common-mode input impedance C 1.02 || 2.26 MΩ|| pF
OUTPUT
Each output with 100 Ωto
Maximum output voltage high TA= 25°C 0.45 V
mid-supply
Each output with 100 Ωto
Minimum output voltage low TA= 25°C –0.45 V
mid-supply
C
Differential output voltage swing 1.8 V
Differential output current drive RL= 10 Ω50 mA
Output balance error VO= 100 mV, f = 1 MHz –49 dB
Closed-loop output impedance f = 1 MHz 0.3 Ω
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth 570 MHz
Slew rate 60 V/μs
Gain 1 V/V
Output common-mode offset 1.25 V < CM < 3.5 V 4 mV
from CM input C
CM input bias current 1.25 V < CM < 3.5 V ±40 µA
CM input voltage range –1.5 to 1.5 V
CM input impedance 20 || 1 kΩ|| pF
CM default voltage 0 V
POWER SUPPLY
Specified operating voltage C 3 V
Quiescent current TA= 25°C A 34.8 mA
Power-supply rejection (±PSRR) C 70 dB
POWER DOWN Referenced to Vs–
Enable voltage threshold Assured on above 2.1 V + VS– >2.1 + VS– V
Disable voltage threshold Assured off below 0.7 V + VS– <0.7 + VS– V
Power-down quiescent current 0.46 mA
Input bias current PD = VS– C 65 µA
Input impedance 50 || 2 kΩ|| pF
Turn-on time delay Measured to output on 100 ns
Turn-off time delay Measured to output off 10 µs
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6.7 Typical Characteristics
6.7.1 Typical Characteristics: VS+ – VS– =5V
test conditions (unless otherwise noted): VS+ = 2.5 V, VS– = –2.5 V, CM = open, VO= 2 Vpp, RF= 349 Ω, RL= 200 Ω
differential, G = 10 dB, single-ended input, input and output referenced to midrail
Table 1. Table of Graphs VS+ – VS– =5V
TYPICAL CHARACTERISTIC CURVE FIGURE NO.
Small-signal frequency response Figure 1
Large-signal frequency response Figure 2
HD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 3
HD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 4
HD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 5
HD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 6
HD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 7
Harmonic distortion HD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 8
HD2, G = 10 dB vs Output voltage Figure 9
HD3, G = 10 dB vs Output voltage Figure 10
HD2, G = 10 dB vs Common-mode output voltage Figure 11
HD3, G = 10 dB vs Common-mode output voltage Figure 12
IMD2, G = 6 dB, VOD = 2 VPP vs Frequency Figure 13
IMD3, G = 6 dB, VOD = 2 VPP vs Frequency Figure 14
IMD2, G = 10 dB, VOD = 2 VPP vs Frequency Figure 15
Intermodulation distortion IMD3, G = 10 dB, VOD = 2 VPP vs Frequency Figure 16
IMD2, G = 14 dB, VOD = 2 VPP vs Frequency Figure 17
IMD3, G = 14 dB, VOD = 2 VPP vs Frequency Figure 18
OIP2vs Frequency Figure 19
Output intercept point OIP3vs Frequency Figure 20
0.1-dB flatness Figure 21
S-parameters vs Frequency Figure 22
Transition rate vs Output voltage Figure 23
Transient response Figure 24
Settling time Figure 25
Rejection ratio vs Frequency Figure 26
Output impedance vs Frequency Figure 27
Overdrive recovery Figure 28
Output voltage swing vs Load resistance Figure 29
Turn-off time Figure 30
Turn-on time Figure 31
Input offset voltage vs Input common-mode voltage Figure 32
Open-loop gain and phase vs Frequency Figure 33
Input referred noise vs Frequency Figure 34
Noise figure vs Frequency Figure 35
Quiescent current vs Supply voltage Figure 36
vs Supply voltage in power-down
Power-supply current Figure 37
mode
Output balance error vs Frequency Figure 38
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−120
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1 10 100 1000
f − Frequency − MHz
3rdOrderHarmonicDistortion − dBc
G=6dB,
V =2V
OD PP
R =100
LW
R =1k
LW
R =500
LW
R =200
LW
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110 100 1000
f − Frequency − MHz
2ndOrderHarmonicDistortion − dBc
G=6dB,
V =2V
OD PP
R =100
LW
R =500
LW
R =1k
LW
R =200
LW
0
2
4
6
8
10
12
14
16
18
20
22
0.1 110 100 1000 10000
f − Frequency − MHz
LargeSignalGain − dB
G=20dB
G=14dB
G=10dB
G=6dB
V =2V
OD PP
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Typical Characteristics: VS+ – VS– = 5 V (continued)
Table 1. Table of Graphs VS+ – VS– = 5 V (continued)
TYPICAL CHARACTERISTIC CURVE FIGURE NO.
CM input impedance vs Frequency Figure 39
CM small-signal frequency response Figure 40
CM input bias current vs CM input voltage Figure 41
Differential output offset voltage vs CM input voltage Figure 42
Output common-mode offset vs CM input voltage Figure 43
Figure 1. Small-Signal Frequency Response Figure 2. Large-Signal Frequency Response
Figure 3. HD2 vs Frequency Figure 4. HD3 vs Frequency
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f=16MHz
f=8MHz
V -V
OD PP
f=64MHz
f=32MHz
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3ndOrderHarmonicDistortion-dBc
f=64MHz
f=32MHz
f=8MHz
f=16MHz
V -V
OD PP
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2ndOrderHarmonicDistortion − dBc
G=14dB,
V =2V
OD PP
R =100
LW
R =200
LW
R =1k
LW
R =500
LW
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3rdOrderHarmonicDistortion − dBc
G=14dB,
V =2V
OD PP
R =100
LW
R =200
LW
R =500
LW
R =1k
LW
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3rdOrderHarmonicDistortion − dBc
G=10dB,
V =2V
OD PP
R =500
LW
R =1k
LW
R =100
LW
R =200
LW
−120
−110
−100
−90
−80
−70
−60
110 100 1000
f − Frequency − MHz
2ndOrderHarmonicDistortion − dBc
G=10dB,
V =2V
OD PP
R =200
LW
R =100
LW
R =1k
LW
R =500
LW
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 5. HD2 vs Frequency Figure 6. HD3 vs Frequency
Figure 7. HD2 vs Frequency Figure 8. HD3 vs Frequency
Figure 10. HD3 vs Output Voltage
Figure 9. HD2 vs Output Voltage
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l TEXAS INSTRUMENTS do M/é / ’ f /n \ ‘ / w W )’ 2, I %( //’/ ' J/l \‘7 ' \/l I
-100
-95
-90
-85
-80
-75
-70
-65
-60
0 50 100 150 200
− IntermodulationDistortion- dBc
IMD 3
F-Frequency-MHz
Gain=10dB,
V =2V Envelope
OD PP
R =200
LW
R =100
LW
R =1k
LW
R =500
LW
0 50 100 150 200
-100
-90
-80
-70
-60
-50
-40
-30
IMD2-IntermodulationDistortion-dBc
f-Frequency-Mhz
Gain=10dB,
V =2V Envelope
OD PP R =200
LW
R =100
LW
R =500
LW
R =1k
LW
−100
−95
−90
−85
−80
−75
−70
−65
−60
050 100 150 200
− IntermodulationDistortion − dBc
IMD3
f − Frequency − MHz
RL=1kΩ
RL=200 Ω
RL=500 Ω
RL=100 Ω
Gain=6dB,
V =2V Envelope
OD PP
-100
-90
-80
-70
-60
-50
-40
-30
050 100 150 200
IMD -IntermodulationDistortion-dBc
2
f-Frequency-Mhz
Gain=6dB,
V =2V Envelop
OD PP
R =200
LW
R =100
LW
R =500
LW
R =1k
LW
-110
-100
-90
-50
-40
-30
-1 -0.8 -0.6 -0.4 -0.2 0.4
3rdOrderHarmonicDistortion − dBc
V − − V
IC Common-ModeOutputVoltage
0 0.2 0.6 10.8
V =-1Vto1V
V =2V
G=10dB
R =200
CM
OD PP
LW
1MHz
-120
-80
-60
-70
-20
32MHz
64MHz
100MHz
150MHz
4MHz
16MHz
V =-1Vto1V
V =2V
G=10dB
R =200
CM
OD PP
LW
32MHz
100MHz
64MHz
16MHz 4MHz 1MHz
-1 -0.8 -0.6 -0.4 -0.2 0.4
V − − V
IC Common-ModeOutputVoltage
0 0.2 0.6 10.8
-120
-100
-80
-60
-40
-20
0
2ndOrderHarmonicDistortion − dBc
150MHz
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 11. HD2 vs Common-Mode Output Voltage Figure 12. HD3 vs Common-Mode Output Voltage
Figure 13. IMD2 vs Frequency Figure 14. IMD3 vs Frequency
Figure 15. IMD2 vs Frequency Figure 16. IMD3 vs Frequency
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9.8
9.9
10
10.1
10.2
0.1 1 10 100 1000
SignalGain − dB
f − Frequency − MHz
V =2V
OD PP
110 100
-70
-60
-50
-40
-30
-20
-10
0
S-Parameters-dB
1000
S21
S11
S22
S12
f-Frequency-MHz
40
45
50
55
60
65
70
75
80
85
90
0 50 100 150 200
Gain=10dB
− OutputInterceptPoint − dBm
OIP 2
f − Frequency − MHz
Gain=6dB
Gain=14dB
25
27
29
31
33
35
37
39
41
43
45
0 50 100 150 200 250
− OutputInterceptPoint − dBm
OIP3
f − Frequency − MHz
Gain=6dB
Gain=10dB
Gain=14dB
−100
−95
−90
−85
−80
−75
−70
−65
−60
050 100 150 200
− IntermodulationDistortion − dBc
IMD 3
f − Frequency − MHz
Gain=14dB
V =2V Envelope
OD PP
R =100 W
L
R =500 W
L
R =1kW
L
R =200 W
L
−100
−90
−80
−70
−60
−50
−40
−30
050 100 150 200
− IntermodulationDistortion − dBc
IMD2
f − Frequency − MHz
R =1k
LW
R =200
LW
Gain=14dB,
V =2V Envelope
CO PP
R =100
LW
R =500
LW
THS4509-Q1
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SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 17. IMD2 vs Frequency Figure 18. IMD3 vs Frequency
Figure 19. OIP2 vs Frequency Figure 20. OIP3 vs Frequency
Figure 22. S-Parameters vs Frequency
Figure 21. 0.1-dB Flatness
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l TEXAS INSTRUMENTS on S1EP Rejeclion Ralio ma t - Time - 200 nsldiv
−5
−4
−3
−2
−1
0
1
2
3
4
5
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Input
Output
VOD− DifferentialOutputVoltage − V
InputV oltage − V
t − Time 200ns/div−
0.1
1
10
100
0.1 110 100 1000
f − Frequency− MHz
− OutputImpedance −ZoΩ
−5
−4
−3
−2
−1
0
1
2
3
4
5
t − Time − 500ps/div
PercentofFinalValue − %
V =2V
OD step
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
f − Frequency − MHz
RejectionRatio −dB
PSRR−
PSRR+
CMRR
−1.5
−1
−0.5
0
0.5
1
1.5
t − Time − 500ps/div
VOD − DifferentialOutputVoltage − V
V =2V
OD step
Fall
TransistionRate − V/ s
m
0
1000
2000
3000
4000
5000
6000
7000
8000
0 0.5 11.5 22.5 3 3.5 4
Rise
V DifferentialOutrputVoltage-V
OD STEP
-
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 23. Transition Rate vs Output Voltage Figure 24. Transient Response
Figure 26. Rejection Ratio vs Frequency
Figure 25. Settling Time
Figure 27. Output Impedance vs Frequency Figure 28. Overdrive Recovery
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l TEXAS INSTRUMENTS x - 1mm - 5n nsldiv nvA/i
1100 10k 1M 100M 10G
OpenLoopGain − dB
OpenLoopPhase − degrees
f − Frequency − Hz
0
10
20
30
40
50
60
70
80
90
-230
-200
-170
-140
-110
-80
-50
-20
10
40
Gain
Phase
nV/ Hz
− VoltageNoise −
Vn
In− CurrentNoise −pA/ Hz
1
10
100
1000
10 100 1k 10k 100k 1M 10M
Vn
In
f − Frequency − Hz
0
0.4
0.8
1.2
1.6
2
t − Time 50ns/div−
0
1
2
3
4
5
PD
Output
− DifferentialOutputV oltage − V
VOD
PowerDownInput − V
0
1
2
3
4
5
6
7
V -DifferentialOutputVoltage-V
OD
10 100 1000
R -LoadResistance-
LW
0
0.4
0.8
1.2
1.6
2
0
1
2
3
4
5
− DifferentialOuputVoltage − V
VOD
PowerDownInput − V
t − imeT 2 s/divm−
PD
Output
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 29. Output Voltage Swing vs Load Resistance Figure 30. Turnoff Time
Figure 32. Input Offset Voltage
Figure 31. Turnon Time vs Input Common-Mode Voltage
Figure 33. Open-Loop Gain and Phase vs Frequency Figure 34. Input Referred Noise vs Frequency
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l TEXAS INSTRUMENTS , X
CMInputImpedance − k Ω
0.01
0.1
1
10
100
0.1 1 10 100 1000
f − Frequency − MHz
0.1 1 10 100 1000
CMGain − dB
f − Frequency − MHz
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100mVPP
0
100
200
300
400
500
600
700
800
0 0.5 1 1.5 2 2.5
PowerSupplyCurrent − A
µ
V
S− SupplyVoltage − V
T
A=25°
C
T
A=85°
C
T
A= −40
°C
−60
−50
−40
−30
−20
−10
0
10
0.1 110 100 1000
OutputBalanceError − dB
f − Frequency − MHz
25
30
35
40
1 1.5 2 2.5
− QuiescentCurrent − mA
IQ
±1.35V
T 25 C
A=°
T 5 C
A=8 °
T C
A=-40°
V -SupplyVoltage-V
S
10
11
12
13
14
15
16
17
18
19
20
0 50 100 150 200
f − Frequency − MHz
NF − NoiseFigure − dB
Gain=10dB
Gain=14dB
Gain=20dB
Gain=6dB 50- SystemW
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 35. Noise Figure vs Frequency Figure 36. Quiescent Current vs Supply Voltage
Figure 38. Output Balance Error vs Frequency
Figure 37. Power-Supply Current
vs Supply Voltage in Power-Down Mode
Figure 40. CM Small-Signal Frequency Response
Figure 39. CM Input Impedance vs Frequency
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l TEXAS INSTRUMENTS
−50
−40
−30
−20
−10
0
10
20
30
40
50
−2.5 −2 −1.5 −1 −0.5 00.5 11.5 22.5
OutputCommon−ModeOffset − mV
CMInputVoltage − V
−300
−200
−100
0
100
200
300
−2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5
CMInputBiasCurrent − A
µ
CMInputVoltage − V
DifferentialOutputOffsetV
oltage − mV
−1
0
1
2
3
4
5
−2.5 −2 −1.5 −1 −0.5 0 0.5 11.5 22.5
CMInputVoltage − V
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 42. Differential Output Offset Voltage
Figure 41. CM Input Bias Current vs CM Input Voltage vs CM Input Voltage
Figure 43. Output Common-Mode Offset vs CM Input Voltage
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6.7.2 Typical Characteristics: VS+ – VS– =3V
test conditions (unless otherwise noted): VS+ = 1.5 V, VS– = –1.5 V, CM = open, VOD = 1 Vpp, RF= 349 Ω,
RL= 200 Ωdifferential, G = 10 dB, single-ended input, input and output referenced to midrail
Table 2. Table of Graphs VS+ – VS– =3V
TYPICAL CHARACTERISTIC CURVE FIGURE NO.
Small-signal frequency response Figure 44
Large-signal frequency response Figure 45
HD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 46
HD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 47
HD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 48
Harmonic distortion HD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 49
HD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 50
HD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 51
IMD2, G = 6 dB, VOD = 1 VPP vs Frequency Figure 52
IMD3, G = 6 dB, VOD = 1 VPP vs Frequency Figure 53
IMD2, G = 10 dB, VOD = 1 VPP vs Frequency Figure 54
Intermodulation distortion IMD3, G = 10 dB, VOD = 1 VPP vs Frequency Figure 55
IMD2, G = 14 dB, VOD = 1 VPP vs Frequency Figure 56
IMD3, G = 14 dB, VOD = 1 VPP vs Frequency Figure 57
OIP2vs Frequency Figure 58
Output intercept point OIP3vs Frequency Figure 59
0.1-dB flatness Figure 60
S-parameters vs Frequency Figure 61
Transition rate vs Output voltage Figure 62
Transient response Figure 63
Settling time Figure 64
Output voltage swing vs Load resistance Figure 65
Rejection ratio vs Frequency Figure 66
Overdrive recovery Figure 67
Output impedance vs Frequency Figure 68
Turn-off time Figure 69
Turn-on time Figure 70
Output balance error vs Frequency Figure 71
Noise figure vs Frequency Figure 72
CM input impedance vs Frequency Figure 73
Differential output offset voltage vs CM input voltage Figure 74
Output common-mode offset vs CM input voltage Figure 75
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l TEXAS INSTRUMENTS } , \H mm /
−120
−110
−100
−90
−80
−70
−60
−50
−40
110 100 1000
f − Frequency − MHz
2ndOrderHarmonicDistortion − dBc
RL=500 Ω
RL=200Ω
RL=1kΩ
G=10dB,
V =1V
OD PP
−100
−90
−80
−70
−60
−50
−40
110 100 1000
f − Frequency − MHz
3rdOrderHarmonicDistortion − dBc
G=10dB,
C =1V
OD PP
R =1k
LW
R =200
LW
R =500
LW
f − Frequency − MHz
3rdOrderHarmonicDistortion − dBc
−100
−90
−80
−70
−60
−50
−40
110 100 1000
R =1k
LW
R =500
LW
R =200
LW
R =100
LW
G=6dB,
V =1V
OD PP
−120
−110
−100
−90
−80
−70
−60
−50
−40
1 10 100 1000
f − Frequency − MHz
2ndOrderHarmonicDistortion − dBc
RL=500 Ω
RL=1k Ω
RL=200 Ω
RL=100Ω
G=6dB,
V =1V
OD PP
SmallSignalGain − dB
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000 10000
f-Frequency-MHz
V =100mV
OD PP
G=20dB
G=14dB
G=10dB
G=6dB
0
2
4
6
8
10
12
14
16
18
20
22
0.1 110 100 1000 10000
f− Frequency − MHz
LargeSignalGain − dB
V =1V
OD PP
G=20dB
G=14dB
G=10dB
G=6dB
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 44. Small-Signal Frequency Response Figure 45. Large-Signal Frequency Response
Figure 46. HD2 vs Frequency Figure 47. HD3 vs Frequency
Figure 49. HD3 vs Frequency
Figure 48. HD2 vs Frequency
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−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
f − Frequency − MHz
− IntermodulationDistortion − dBc
IMD2
Gain=10dB,
V =1V Envelope
OD PP
R =500
LW
R =1k
LW
R =200
LW
R =100
LW
−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
− IntermodulationDistortion − dBc
IMD
3
f − Frequency − MHz
Gain=10dB,
V =1V Envolope
OD PP
R =100
LW
R =1k
LW
R =200
LW
R =500
LW
−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
− IntermodulationDistortion − dBc
IMD3
f − Frequency − MHz
Gain=6dB,
V =1V Envelope
OD PP
R =100
LW
R =1k
LW
R =500
LW
R =200
LW
− IntermodulationDistortion − dBc
IMD2
−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
f − Frequency − MHz
R =500
LW
R =200
LW
R =100
LW
R =1k
LW
Gain=6dB,
V =1V
OD PP
−120
−110
−100
−90
−80
−70
−60
−50
−40
110 100 1000
f − Frequency − MHz
2ndOrderHarmonicDistortion − dBc
RL=500 Ω
RL=200Ω
RL=100Ω
G=14dB,
V =1V
OD PP
RL=1k Ω
−100
−90
−80
−70
−60
−50
−40
110 100 1000
f − Frequency − MHz
3rdOrderHarmonicDistortion − dBc
R =500
LW
R =1k
LW
R =200
LW
R =100
LW
G=14dB,
V =1V
OD PP
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 50. HD2 vs Frequency Figure 51. HD3 vs Frequency
Figure 52. IMD2 vs Frequency Figure 53. IMD3 vs Frequency
Figure 55. IMD3 vs Frequency
Figure 54. IMD2 vs Frequency
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SignalGain − dB
f − Frequency − MHz
9.8
9.9
10
10.1
10.2
0.1 1 10 100 1000 10000
V =1V
OD PP
-70
-60
-50
-40
-30
-20
-10
0
110 100 1000
f=Frequency-MHz
S-Parameters-dB
S21
S11
S22
S12
30
35
40
45
50
55
60
65
70
75
80
050 100 150 200
− OutputInterceptPoint − dBm
OIP2
Gain=6dB
f − Frequency − MHz
Gain=10dB
Gain=14dB
15
20
25
30
35
40
45
050 100 150 200 250
− OutputInterceptPoint − dBm
OIP3
f − Frequency − MHz
Gain=10dB
Gain=14dB
Gain=6dB
−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
f − Frequency − MHz
− IntermodulationDistortion − dBc
IMD 2
Gain=14dB,
V =1V Envelope
OD PP
R =500
LW
R =200
LW
R = 1 k
LW
R =100
LW
−100
−90
−80
−70
−60
−50
−40
−30
0 50 100 150 200
− IntermodulationDistortion − dBc
IMD3
f − Frequency − MHz
Gain=14dB,
V =1V Envelope
OD PP
R =100
LW
R =500
LW
R =1k
LW
R =200
LW
THS4509-Q1
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SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 56. IMD2 vs Frequency Figure 57. IMD3 vs Frequency
Figure 58. OIP2 vs Frequency Figure 59. OIP3 vs Frequency
Figure 61. S-Parameters vs Frequency
Figure 60. 0.1-dB Flatness
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l TEXAS INSTRUMENTS svzp l- Time - 200 nsldiv
VOD − DifferentialOutputVoltage-V
InputVoltage-V
t − Time 200ns/div−
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
Input
Output
f − Frequency − MHz
RejectionRatio −dB
0
10
20
30
40
50
60
70
80
90
0.01 0.1 1 10 100 1000
CMRR
PSRR−
PSRR+
0
0.5
1
1.5
2
2.5
0100 1000
V - Differential Output Voltage - V
OD
R -LoadResistance-
LW
−5
−4
−3
−2
−1
0
1
2
3
4
5
t − Time 500ps/div−
PercentofFinalVoltage-V
V =1V
OD step
VOD− DifferentialOutputVoltage-VSTEP
SR − TransitionRate − V/ s
µ
0
500
1000
1500
2000
2500
3000
3500
4000
00.2 0.4 0.6 0.8 1 1.2 1.4
Falling
Rising
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
t − Time − 500ps/div
V
OD − DifferentialOutputVoltage-V
V =1V
OD step
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 63. Transient Response
Figure 62. Transition Rate vs Output Voltage
Figure 65. Output Voltage Swing vs Load Resistance
Figure 64. Settling Time
Figure 66. Rejection Ratio vs Frequency Figure 67. Overdrive Recovery
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l TEXAS INSTRUMENTS l- Time - 5n nsldiv
CMInputImpedance − k Ω
f − Frequency − MHz
0.01
0.1
1
10
100
0.1 1 10 100 1000
t − Time − 50ns/div
PowerDownInput − V
0
0.2
0.4
0.6
0.8
1
1.2
0
0.5
1
1.5
2
2.5
3
− DifferentialOuputVoltage-V
VOD
PD
O u t p u t
OutputBalanceError − dB
f − Frequency − MHz
−60
−50
−40
−30
−20
−10
0
10
0.1 110 100 1000
− DifferentialOuputVoltage-V
VOD
PowerDownInput − V
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
3
t – Time 2 s/divm–
PD
Output
f − Frequency− MHz
− OutputImpedance −ZoΩ
0.1
1
10
100
0.1 1 10 100 1000
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 68. Output Impedance vs Frequency Figure 69. Turn-off Time
Figure 71. Output Balance Error vs Frequency
Figure 70. Turn-on Time
Figure 72. Noise Figure vs Frequency Figure 73. CM Input Impedance vs Frequency
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l TEXAS INSTRUMENTS
DifferentialOutputOffsetV oltage − mV
CMInputVoltage − V
−1
0
1
2
3
4
5
−1.5 −1 −0.5 0 0.5 11.5
−50
−40
−30
−20
−10
0
10
20
30
40
50
−1.5 −1 −0.5 0 0.5 1 1.5
OutputCommon−ModeOffset − mV
CMInputVoltage-V
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 75. Output Common-Mode Offset
Figure 74. Differential Output Offset Voltage vs CM Input Voltage
vs CM Input Voltage
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l TEXAS INSTRUMENTS
V+
-IN
+
±
High-Aol
Differential I/O
Amplifier
+IN
50 k
2.5 k
2.5 k
+OUT
-OUT
+
±
+
±
Vcm
Error
Amplifier Vcm
V+
50 k
EN Buffer
V±
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
7 Detailed Description
7.1 Overview
The THS4509-Q1 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The THS4509-Q1, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the positive and negative signal path channels,
which function similarly to inverting mode operational amplifiers and are the primary signal paths. The third
channel is the common-mode feedback circuit. This is the circuit that sets the output common mode as well as
driving the positive and negative outputs to be equal magnitude and opposite phase, even when only one of the
two input channels is driven. The common-mode feedback circuit allows single-ended to differential operation.
7.2 Functional Block Diagram
7.3 Feature Description
THS4509-Q1 fully differential amplifier requires external resistors to set a minimum gain of 6 db and optimized
gain of 10 db for correct signal-path operation. When configured for the desired input impedance and gain setting
with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than
Vs– + 2.1 V, or turned off by asserting PD low. Disabling the amplifier shuts off the quiescent current and stops
correct amplifier operation. The signal path is still present for the source signal through the external resistors.
The CM control pin sets the output average voltage. Left open, CM voltage defaults to an internal midsupply
value. Driving the CM input with a voltage reference within its valid range sets a target for the internal common
mode error amplifier.
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7.4 Device Functional Modes
An integrated, fully-differential amplifier is very similar in architecture to a standard, voltage feedback operational
amplifier, with a few differences. Both types of amplifiers have differential inputs. Fully differential amplifiers have
differential outputs, while a standard operational amplifier’s output is single-ended. In a fully-differential amplifier,
the output is differential and the output common-mode voltage can be controlled independently of the differential
voltage. The purpose of the Vocm input in the fully-differential amplifier is to set the output common-mode
voltage. Vocm is biased to the midpoint between positive and negative supplies by an internal voltage divider In
a standard operational amplifier with single-ended output, the output common-mode voltage and the signal are
the same thing. There is typically one feedback path from the output to the negative input in a standard
operational amplifier. A fully-differential amplifier has multiple feedback paths.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following circuits show application information for the THS4509-Q1. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. See THS4509-Q1 EVM for recommendations. For more detail on
the use and operation of fully differential op amps see the application report Fully-Differential Amplifiers
(SLOA054) .
8.1.1 Test Circuits
The THS4509-Q1 is tested with the following test circuits built on the EVM. For simplicity, power-supply
decoupling is not shown – see layout in the applications section for recommendations. Depending on the test
conditions, component values are changed per the following tables, or as otherwise noted. The signal generators
used are ac coupled 50-Ωsources and a 0.22-μF capacitor and a 49.9-Ωresistor to ground are inserted across
RIT on the alternate input to balance the circuit. A split power supply is used to ease the interface to common test
equipment, but the amplifier can be operated single supply, as described in the applications section, with no
impact on performance.
Table 3. Gain Component Values
GAIN RFRGRIT
6 dB 348 Ω165 Ω61.9 Ω
10 dB 348 Ω100 Ω69.8 Ω
14 dB 348 Ω56.2 Ω88.7 Ω
20 dB 348 Ω16.5 Ω287 Ω
SPACE
NOTE
The gain setting includes 50-Ωsource impedance. Components are chosen to achieve
gain and 50-Ωinput termination.
Table 4. Load Component Values
RLROROT ATTEN
100 Ω25 Ωopen 6 dB
200 Ω86.6 Ω69.8 Ω16.8 dB
499 Ω237 Ω56.2 Ω25.5 dB
1k Ω487 Ω52.3 Ω31.8 dB
SPACE
NOTE
Note the total load includes 50-Ωtermination by the test equipment. Components are
chosen to achieve load and 50-Ωline termination through a 1:1 transformer.
Due to the voltage divider on the output formed by the load component values, the amplifier's output is
attenuated. The column ATTEN in Table 4 shows the attenuation expected from the resistor divider. When using
a transformer at the output, as shown in Figure 77, the signal sees slightly more loss, and these numbers are
approximate.
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Product Folder Links: THS4509-Q1
w W??? ifi ”E
THS 4509
CM
From
50 Ω
Source
VIN
0.22 µF
49.9 Ω
VOUT
Open
To 50 Ω
Test
Equipment
RG
RIT
RG
RIT
RF
VS+
VS−
RO
ROROT
0.22 µF
1:1
RF
Output Measured
Here With High
Impedance
Differential Probe
THS4509
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50 Ω
Source VS+
VS−
49.9 Ω
49.9 Ω100 Ω
0.22 µF
49.9 Ω0.22 µF
Open
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
8.1.1.1 Frequency Response
The circuit shown in Figure 76 is used to measure the frequency response of the circuit.
A network analyzer is used as the signal source and as the measurement device. The output impedance of the
network analyzer is 50 Ω. RIT and RGare chosen to impedance match to 50 Ω, and to maintain the proper gain.
To balance the amplifier, a 0.22-µF capacitor and 49.9-Ωresistor to ground are inserted across RIT on the
alternate input.
The output is probed using a high-impedance differential probe across the 100-Ωresistor. The gain is referred to
the amplifier output by adding back the 6-dB loss due to the voltage divider on the output.
Figure 76. Frequency Response Test Circuit
8.1.1.2 Distortion and 1-dB Compression
The circuit shown in Figure 77 is used to measure harmonic distortion, intermodulation distortion, and 1-db
compression point of the amplifier.
A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output
impedance of the signal generator is 50 Ω. RIT and RGare chosen to impedance-match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF capacitor and 49.9-Ωresistor to ground are inserted across
RIT on the alternate input.
A low-pass filter is inserted in series with the input to reduce harmonics generated at the signal source. The level
of the fundamental is measured, then a high-pass filter is inserted at the output to reduce the fundamental so that
it does not generate distortion in the input of the spectrum analyzer.
The transformer used in the output to convert the signal from differential to single ended is an ADT1-1WT. It
limits the frequency response of the circuit so that measurements cannot be made below approximately 1 MHz.
Figure 77. Distortion Test Circuit
The 1-dB compression point is measured with a spectrum analyzer with 50-Ωdouble termination or 100-Ω
termination as shown in Table 4. The input power is increased until the output is 1 dB lower than expected. The
number reported in the table data is the power delivered to the spectrum analyzer input. Add 3 dB to see the
amplifier output.
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Product Folder Links: THS4509-Q1
From
50 Ω
Source THS4509
CM
VIN
CMRR
PSRR+
PSRR−
VS+
VS−
VS+
VS−
100 Ω
100 Ω
69.8 Ω
348 Ω
348 Ω
49.9 Ω
49.9 Ω
Open
0.22 µF
100 Ω
Output
Measured
Here
With High
Impedance
Differential
Probe
VS+
CM
VIN From
source
VS–
49.9 W
0.22 Fm
RF
RF
RG
RG
RIT
RIT
VOUT+
V
OUT–
To
50-ohm
Test
Equipment
RCMT
RCM
THS4509
50-ohm
49.9 W
0.22 Fm
49.9 W
49.9 W
THS 4509
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50 Ω
Source
0.22 µF
49.9 Ω
VOUT+
Open
To 50 Ω
Test
Equipment
VS+
VS− 0.22 µF
VOUT−
49.9 Ω
49.9 Ω
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
8.1.1.3 S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive,
Output Voltage, and Turn-On and Turn-Off Time
The circuit shown in Figure 78 is used to measure s-parameters, slew rate, transient response, settling time,
output impedance, overdrive recovery, output voltage swing, and turnon and turnoff times of the amplifier. For
output impedance, the signal is injected at VOUT with VIN left open and the drop across the 49.9-Ωresistor is
used to calculate the impedance seen looking into the amplifier’s output.
Because S21 is measured single ended at the load with 50-Ωdouble termination, add 12 dB to refer to the
amplifier’s output as a differential signal.
Figure 78. S-Parameter, Sr, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and
Turnon and Turnoff Test Circuit
8.1.1.4 CM Input
The circuit shown in Figure 79 is used to measure the frequency response and input impedance of the CM input.
Frequency response is measured single ended at VOUT+ or VOUT– with the input injected at VIN, RCM = 0 Ω, and
RCMT = 49.9 Ω. The input impedance is measured with RCM = 49.9 Ωwith RCMT = open, and calculated by
measuring the voltage drop across RCM to determine the input current.
Figure 79. CM Input Test Circuit
8.1.1.5 CMRR and PSRR
The circuit shown in Figure 80 is used to measure the CMRR and PSRR of VS+ and VS–. The input is switched
appropriately to match the test being performed.
Figure 80. CMRR and PSRR Test Circuit
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VOUT–
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IN–
VS–
RF
RG
RG
VIN+
THS4509
Differential
Input
Differential
Output
+–
–+
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
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8.1.2 Differential Input to Differential Output Amplifier
The THS4509-Q1 is a fully differential op amp, and can be used to amplify differential input signals to differential
output signals. A basic block diagram of the circuit is shown in Figure 81 (CM input not shown). The gain of the
circuit is set by RFdivided by RG.
Figure 81. Differential Input to Differential Output Amplifier
Depending on the source and load, input and output termination can be accomplished by adding RIT and RO.
8.1.3 Single-Ended Input to Differential Output Amplifier
The THS4509-Q1 can be used to amplify and convert single-ended input signals to differential output signals. A
basic block diagram of the circuit is shown in Figure 82 (CM input not shown). The gain of the circuit is again set
by RFdivided by RG.
Figure 82. Single-Ended Input to Differential Output Amplifier
8.1.4 Input Common-Mode Voltage Range
The input common-model voltage of a fully differential op amp is the voltage at the + and – input pins of the op
amp.
It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is
in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one
input pin will determine the input common-mode voltage of the op amp.
Treating the negative input as a summing node, the voltage is given by Equation 1:
(1)
To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+.
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VS+
CM
VS–
50kW
tointernal
CMcircuit
IEXT
50kW
( )
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--
=-+
k50
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EXT
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input
common-mode voltage of the source.
8.1.5 Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the voltage at the CM pin(s). The internal common-mode control
circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set
within 0.5 V of mid-supply, with less than 4-mV differential offset voltage. If left unconnected, the common-mode
set point is set to mid-supply by internal circuitry, which may be overdriven from an external source. Figure 83 is
representative of the CM input. The internal CM circuit has about 700 MHz of –3-dB bandwidth, which is required
for best performance, but it is intended to be a DC bias input pin. To reduce noise at the output, TI recommends
bypass capacitors are recommended on this pin. The external current required to overdrive the internal resistor
divider is given by Equation 2:
where
• VCM is the voltage applied to the CM pin. (2)
Figure 83. CM Input Circuit
8.1.6 Single-Supply Operation (3 V to 5 V)
To facilitate testing with common lab equipment, the THS4509-Q1 EVM allows split-supply operation, and the
characterization data presented in this data sheet was taken with split-supply power inputs. The device can
easily be used with a single-supply power input without degrading the performance. Figure 84,Figure 85, and
Figure 86 show DC and AC-coupled single-supply circuits with single-ended inputs. These configurations all
allow the input and output common-mode voltage to be set to mid-supply allowing for optimum performance. The
information presented here can also be applied to differential input sources.
In Figure 84, the source is referenced to the same voltage as the CM pin (VCM). VCM is set by the internal circuit
to mid-supply. RTalong with the input impedance of the amplifier circuit provides input termination, which is also
referenced to VCM.
Note RSand RTare added to the alternate input from the signal input to balance the amplifier. Alternately, one
resistor can be used equal to the combined value RG+ RS||RTon this input. This is also true of the circuits shown
in Figure 85 and Figure 86.
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RF
RG
RG
RT
RO
ROVOUT+
VOUT-
THS4509
VBias= VCM
RS
RT
VCM
VCM
VCM
VCM
RS
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
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Figure 84. THS4509-Q1 DC-Coupled Single Supply With Input Biased to VCM
In Figure 85 the source is referenced to ground and so is the input termination resistor. RPU is added to the
circuit to avoid violating the VICR of the op amp. The proper value of resistor to add can be calculated from
Equation 3:
where
• VIC is the desire input common-mode voltage
• VCM = CM
• RIN = RG+ RS||RT(3)
To set to mid-supply, make the value of RPU = RG+ RS||RT.
Table 5 is a modification of Table 3 to add the proper values with RPU assuming a 50-Ωsource impedance and
setting the input and output common-mode voltage to mid-supply.
There are two drawbacks to this configuration. One is it requires additional current from the power supply. Using
the values shown for a gain of 10 dB requires 37 mA more current with 5-V supply, and 22 mA more current with
3-V supply.
The other drawback is this configuration also increases the noise gain of the circuit. In the 10-dB gain case,
noise gain increases by a factor of 1.5.
Table 5. RPU Values for Various Gains
GAIN RFRGRIT RPU
6 dB 348 Ω169 Ω64.9 Ω200 Ω
10 dB 348 Ω102 Ω78.7 Ω133 Ω
14 dB 348 Ω61.9 Ω115 Ω97.6 Ω
20 dB 348 Ω40.2 Ω221 Ω80.6 Ω
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2.7pF
0.1 Fm
14-bit,
125 MSPS
AIN +
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ADS5500
4 V
THS 4509
CM
348 W
348 W
100 W
100 W
69.3 W
VIN
From
50-
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100 W
100 W
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69.8 W49.9 W
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VS+=3 Vto 5V
CM
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C
RS
C
VS+
CM
VSignal
VS-
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RF
RG
RG
RT
RO
RO
VOUT+
VOUT-
THS 4509
RS
RT
RS
VS+
VS+
RPU
RPU
THS4509-Q1
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SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Figure 85. THS4509-Q1 DC-Coupled Single Supply With RPU Used to Set VIC
Figure 86 shows AC coupling to the source. Using capacitors in series with the termination resistors allows the
amplifier to self bias both input and output to mid-supply.
Figure 86. THS4509-Q1 AC-Coupled Single Supply
8.2 Typical Applications
8.2.1 THS4509-Q1 + ADS5500-EP Combined Performance
Figure 87. THS4509-Q1 + ADS5500-EP Circuit
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65
70
75
80
85
90
10 20 30 40 50 60 70 80 90 100 110
InputFrequency-MHz
SFDR(dBc)
SNR(dBFS)
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.1.1 Design Requirements
The THS4509-Q1 can be used in adjacent applications, such as industrial, in combination with HiRel devices. As
automotive standards are similar to industrial standards, automotive devices are often suitable alternative options
for the industrial customers. Applications using fully differential amplifiers have several requirements. The main
requirements are high linearity and good signal amplitude. Linearity is accomplished by using well matched
feedback and gain set resistors as well as an appropriate supply voltage. The signal amplitude can be tailored by
using an appropriate gain. In this design the gain is set for a gain of 3.48 (RF=348/ RG=100), the SFDR is 80
dBc, and the SNR is 69 dBc at a frequency of 70 Mhz. The supply voltages are set to 4 V and –1 V and the
output common mode is 1.55 V. The TSH4509 can be placed into shutdown to reduce power dissipation to less
than 5 mW.
8.2.1.2 Detailed Design Procedure
The THS4509-Q1 is designed to be a high performance drive amplifier for high performance data converters like
the ADS5500-EP 14-bit 125-MSPS ADC. Figure 87 shows a circuit combining the two devices, and Figure 88
shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level sampling at
125 MSPS. The THS4509-Q1 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5500-EP. The 100-Ωresistors and 2.7-
pF capacitor between the THS4509-Q1 outputs and ADS5500-EP inputs along with the input capacitance of the
ADS5500-EP limit the bandwidth of the signal to 115 MHz (–3 dB). For testing, a signal generator is used for the
signal source. The generator is an AC-coupled 50-Ωsource. A band-pass filter is inserted in series with the input
to reduce harmonics and noise from the signal source. Input termination is accomplished via the 69.8-Ωresistor
and 0.22-µF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ωresistor are inserted to ground across the 69.8-Ωresistor and 0.22-µF capacitor on the
alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω
feedback resistor. See Table 5 for component values to set proper 50-Ωtermination for other common gains. A
split power supply of 4 V and –1 V is used to set the input and output common-mode voltages to approximately
mid-supply while setting the input common-mode of the ADS5500-EP to the recommended 1.55 V. This
maintains maximum headroom on the internal transistors of the THS4509-Q1 to ensure optimum performance.
Figure 89 shows the two-tone FFT of the THS4509-Q1 + ADS5500-EP circuit with 65-MHz and 70-MHz input
frequencies. The SFDR is 90 dBc.
8.2.1.3 Application Curves
Figure 89. THS4509-Q1 + ADS5500-EP Two-Tone Fft With
Figure 88. THS4509-Q1 + ADS5500-EP SFDR and SNR 65-MHz and 70-MHz Input
Performance Versus Frequency
34 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4509-Q1
l TEXAS INSTRUMENTS “H w» 2%
70
75
80
85
90
95
10 20 30 40 50 60 70
InputFrequency-MHz
SFDR(dBc)
SNR(dBFS)
.2 7 pF
0.1 Fm
14-bit,
105 MSPS
AIN+
AIN– VBG
ADS 5424
5V
THS4509
CM
348 W
348 W
100 W
100
69.8 W
VIN
From
50-
source
W
225 W
225 W
69.8 W49.9 W
49.9 W
0.22 Fm0.22 Fm0.1 Fm
0.22 Fm
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Typical Applications (continued)
8.2.2 THS4509-Q1 + ADS5424-SP Combined Performance
Figure 90. THS4509-Q1 + ADS5424-SP Circuit
8.2.2.1 Detailed Design Procedure
Figure 90 shows the THS4509-Q1 driving the ADS5424-SP ADC, and Figure 91 shows their combined SNR and
SFDR performance versus frequency with –1-dBFS input signal level and sampling at 80 MSPS.
As before, the THS4509-Q1 amplifier provides 10 dB of gain, converts the single-ended input to differential, and
sets the proper input common-mode voltage to the ADS5424-SP. Input termination and circuit testing is the same
as previously described for the THS4509-Q1 + ADS5500-EP circuit.
The 225-Ωresistors and 2.7-pF capacitor between the THS4509-Q1 outputs and ADS5424-SP inputs (along with
the input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB).
Since the ADS5424-SP's recommended input common-mode voltage is 2.4 V, the THS4509-Q1 is operated from
a single power-supply input with VS+ =5VandVS– = 0 V (ground).
8.2.2.2 Application Curve
Figure 91. THS4509-Q1 + ADS5424-SP SFDR and SNR Performance vs Frequency
9 Power Supply Recommendations
The THS4509-Q1 can be used with any combination of positive and negative power supplies as long as the
combined supply voltage is between 3 V and 5 V. The THS4509-Q1 will provide best performance when the
output voltage is set at the mid supply voltage, and when the total supply voltage is between 3 V and 5 V. Power
supply bypassing as shown in Figure 93 and Figure 92 is important and power supply regulation should be within
5% or better when using a supply voltage near the edges of the operating range.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: THS4509-Q1
l TEXAS INSTRUMENTS 3;
VCM
V+
10 PF
0.1 PF
+
-
0.01 PF0.01 PF
VCM 0.1 PF
V+
V-
0.01 PF
0.01 PF
10 PF
10 PF
0.1 PF
+
-
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Figure 92. Split Supply Bypassing Capacitors
Figure 93. Single Supply Bypassing Capacitors
10 Layout
10.1 Layout Guidelines
TI recommends following the layout of the external components near the amplifier, ground plane construction,
and power routing of the EVM as closely as possible. General guidelines are:
1. Signal routing should be direct and as short as possible into and out of the op amp circuit.
2. The feedback path should be short and direct avoiding vias.
3. Ground or power planes should be removed from directly under the amplifier’s input and output pins.
4. An output resistor is recommended on each output, as near to the output pin as possible.
5. Two 10-μF and two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-
supply pins as possible.
6. Two 0.1-μF capacitors should be placed between the CM input pins and ground. This limits noise coupled
into the pins. One each should be placed to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on layer 2 (L2) and to use a solid ground on layer 3 (L3). A
single-point connection should be used between each split section on L2 and L3.
8. A single-point connection to ground on L2 is recommended for the input termination resistors R1 and R2.
This should be applied to the input gain resistors if termination is not used.
9. The THS4509-Q1 recommended PCB footprint is shown in Figure 94.
36 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4509-Q1
‘5‘ TEXAS INSTRUMENTS mTLT TLT TLT
49.9 Ω−
+
J1
R12 C15
0.22 µF
R1
69.8 Ω
R3
100 Ω
R4
100 Ω
R2
69.8 Ω
J2
TP2
C14
0.1 µFC11
0.1 µF
TP1
U1 11
2
12
4
Vocm
9
TP3
R6
348 Ω
1315
14 16
PwrPad10
VO−
VO+
3
75 86
VCC
348 Ω
VCC
R5
PD
C9
0.1 µF
C10
0.1 µF
C4
10 µF 10 µF
C6
VEE
VS−
J4 J5
GND
VEE
VS+
J6
C3
10 µF 10 µF
C5
0.1 µF 0.1 µF
C12 C13
J8
J3
T1
16
5
4
R9
open
R7
86.6 Ω
R8
86.6 Ω
R10
open
XFMR_ADT1−1WT
3
R11
69.8 Ω
J7
C8
open C7
open
C1
open
C2
open
VCC
VEE
0.144 0.0195
0.144
0.010
vias
Pin 1
Top View
0.012
0.030
0.0705
0.015
0.0095
0.049
0.032
0.0245
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
Layout Guidelines (continued)
Figure 94. QFN Etch and Via Pattern
10.1.1 THS4509-Q1 EVM
Figure 95 is the THS4509-Q1 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in Figure 96,
and Table 6 is the bill of material for the EVM as supplied from TI.
Figure 95. THS4509-Q1 EVAL1 EVM Schematic
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Links: THS4509-Q1
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THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
Layout Guidelines (continued)
Table 6. THS4509-Q1 EVAL1 EVM Bill Of Materials
SMD REFERENCE PCB MANUFACTURER'S
ITEM DESCRIPTION SIZE DESIGNATOR QTY PART NUMBER
1 CAPACITOR, 10 µF, ceramic, X5R, 6.3 V 0805 C3, C4, C5, C6 4 (AVX) 08056D106KAT2A
2 CAPACITOR, 0.1 µF, ceramic, X5R, 10 V 0402 C9, C10, C11, C12, C13, C14 6 (AVX) 0402ZD104KAT2A
3 CAPACITOR, 0.22 µF, ceramic, X5R, 6.3 V 0402 C15 1 (AVX) 04026D224KAT2A
4 OPEN 0402 C1, C2, C7, C8 4
5 OPEN 0402 R9, R10 2
6 Resistor, 49.9 Ω, 1/16 W, 1% 0402 R12 1 (KOA) RK73H1ETTP49R9F
8 Resistor, 69.8 Ω, 1/16 W, 1% 0402 R1, R2, R11 3 (KOA) RK73H1ETTP69R8F
9 Resistor, 86.6 Ω, 1/16 W, 1% 0402 R7, R8 2 (KOA) RK73H1ETTP86R6F
10 Resistor, 100 Ω, 1/16 W, 1% 0402 R3, R4 2 (KOA) RK73H1ETTP1000F
11 Resistor, 348 Ω, 1/16 W, 1% 0402 R5, R6 2 (KOA) RK73H1ETTP3480F
12 Transformer, RF T1 1 (MINI-CIRCUITS) ADT1-1WT
Jack, banana receptacle, 3
13 J4, J5, J6 (HH SMITH) 101
0.25" diameter hole
14 OPEN J1, J7, J8 3
15 Connector, edge, SMA PCB jack J2, J3 2 (JOHNSON) 142-0701-801
16 Test point, red TP1, TP2, TP3 3 (KEYSTONE) 5000
17 IC, THS4509 U1 1 (TI) THS4509RGT
18 Standoff, 4-40 HEX, 0.625" length 4 (KEYSTONE) 1808
19 Screw, phillips, 4-40, 0.250" 4 SHR-0440-016-SN
20 Printed-circuit-board 1 (TI) EDGE# 6468901
10.1.2 EVM Warnings and Restrictions
It is important to operate this EVM within the input and output voltage ranges below:
• Input Range, VI: 3 V to 6 V not to exceed VS+ or VS-
• Output range, VO: 3 V to 6 V not to exceed VS+ or VS-
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
38 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4509-Q1
l TEXAS INSTRUMENTS
THS4509-Q1
www.ti.com
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
10.2 Layout Example
Figure 96. THS4509-Q1 EVAL1 EVM Layer 1 Through 4
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Links: THS4509-Q1
l TEXAS INSTRUMENTS
THS4509-Q1
SLOS547A –NOVEMBER 2008–REVISED NOVEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the application report, Fully-Differential Amplifiers (SLOA054).
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4509-Q1
I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS4509QRGTRQ1 ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OOSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4509-Q1 :
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
•Catalog: THS4509
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4509QRGTRQ1 VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4509QRGTRQ1 VQFN RGT 16 3000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2020
Pack Materials-Page 2
GENERIC PACKAGE VIEW RGT 16 VQFN - 1 mm max heigm PLASTIC QUAD FLATPACKV N0 LEAD Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4203495” I TEXAS INSTRI IMFNTS
www.ti.com
PACKAGE OUTLINE
C
16X 0.30
0.18
1.45 0.1
16X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
12X 0.5
4X
1.5
A3.1
2.9 B
3.1
2.9
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
4
9
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
SYMM
SYMM
17
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
SCALE 3.600
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(2.8)
(2.8)
(0.475)
TYP
( 1.45)
(R0.05)
ALL PAD CORNERS (0.475) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
17
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.34)
(R0.05) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
ALL AROUND
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
4
58
9
12
13
16
17
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