TPS54540B-Q1 Datasheet by Texas Instruments

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VIN VIN

RT/CLK

COMP

GND

TPS54540B-Q1

BOOT

SW VOUT

100

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Efficiency (%)

IO - Output Current (A)

Series1

Series2

Series4

C024

VIN = 12 V

VIN = 36 V

VIN = 60 V

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

TPS54540B-Q1 4.5-V to 42-V Input, 5-A, Step-Down DC-DC Converter With Eco-mode™

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature Range

– Device HBM ESD Classification Level H1C

– Device CDM ESD Classification Level C3B

• High-Efficiency at Light Loads With Pulse-

Skipping Eco-mode™

• 92-mΩHigh-Side MOSFET

• 146-μA Operating Quiescent Current and 2-µA

Shutdown Current

• 100-kHz to 2.5-MHz Adjustable Switching

Frequency

• Synchronizes to External Clock

• Low Dropout at Light Loads With Integrated

BOOT Recharge FET

• Adjustable UVLO Voltage and Hysteresis

• 0.8-V 1% Internal Voltage Reference

• 8-Pin HSOP PowerPAD™ Package

• –40°C to 150°C TJOperating Range

• Supported by WEBENCH®Software Tool

2 Applications

• Vehicle Accessories: GPS (See SLVA412),

Entertainment, ADAS, eCall

• USB-Dedicated Charging Ports and Battery

Chargers (See SLVA464)

• Industrial Automation and Motor Control

• 12-V, 24-V, and 48-V Industrial, Automotive, and

Communications Power Systems

3 Description

The TPS54540B-Q1 device is a 42-V, 5-A, step-down

regulator with an integrated high-side MOSFET. The

device survives load-dump pulses up to 65 V per ISO

7637. Current mode control provides simple external

compensation and flexible component selection. A

low-ripple pulse-skip mode reduces the no load

supply current to 146 μA. Shutdown supply current is

reduced to 2 μA when the enable pin is pulled low.

Undervoltage lockout is internally set at 4.3 V but can

be increased using an external resistor divider at the

enable pin. The output voltage start-up ramp is

internally controlled to provide a controlled start-up

and eliminate overshoot.

A wide adjustable frequency range allows either

efficiency or external component size to be optimized.

Output current is limited cycle-by-cycle. Frequency

foldback and thermal shutdown protect internal and

external components during an overload condition.

The TPS54540B-Q1 is available in an 8-pin

thermally-enhanced HSOP PowerPAD package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS54540B-Q1 HSOP (8) 4.89 mm × 3.90 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic Efficiency vs Load Current

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 5

6.7 Switching Characteristics.......................................... 6

6.8 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 22

8 Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Applications ................................................ 23

9 Power Supply Recommendations...................... 36

10 Layout................................................................... 36

10.1 Layout Guidelines ................................................. 36

10.2 Layout Example .................................................... 36

10.3 Estimated Circuit Area .......................................... 37

11 Device and Documentation Support ................. 37

11.1 Device Support...................................................... 37

11.2 Documentation Support ........................................ 37

11.3 Community Resources.......................................... 37

11.4 Trademarks........................................................... 37

11.5 Electrostatic Discharge Caution............................ 37

11.6 Glossary................................................................ 37

12 Mechanical, Packaging, and Orderable

Information ........................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

February 2017 * Initial release.

*9 TEXAS INSTRUMENTS

GND7

COMP6

FB5

SW8

VIN

RT/CLK

BOOT

PowerPAD

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5 Pin Configuration and Functions

DDA Package

8-Pin HSOP With PowerPAD

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

BOOT 1 I A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the

minimum required to operate the high side MOSFET, the MOSFET stops switching until the capacitor is

refreshed.

COMP 6 I Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency

compensation components to this pin.

EN 3 I Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input

undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.

FB 5 I Inverting input of the transconductance (gm) error amplifier.

GND 7 — Ground

RT/CLK 4 I

Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an

external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,

a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and

the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is

reenabled and the operating mode returns to resistor frequency programming.

SW 8 O The source of the internal high-side power MOSFET and switching node of the converter.

VIN 2 I Input supply voltage is connected to this pin with a 4.5-V to 42-V operating range.

PowerPAD 9 — GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Voltage

VIN –0.3 65

EN –0.3 8.4

FB –0.3 3

COMP –0.3 3

RT/CLK –0.3 3.6

BOOT-SW –0.3 8

SW –0.6 65

SW, 10-ns Transient –2 65

Operating junction temperature –40 150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750

(1) See Equation 1 in the Feature Description section.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VIN Input supply voltage(1) VO+ Vdo 60 V

VOOutput voltage 0.8 58.8 V

IOOutput current 0 5 A

TJJunction Temperature –40 150 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1)

TPS54540B-Q1

UNITDDA (HSOP)

8 PINS

RθJA Junction-to-ambient thermal resistance 41.7 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 52.7 °C/W

RθJB Junction-to-board thermal resistance 22.6 °C/W

ψJT Junction-to-top characterization parameter 7.9 °C/W

ψJB Junction-to-board characterization parameter 22.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 °C/W

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(1) Open-loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.

6.5 Electrical Characteristics

TJ= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage 4.5 42 V

Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V

Internal undervoltage lockout threshold hysteresis 325 mV

Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤VIN ≤42 V 2.25 4.5 μA

Operating: nonswitching supply current FB = 0.9 V, TA= 25°C 146 175

ENABLE AND UVLO (EN PIN)

Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V

Input current Enable threshold 50 mV –4.6 μA

Enable threshold –50 mV –0.58 –1.2 –1.8

Hysteresis current –2.2 –3.4 –4.5 μA

INTERNAL SOFT-START TIME

Soft-start time fSW = 500 kHz, 10% to 90% 2.1 ms

Soft-start time fSW = 2.5 MHz, 10% to 90% 0.42 ms

VOLTAGE REFERENCE

Voltage reference 0.792 0.8 0.808 V

HIGH-SIDE MOSFET

On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ

ERROR AMPLIFIER

Input current 50 nA

Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μS

Error amplifier transconductance (gM) during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μS

Error amplifier DC gain VFB = 0.8 V 10000 V/V

Minimum unity gain bandwidth 2500 kHz

Error amplifier source and sink V(COMP) = 1 V, 100-mV overdrive ±30 μA

COMP to SW current transconductance 17 A/V

CURRENT LIMIT

Current limit threshold

All VIN and temperatures, Open Loop 6.3 7.9 9.5

AAll temperatures, VIN = 12 V, Open Loop 6.3 7.9 9.5

VIN = 12 V, TA= 25°C, Open Loop(1) 7.0 7.9 8.8

THERMAL SHUTDOWN

Thermal shutdown 176 °C

Thermal shutdown hysteresis 12 °C

ERROR AMPLIFIER

Enable to COMP active VIN = 12 V, TA= 25°C 346 µs

6.6 Timing Requirements

TJ= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

MIN NOM MAX UNIT

RT/CLK

Minimum CLK input pulse width 15 ns

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6.7 Switching Characteristics

TJ= –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT LIMIT

Current limit threshold delay 60 ns

RT/CLK

Switching frequency range using RT

mode 100 2500 kHz

fSW Switching frequency RT= 200 kΩ450 500 550 kHz

Switching frequency range using

CLK mode 160 2300 kHz

RT/CLK high threshold 1.55 2 V

RT/CLK low threshold 0.5 1.2 V

RT/CLK falling edge to SW rising

edge delay Measured at 500 kHz with RT

resistor in series 55 ns

PLL lock in time Measured at 500 kHz 78 μs

TEXAS INSTRUMENTS \\ \\ \ \\ 1000

450

460

470

480

490

500

510

520

530

540

550

±50 ±25 0 25 50 75 100 125 150

FS - Switching Frequency (kHz)

TJ - Junction Temperature (ƒC)

C029

100

150

200

250

300

350

400

450

500

200 300 400 500 600 700 800 900 1000

FSW - Switching Frequency (kHz)

RT/CLK - Resistance (k)

C030

Temperature Junction (Tj)

High Side Switch Current (A)

-40 -10 20 50 80 110 140 170

6.5

7.5

8.5

9.5

D001

4.5

Input Voltage (V)

High Side Switch Current (A)

0 10 20 30 40 50 60

6.5

7.5

8.5

D002

-40 qC

25 qC

150 qC

0.05

0.1

0.15

0.2

0.25

±50 ±25 0 25 50 75 100 125 150

RDSON - On-State Resistance ()

TJ - Junction Temperature (ƒC)

BOOT-SW = 3 V

BOOT-SW = 6 V

C025

0.784

0.789

0.794

0.799

0.804

0.809

0.814

±50 ±25 0 25 50 75 100 125 150

VFB - Voltage Referance ( V)

TJ - Junction Temperature (ƒC)

C026

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6.8 Typical Characteristics

Figure 1. ON-Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

Figure 3. High-side Switch Current Limit vs Junction

Temperature Figure 4. High-side Switch Current Limit vs Input Voltage

Figure 5. Switching Frequency vs Junction Temperature Figure 6. Switching Frequency vs RT/CLK Resistance Low-

Frequency Range

l TEXAS INSTRUMENTS

±5.5

±5.3

±5.1

±4.9

±4.7

±4.5

±4.3

±4.1

±3.9

±3.7

±3.5

±50 ±25 0 25 50 75 100 125 150

IEN (uA)

TJ - Junction Temperature (ƒC)

C035

±2.5

±2.3

±2.1

±1.9

±1.7

±1.5

±1.3

±1.1

±0.9

±0.7

±0.5

±50 ±25 0 25 50 75 100 125 150

IEN (µA)

TJ - Junction Temperature (ƒC)

C036

100

110

120

±50 ±25 0 25 50 75 100 125 150

gm (µA/V)

TJ - Junction Temperature (ƒC)

C033

1.15

1.16

1.17

1.18

1.19

1.2

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.3

±50 ±25 0 25 50 75 100 125 150

EN - Threshold (V)

TJ - Junction Temperature (ƒC)

C034

500

700

900

1100

1300

1500

1700

1900

2100

2300

2500

0 50 100 150 200

FSW - Switching Frequency (kHz)

RT/CLK - Resistance (k)

C031

200

250

300

350

400

450

500

±50 ±25 0 25 50 75 100 125 150

gm (µA/V)

TJ - Junction Temperature (ƒC)

C032

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Typical Characteristics (continued)

Figure 7. Switching Frequency vs RT/CLK Resistance

High-Frequency Range Figure 8. EA Transconductance vs Junction Temperature

Figure 9. EA Transconductance During Soft-Start vs

Junction Temperature Figure 10. EN Pin Voltage vs Junction Temperature

Figure 11. EN Pin Current vs Junction Temperature Figure 12. EN Pin Current vs Junction Temperature

l TEXAS INSTRUMENTS — 5mg — 5mg J smsz

110

130

150

170

190

210

±50 ±25 0 25 50 75 100 125 150

IVIN (µA)

TJ - Junction Temperature (ƒC)

C041

110

130

150

170

190

210

0 5 10 15 20 25 30 35 40 45

IVIN (µA)

VIN - Input Voltage (V)

Series2

C042

TJ = 25ƒC

0.5

1.5

2.5

±50 ±25 0 25 50 75 100 125 150

IVIN (µA)

TJ - Junction Temperature (ƒC)

C039

0.5

1.5

2.5

0 5 10 15 20 25 30 35 40 45

IVIN (µA)

VIN - Input Voltage (V)

Series2

C040

TJ = 25ƒC

±4.5

±4.3

±4.1

±3.9

±3.7

±3.5

±3.3

±3.1

±2.9

±2.7

±2.5

±50 ±25 0 25 50 75 100 125 150

IEN - Hysteresis (µA)

TJ - Junction Temperature (ƒC)

C037

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

% of Nominal Switching Frequency

VSENSE (V)

Series2

Series4

C038

VSENSE Falling

VSENSE Rising

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Typical Characteristics (continued)

Figure 13. EN Pin Current Hysteresis vs Junction

Temperature Figure 14. Switching Frequency vs VSENSE

Figure 15. Shutdown Supply Current vs Junction

Temperature Figure 16. Shutdown Supply Current vs Input Voltage (VIN)

Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage

l TEXAS INSTRUMENTS 0092

100

300

500

700

900

1100

1300

1500

1700

1900

2100

2300

2500

Soft-Start Time (ms)

Switching Frequency (kHz)

C045

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

±50 ±25 0 25 50 75 100 125 150

VIN (V)

TJ - Junction Temperature (ƒC)

UVLO Start Switching

UVLO Stop Switching

C044

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

±50 ±25 0 25 50 75 100 125 150

VI - BOOT-PH (V)

TJ - Junction Temperature (ƒC)

BOOT-PH UVLO Falling

BOOT-PH UVLO Rising

C043

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Typical Characteristics (continued)

Figure 19. BOOT-SW UVLO vs Junction Temperature Figure 20. Input Voltage UVLO vs Junction Temperature

Figure 21. Soft-Start Time vs Switching Frequency

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7 Detailed Description

7.1 Overview

The TPS54540-Q1 device is a 42-V, 5-A, step-down (buck) regulator with an integrated high-side N-channel

MOSFET. The device implements constant frequency, current mode control that reduces output capacitance and

simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows

either efficiency or size optimization when selecting the output filter components. The switching frequency is

adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop

(PLL) connected to the RT/CLK pin that will synchronize the power switch turnon to a falling edge of an external

clock signal.

The TPS54540-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to

adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup

current source enables operation when the EN pin is floating. The operating current is 146 μA under no load

condition (not switching). When the device is disabled, the supply current is 2 μA.

The integrated 92-mΩhigh-side MOSFET supports high-efficiency power supply designs capable of delivering

5 A of continuous current to a load. The gate drive bias voltage for the integrated high-side MOSFET is supplied

by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54540-Q1 device reduces the external

component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a

UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset

threshold. An automatic BOOT capacitor recharge circuit allows the TPS54540-Q1 device to operate at high duty

cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of

the application. The minimum output voltage is the internal 0.8-V feedback reference.

Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP

comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than

106% of the desired output voltage.

The TPS54540-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to

reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When

the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the

nominal regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and

overcurrent fault conditions to help maintain control of the inductor current.

l TEXAS INSTRUMENTS (_H i .C} + L _ n—W—i (3ND rowznno “ELK

Error

Amplifier

Boot

Charge

Boot

UVLO

Current

Sense

Oscillator

with PLL

Frequency

Foldback

Logic

Slope

Compensation

PWM

Comparator

Minimum

Clamp

Pulse

Skip

Maximum

Clamp

Voltage

Reference

DAC for

Soft-Start

COMP

RT/CLK

BOOT

VIN

GND

Thermal

Shutdown

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

8/8/ 2012 A 0192789

POWERPAD

Shutdown

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The TPS54540-Q1 device uses fixed frequency, peak current mode control with adjustable switching frequency.

The output voltage is compared through external resistors connected to the FB pin to an internal voltage

reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error

amplifier output at the COMP pin controls the high-side power switch current. When the high-side MOSFET

switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP

pin voltage will increase and decrease as the output current increases and decreases. The device implements

current limiting by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is

implemented with a minimum voltage clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54540-Q1 device adds a compensating ramp to the MOSFET switch current sense signal. This slope

compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the

high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.

TEXAS INSTRUMENTS

( ) ( )

OUT F dc OUT

IN DS OUT F

V V R I

V min R on I V

+ + ´

= + ´ -

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Feature Description (continued)

7.3.3 Pulse-Skip Eco-mode

The TPS54540-Q1 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by

reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at

the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The

pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of

600 mV.

When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.

Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the

falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching

resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to

the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the

device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light

load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54540-Q1 device senses and controls peak switch current, not the average

load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor

value. As the load current approaches zero, the device enters a pulse-skip mode during which it draws only

152 µA of input quiescent current. The circuit in Figure 33 enters Eco-mode at about 18-mA output current, and

with no external load has an average input current of 240 µA.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54540-Q1 device provides an integrated bootstrap voltage regulator. A small capacitor between the

BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed

when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the

BOOT capacitor is 0.1 μF. For stable performance over temperature and voltage, TI recommends a ceramic

capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54540-Q1

device will operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the

voltage from BOOT to SW drops to less than 2.1 V, the high-side MOSFET is turned off and an integrated low-

side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side

MOSFET at high-output voltages, it is disabled at 24-V output and reenabled when the output reaches 21.5 V.

Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on

for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty

cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during

dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-

side diode voltage and the printed-circuit-board resistance.

Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure proper

operation of the device. This calculation must include tolerance of the component specifications and the variation

of these specifications at their maximum operating temperature in the application.

where

• VF= Schottky diode forward voltage

• Rdc = DC resistance of inductor

• RDS(on) = High-side MOSFET resistance

• D = Effective duty cycle of 99% (1)

During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is

being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time

required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle

PWM control.

l TEXAS INSTRUMENTS

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TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

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Product Folder Links: TPS54540B-Q1

Feature Description (continued)

At heavy loads, the minimum input voltage must be increased to insure a monotonic start-up. Equation 2 can be

used to calculate the minimum input voltage for this condition.

VOmax = Dmax × (VVINmin – IOmax × RDS(on) + VF) – VF– IOmax × Rdc

where

• Dmax ≥0.9

• RDS(on) = 1 / (–0.3 × VB2SW2+ 3.577 × VB2SW – 4.246)

• VB2SW = VBOOT + VF

• VBOOT = (1.41 × VVIN – 0.554 – VF× ƒSW – 1.847 × 103× IB2SW) / (1.41 + ƒSW)

• IB2SW = 100 × 10–6A (2)

7.3.5 Error Amplifier

The TPS54540-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier

compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.

The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation,

the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor and capacitor) are connected between the

error amplifier output COMP pin and GND pin.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature

and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor

divider from the output node to the FB pin. TI recommends using 1% tolerance or better divider resistors. Select

the low-side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To improve

efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator

will be more susceptible to noise and voltage errors from the FB input current may become noticeable.

(3)

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54540-Q1 device is enabled when the VIN pin voltage is greater than 4.3 V and the EN pin voltage

exceeds the enable threshold of 1.2 V. The TPS54540-Q1 device is disabled when the VIN pin voltage falls less

than 4 V or when the EN pin voltage is less than 1.2 V. The EN pin has an internal pullup current source, I1, of

1.2 μA that enables operation of the TPS54540-Q1 device when the EN pin floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to

adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional

3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled to less than 1.2 V, the

3.4-μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use

Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to calculate RUVLO2 for

the desired VIN start voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high

input voltages (for example, 40 V), the EN pin may experience a voltage greater than the absolute maximum

voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN

resistors, the EN pin is clamped internally with a 5.8 V Zener diode that will sink up to 150 μA.

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TPS54540B-Q1

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Feature Description (continued)

Figure 22. Adjustable Undervoltage Lockout

(UVLO) Figure 23. Internal EN Clamp

(4)

(5)

7.3.8 Internal Soft Start

The TPS54540-Q1 device has an internal digital soft start that ramps the reference voltage from zero volts to its

final value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6.

(6)

If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft start resets. The

soft start also resets in thermal shutdown.

7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)

The switching frequency of the TPS54540-Q1 device is adjustable over a wide range from 100 kHz to 2500 kHz

by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V, and must

have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching

frequency, use Equation 7 or Equation 8 or the curves in Figure 5 and Figure 6. To reduce the solution size one

would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,

maximum input voltage and minimum controllable on time should be considered. The minimum controllable on

time is typically 135 ns, which limits the maximum operating frequency in applications with high input to output

step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. See

Accurate Current Limit for a more detailed discussion of the maximum switching frequency.

(7)

(8)

l TEXAS INSTRUMENTS

RT/CLK

TPS54540B-Q1

Clock

Source

PLL

RT/CLK

TPS54540B-Q1

Hi-Z

Clock

Source

PLL

TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

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Feature Description (continued)

7.3.10 Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement

this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in

Figure 24. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and

have a pulse-width greater than 15 ns. The synchronization frequency range is from 160 kHz to 2300 kHz. The

rising edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization

circuit should be designed such that the default frequency set resistor is connected from the RT/CLK pin to

ground when the synchronization signal is off. When using a low impedance signal source, the frequency set

resistor is connected in parallel with an ac coupling capacitor to a termination resistor (for example, 50 Ω) as

shown in Figure 24. The two resistors in series provide the default frequency setting resistance when the signal

source is turned off. The sum of the resistance should set the switching frequency close to the external CLK

frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK

pin.

The first time the RT/CLK is pulled above the PLL threshold, the TPS54540-Q1 device switches from the RT

resistor free-running frequency mode to the PLL synchronized mode. The internal 0.5-V voltage source is

removed, and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The

switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device

transitions from the resistor mode to the PLL mode, and locks onto the external clock frequency within 78 µs.

During the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to

150 kHz and then increase or decrease to the resistor programmed frequency when the 0.5-V bias voltage is

reapplied to the RT/CLK resistor.

The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 V to 0.8 V. The device

implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and

fault conditions. Figure 25,Figure 26, and Figure 27 show the device synchronized to an external system clock in

continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-mode).

SPACER

Figure 24. Synchronizing to a System Clock

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TPS54540B-Q1

www.ti.com

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Product Folder Links: TPS54540B-Q1

Feature Description (continued)

Figure 25. Plot of Synchronizing in CCM Figure 26. Plot of Synchronizing in DCM

Figure 27. Plot of Synchronizing in Eco-mode™

7.3.11 Maximum Switching Frequency

To protect the converter in overload conditions at higher switching frequencies and input voltages, the

TPS54540-Q1 device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as

the FB pin voltage falls from 0.8 V to 0 V. The TPS54540-Q1 device uses a digital frequency foldback to enable

synchronization to an external clock during normal start-up and fault conditions. During short circuit events, the

inductor current can exceed the peak current limit because of the high input voltage and the minimum

controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases

slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the

period of the switching cycle providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can

be controlled by frequency foldback protection. Equation 10 calculates the maximum switching frequency at

which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating

frequency should not exceed the calculated value.

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TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

www.ti.com

Product Folder Links: TPS54540B-Q1

Feature Description (continued)

Equation 9 calculates the maximum switching frequency limitation set by the minimum controllable on time and

the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to

skip switching pulses to achieve the low duty cycle required at maximum input voltage.

(9)

where

• IO= Output current

• ICL = Current limit

• Rdc = inductor resistance

• VIN = maximum input voltage

• VOUT = output voltage

• VOUTSC = output voltage during short

• Vd = diode voltage drop

• RDS(on) = switch on resistance

• tON = controllable on time

• ƒDIV = frequency divide equals (1, 2, 4, or 8) (10)

7.3.12 Accurate Current Limit

The TPS54540-Q1 device implements peak current mode control in which the COMP pin voltage controls the

peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin

voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-

side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier

increases switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level

which sets the peak switch current limit. The TPS54540-Q1 device provides an accurate current limit threshold

with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak

inductor current. The relationship between the inductor value and the peak inductor current is shown in

Figure 28.

Figure 28. Current Limit Delay

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www.ti.com

SLVSDX6 –FEBRUARY 2017

Product Folder Links: TPS54540B-Q1

Feature Description (continued)

7.3.13 Overvoltage Protection

The TPS54540-Q1 device incorporates an output overvoltage protection (OVP) circuit to minimize voltage

overshoot when recovering from output fault conditions or strong unload transients in designs with low-output

capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual

output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage

for a considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the

peak current limit threshold. When the overload condition is removed, the regulator output rises and the error

amplifier output transitions to the normal operating level. In some applications, the power supply output voltage

can increase faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin

voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB pin

voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize

output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the

internal voltage reference, the high-side MOSFET resumes normal operation.

7.3.14 Thermal Shutdown

The TPS54540-Q1 device provides an internal thermal shutdown to protect the device when the junction

temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the

thermal trip threshold. Once the die temperature falls to less than 164°C, the device reinitiates the power-up

sequence controlled by the internal soft-start circuitry.

7.3.15 Small Signal Model for Loop Response

Figure 29 shows an equivalent model for the TPS54540-Q1 device control loop, which can be simulated to check

the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a

gmEA of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The

resistor Roand capacitor Comodel the open loop gain and frequency response of the amplifier. The 1-mV AC

voltage source between the nodes a and b effectively breaks the control loop for the frequency response

measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b

provides the small signal response of the overall loop. The dynamic loop response can be evaluated by replacing

RLwith a current source with the appropriate load step amplitude and step rate in a time domain analysis. This

equivalent model is only valid for continuous conduction mode (CCM) operation.

Figure 29. Small Signal Model for Loop Response

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TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

www.ti.com

Product Folder Links: TPS54540B-Q1

Feature Description (continued)

7.3.16 Simple Small Signal Model for Peak Current Mode Control

Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The

TPS54540-Q1 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)

supplying current to the output capacitor and load resistor. The control to output transfer function is shown in

Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in

switch current and the change in COMP pin voltage (node c in Figure 29) is the power stage transconductance,

gmPS. The gmPS for the TPS54540-Q1 device is 17 A/V. The low-frequency gain of the power stage is the

product of the transconductance and the load resistance as shown in Equation 12.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the

load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of

Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB

crossover frequency the same with varying load conditions. The type of output capacitor chosen determines

whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum

electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the

overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14).

Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

(11)

(12)

(13)

(14)

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TPS54540B-Q1

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Feature Description (continued)

7.3.17 Small Signal Model for Frequency Compensation

The TPS54540-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonly-

used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in

Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR

output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or

tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to the small

signal model in Figure 31. The open-loop gain and bandwidth are modeled using the ROand COshown in

Figure 31. See the Typical Applications section for a design example using a Type 2A network with a low ESR

output capacitor.

Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools

to create a design based on the power supply requirements.

Figure 31. Types of Frequency Compensation

Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation

(15)

(16)

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TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

www.ti.com

Product Folder Links: TPS54540B-Q1

Feature Description (continued)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

7.4 Device Functional Modes

The TPS54540-Q1 device is designed to operate with input voltages greater than 4.5 V. When the VIN voltage is

greater than the 4.3 V typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the

device is active. If the VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching.

If the EN voltage falls below the 1.2-V threshold the device stops switching and enters a shutdown mode with low

supply current of 2 μA typical.

The TPS54540-Q1 device operates in CCM when the output current is enough to keep the inductor current

greater than 0 A at the end of each switching period. As a nonsynchronous converter, it will enter DCM at low-

output currents when the inductor current falls to 0 A before the end of a switching period. At very low-output

current the COMP voltage will drop to the pulse-skipping threshold and the device operates in a pulse-skipping

Eco-mode. In this mode, the high-side MOSFET does not switch every switching period. This operating mode

reduces power loss while keeping the output voltage regulated. For more information on Eco-mode, see the

Pulse-Skip Eco-mode section.

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TPS54540B-Q1

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54540-Q1 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device

is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of

5 A. Example applications are: 12-V and 24-V industrial, automotive, and communications power systems. Use

the following design procedure to select component values for the TPS54540-Q1 device. This procedure

illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Calculations can

be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use the WEBENCH

software to generate a complete design. The WEBENCH software uses an iterative design procedure and

accesses a comprehensive database of components when generating a design. This section presents a

simplified discussion of the design process.

8.2 Typical Applications

8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 5-A Output

Figure 33. 3.3-V Output TPS54540 Design Example

8.2.1.1 Design Requirements

This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. A few

parameters must be known to start the design process. These requirements are typically determined at the

system level. This example in Figure 33 is designed with the known parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE

Output Voltage 3.3 V

Transient Response 1.25-A to

3.75-A load step ΔVOUT = 4 %

Maximum Output Current 5 A

Input Voltage 12 V nom. 6 V to 42 V

Output Voltage Ripple 0.5% of VOUT

l TEXAS INSTRUMENTS £l+ + (2+ + 101756 400 (kHz)1

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TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

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Product Folder Links: TPS54540B-Q1

Table 1. Design Parameters (continued)

DESIGN PARAMETERS EXAMPLE VALUE

Start Input Voltage (rising VIN) 5.75 V

Stop Input Voltage (falling VIN) 4.5 V

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest

switching frequency possible because this produces the smallest solution size. High switching frequency allows

for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower

frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power

switch, the input voltage, the output voltage and the frequency foldback protection.

Equation 9 and Equation 10 should be used to calculate the upper limit of the switching frequency for the

regulator (see Equation 25 and Equation 26). Choose the lower value result from the two equations. Switching

frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short

circuit.

The typical minimum on time, tonmin, is 135 ns for the TPS54540-Q1 device. Equation 9 and Equation 10 should

be used to calculate the upper limit of the switching for the regulator (see Equation 25 and Equation 26). For this

example, the output voltage is 3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52

V, inductor DC resistance of 10.3 mΩ, typical switch resistance of 92-mΩand 5-A load, from Equation 9 the

maximum switch frequency to avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern

during short circuits use Equation 10 to determine the maximum switching frequency for frequency fold-back

protection. With a current limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching

frequency is 960 kHz.

For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated

maximums. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in

Equation 7. The switching frequency is set by resistor R3shown in Figure 33. For 400-kHz operation, the closest

standard value resistor is 243 kΩ(see Equation 27).

(25)

(26)

(27)

8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 28.

KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The

inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents

impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal

to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the

designer, however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.

When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is

part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA

for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple

current. This provides sufficient ripple current with the input voltage at the minimum.

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ç ÷

ç ÷ ç ÷

´ ´ ´ m ´

è ø

ç ÷

è ø

( )

OUT OUT

IN max

RIPPLE

O SW

IN max

V (V V ) 3.3 V x (42 V - 3.3 V)

I 1.58 A

V L 42 V x 4.8 H x 400 kHzf

´ -

= = =

´ ´ m

( )

OUT

IN max OUT

O min

OUT IND SW

IN max

V V V42 V - 3.3 V 3.3 V

L 5.1 H

I K V 5 A x 0.3 42 V 400 kHzf

= ´ = ´ = m

´ ´ ´

TPS54540B-Q1

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For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS

current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can

be found from Equation 30 and Equation 31 (using Equation 29). For this design, the RMS inductor current is 5 A

and the peak inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current

rating of 12 A and an RMS current rating of 10 A. This inductor also has a typical inductance of 5.5 µH at no load

and 4.8 µH at a 5-A load. Lastly, the chosen inductor has a DCR of 10.3 mΩ.

As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but

will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of

the regulator but allow for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,

faults or transient load conditions, the inductor current can increase above the peak inductor current level

calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of

the device. For this reason, the most conservative design approach is to choose an inductor with a saturation

current rating equal to or greater than the switch current limit of the TPS54540 device, which is nominally 7.5 A.

(28)

spacer

(29)

spacer

(30)

spacer

(31)

8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in

load current. The output capacitance must be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to

supply the increased load current until the regulator responds to the load step. A regulator does not respond

immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The

regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and

adjust the peak switch current in response to the higher load. The output capacitance must be large enough to

supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.

Equation 32 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw

is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,

the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,

ΔIOUT is 3.75 A – 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. Using these numbers gives a minimum

capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage

change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and

tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to

low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can

produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is

shown in Figure 38. The excess energy absorbed in the output capacitor will increase the voltage on the

capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.

l TEXAS INSTRUMENTS RIPPLE $2

( )

()

( )

OUT OUT

IN max

COUT(rms)

O SW

IN max

V V V 3.3 V 42 V - 3.3 V

I 460 mA

12 V L 12 42 V 4.8 H 400 kHzf

´ - ´

= = =

´ ´ ´ ´ ´ m ´

ORIPPLE

ESR

RIPPLE

V16 mV

R 10 m

I 1.58 A

< = = W

OUT

SW ORIPPLE

RIPPLE

1 1 1 1

C x 30 F

16 mV

8 8 x 400 kHz

1.58 A

> ´ = = m

´æ ö æ ö

ç ÷

ç ÷ è ø

è ø

( ) ( )

( )

( ) ( )

( )

2 2 2 2

OH OL

OUT O 2 2 2 2

f I

I - I 3.75 A - 1.25 A

C L x 4.8 H x 68 F

3.43 V 3.3 V

V - V

> = m = m

OUT

SW OUT

2 I 2 2.5 A

C 95 F

V 400 kHz x 0.13 Vf

´ D ´

> = = m

´ D

TPS54540B-Q1

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Equation 33 calculates the minimum capacitance required to keep the output voltage overshoot to a desired

value, where LOis the value of the inductor, IOH is the output current under heavy load, IOL is the output under

light load, Vfis the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step

will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in

our specification is 4 % of the output voltage. This makes Vf= 1.04 × 3.3 V = 3.43 V. Vi is the initial capacitor

voltage that is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum

capacitance of 68 μF.

Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification,

where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the

inductor ripple current. Equation 34 yields 30 μF.

Equation 35 calculates the maximum ESR an output capacitor must meet the output voltage ripple specification.

Equation 35 indicates the equivalent ESR should be less than 10 mΩ.

The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within

regulation tolerance during a load transient.

Capacitance deratings for aging, temperature and Eco-mode bias increases this minimum value. For this

example, 2 × 100-μF, 6.3-V type X5R ceramic capacitors with 2 mΩof ESR will be used. The derated

capacitance is 130 µF, well above the minimum required capacitance of 95 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor

reliability, especially non ceramic capacitors. Some capacitor data sheets specify the root mean square (RMS)

value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current that the output

capacitor must support. For this example, Equation 36 yields 460 mA.

(32)

(33)

(34)

(35)

(36)

8.2.1.2.4 Catch Diode

The TPS54540 device requires an external catch diode between the SW pin and GND. The selected diode must

have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be

greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due

to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of

42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540-Q1

device.

For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good

thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 V at

5 A and 25°C.

l TEXAS INSTRUMENTS PD 12v 2 I ( < )="" )="" (=""> C ( ) ( ) AV. lo 0.25

OUT

IN SW

I 0.25 5 A 0.25

V 170 mV

C 18.8 F 400 kHzf

´´

D = = =

´ m ´

( ) ( )

( )

()

( )

OUT

IN min

OUT

CI rms

IN min IN min

V V 6 V - 3.3 V

V3.3 V

I I x x 5 A 2.5 A

V V 6 V 6 V

= = ´ =

( )

()( )

( )

OUT OUT

IN max j SW IN

V V I V d C V V d

PV 2

12 V - 3.3 V 5 A x 0.52 V 300 pF x 400 kHz x (12 V 0.52 V) 1.9 W

12 V 2

ff f

- ´ ´ ´ ´ +

= + =

´+

+ =

TPS54540B-Q1

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Product Folder Links: TPS54540B-Q1

The diode must also be selected with an appropriate power rating. The diode conducts the output current during

the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input

voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by

the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher

switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are

due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is

used to calculate the total power dissipation, including conduction losses and AC losses of the diode.

The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode at the

nominal input voltage is 1.9 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a

diode, which has a low leakage current and slightly higher forward voltage drop.

(37)

8.2.1.2.5 Input Capacitor

The TPS54540-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with at

least 3 μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective

capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor

must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater

than the maximum input current ripple of the TPS54540-Q1 device. The input ripple current can be calculated

using Equation 38.

The value of a ceramic capacitor varies significantly with temperature and the Eco-mode bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator

capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The

input capacitor must also be selected with consideration for the DC bias. The effective value of a capacitor

decreases as the DC bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients

up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V,

16 V, 25 V, 50 V or 100 V. For this example, four 4.7-μF, 50-V capacitors in parallel are used. Table 2 lists

several choices of high voltage capacitors.

The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage

ripple occurs at 50% duty cycle and can be calculated using Equation 39. Using the design example values,

IOUT =5A,CIN = 18.8 μF, ƒsw = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current

of 2.5 A.

(38)

(39)

l TEXAS INSTRUMENTS v — v RU S S :2 HYS RU VE s2 UVLO!

OUT

HS LS

V - 0.8 V 3.3 V - 0.8 V

R R x 10.2 k x 31.9 k

0.8 V 0.8 V

æ ö

= = W = W

ç ÷

è ø

ENA

UVLO2

START ENA

UVLO1

V1.2 V

R 88.7 k

V - V 5.75 V - 1.2 V 1.2 A

I365 k

= = = W

+ m

START STOP

UVLO1

HYS

V - V 5.75 V - 4.5 V

R 368 k

I 3.4 A

= = = W

TPS54540B-Q1

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Product Folder Links: TPS54540B-Q1

Table 2. Capacitor Types

VENDOR VALUE (μF) EIA SIZE VOLTAGE DIALECTRIC COMMENTS

Murata

1 to 2.2 1210 100 V

X7R

GRM32 series

1 to 4.7 50 V

11206 100 V GRM31 series

1 to 2.2 50 V

Vishay

1 to 1.8 2220 50 V

VJ X7R series

1 to 1.2 100 V

1 to 3.9 2225 50 V

1 to 1.8 100 V

TDK

1 to 2.2 1812 100 V C series C4532

1.5 to 6.8 50 V

1 to 2.2 1210 100 V C series C3225

1 to 3.3 50 V

AVX

1 to 4.7 1210 50 V

X7R dielectric series

1 100 V

1 to 4.7 1812 50 V

1 to 2.2 100 V

8.2.1.2.6 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic

capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10-V or higher

voltage rating.

8.2.1.2.7 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the

TPS54540-Q1device. The UVLO has two thresholds, one for power-up when the input voltage is rising and one

for power-down or brown outs when the input voltage is falling. For the example design, the supply should turn

on and start switching once the input voltage is greater than 5.75 V (UVLO start). After the regulator starts

switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and

ground connected to the EN pin. Equation 4 and Equation 5 calculate the resistance values necessary. For the

example application, a 365 kΩbetween VIN and EN (RUVLO1) and a 88.7 kΩbetween EN and ground (RUVLO2) are

required to produce the 5.75-V and 4.5-V start and stop voltages.

(40)

(41)

8.2.1.2.8 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩwas selected for R6.

Using Equation 3, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input

current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain

the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher

resistor values decreases quiescent current and improves efficiency at low-output currents but may also

introduce noise immunity problems. For more details about adjusting the output voltage, see Equation 42.

(42)

l TEXAS INSTRUMENTS ‘4 \4 v 0.99 '0 HZ OUT OUT 1 Hz ESR OUT « HZ 7 7 Hz 2 2 WNW) £1

p(mod)

1 1

C5 5100 pF

2 R4 x 2 16.9 k x 1850 Hzf

= = =

´ p ´ ´ p ´ W

co OUT OUT

REF

2 C V 2 30 kHz 130 3.3V

R4 x x 17 k

gmps V x gmea 17 A / V 0.8 V x 350 A / V

fæ ö

´ p´ ´

æ ö æ ö

´ p´ ´ m

æ ö

= = = W

ç ÷

ç ÷ ç ÷

ç ÷ m

è ø è ø

co2 p(mod) x

400 kHz

1850 Hz x 19 kHz

2 2

f f= = =

co1 p(mod) x z(mod) 1850 Hz x 610 kHz 34 kHzf f f= = =

( )

Z mod

ESR OUT

1 1 610 kHz

2 R C 2 1 m 130 F

f= = =

´ p ´ ´ ´ p ´ W ´ m

( )

OUT max

P mod

OUT OUT

I5 A 1850 Hz

2 V C 2 3.3 V 130 F

f= = =

´ p ´ ´ ´ p ´ ´ m

   

 

OUT F dc OUT

IN DS OUT F

V V R I

V min R on I V

0.99

3.3V 0.5V 0.0103 5A

V min 0.12 5A 0.5V 3.99V

0.99

  u

 u 

  : u

 : u 

TPS54540B-Q1

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8.2.1.2.9 Minimum VIN

To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the

device must be above the value calculated with Equation 43 . Using the typical values for the RDS(on), Rdc and VF

in this application example, the minimum input voltage is 3.99 V. The BOOT-SW = 3 V curve in Figure 1 was

used for RDS(on) = 0.12 Ωbecause the device will be operating with low drop out. When operating with low

dropout, the BOOT-SW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed

every switching cycle. In the final application, the values of RDS(on), Rdc and VFused in this equation must include

tolerance of the component specifications and the variation of these specifications at their maximum operating

temperature in the application.

In this application example the calculated minimum input voltage is near the input voltage UVLO for the

TPS54540B-Q1 so the device may turn off before going into drop out.

(43)

8.2.1.2.10 Compensation

There are several methods to design compensation for DC-DC regulators. The method presented here is easy to

calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope

compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the

calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero

and the ESR zero is at least 10 times greater the modulator pole.

To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 44 and

Equation 45. For COUT, use a derated value of 130 μF. Use equations Equation 46 and Equation 47 to estimate a

starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz.

Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of

modulator pole and half of the switching frequency. Equation 46 yields 34 kHz and Equation 47 gives 19 kHz.

Use the geometric mean value of Equation 46 and Equation 47 for an initial crossover frequency. For this

example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved

transient response.

Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a

compensating zero. A capacitor in parallel to these two components forms the compensating pole.

(44)

(45)

(46)

(47)

To determine the compensation resistor, R4, use Equation 48. The typical power stage transconductance, gmps,

is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V,

0.8 V and 350 μA/V, respectively. R4 is calculated to be 17 kΩand a standard value of 16.9 kΩis selected. Use

Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5100 pF for

compensating capacitor C5. 4700 pF is used for this design.

(48)

(49)

l TEXAS INSTRUMENTS R4 16.9 k!) PC [ j W PSW :lex ”ﬂown”:E :12VX 400 kHz X 5A X 4.9 ns : 0.118W PGD :waQGx SW :12v x :3an 400 kHz : 0.014w P0 VI IQ 12V 146% 0.0018W PT :F‘C +Ps +F‘G +PQ:0.958W + 0.118W + 0.014W + 0.0018W:1.092W

( ) ( )

= - ´

TH TOT

A max J max

T T R P

= + ´

J A TH TOT

T T R P

TOT COND SW GD Q

P P P P P 0.958 W 0.118 W 0.014 W 0.0018 W 1.092 W= + + + = + + + =

= ´ = ´ m =

Q IN Q

P V I 12 V 146 A 0.0018 W

GD IN G SW

P V Q 12 V 3nC 400 kHz 0.014 W= ´ ´ = ´ ´ =f

SW IN SW OUT rise

P V I t 12 V 400 kHz 5 A 4.9 ns 0.118 W= ´ ´ ´ = ´ ´ ´ =f

( ) ( )

OUT

COND OUT DS on

V5 V

P I R 5 A 92 m 0.958 W

V 12 V

æ ö

= ´ ´ = ´ W ´ =

ç ÷

è ø

1 1

C8 47 pF

R4 x sw x 16.9 k x 400 kHz xf

= = =

p W p

OUT ESR

C x R 130 F x 1 m

C8 15 pF

R4 16.9 k

m W

= = =

TPS54540B-Q1

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A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series

combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the

compensation pole. The selected value of C8 is 47 pF for this design example.

(50)

(51)

8.2.1.2.11 Power Dissipation Estimate

The formulas in Equation 52 and Equation 58 show how to estimate the TPS54540-Q1 power dissipation under

continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in

discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and

supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.

(52)

spacer

(53)

spacer

(54)

spacer

where

• IOUT is the output current (A)

• RDS(on) is the on-resistance of the high-side MOSFET (Ω)

• VOUT is the output voltage (V)

• VIN is the input voltage (V)

• fsw is the switching frequency (Hz)

• trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns

• QGis the total gate charge of the internal MOSFET

• IQis the operating nonswitching supply current (55)

Therefore,

(56)

For given TA,

(57)

For given TJMAX = 150°C

where

• Ptot is the total device power dissipation (W)

• TAis the ambient temperature (°C)

• TJis the junction temperature (°C)

• RTH is the thermal resistance of the package (°C/W)

• TJMAX is maximum junction temperature (°C)

• TAMAX is maximum ambient temperature (°C) (58)

l TEXAS INSTRUMENTS 'm 'm Ion ‘m

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TA (ƒC)

IOUT (Amps)

18 V

24 V

36 V

C048

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TA (ƒC)

IOUT (Amps)

400 LFM

200 LFM

100 LFM

Nat Conv

C048

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TA (ƒC)

IOUT (Amps)

6 V

12 V

24 V

36 V

C047

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TA (ƒC)

IOUT (Amps)

8 V

12 V

24 V

36 V

C048

TPS54540B-Q1

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There will be additional power losses in the regulator circuit due to the inductor AC and Eco-mode losses, the

catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

8.2.1.2.12 Safe Operating Area

The safe operating area (SOA) of the device is shown in Figure 34, through Figure 37 for 3.3-V, 5-V, and 12-V

outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at

which the TPS54540-Q1 device is at or below the maximum operating temperature. The device is soldered

directly to the EVM, which is a 4-layer double-sided PCB with 2-oz. copper. Careful attention must be paid to the

other components chosen for the design, especially the catch diode.

Figure 34. 3.3-V Outputs Figure 35. 5-V Outputs

Figure 36. 12-V Outputs Figure 37. Air Flow Conditions

VIN = 36 V, VO= 12 V

8.2.1.2.13 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current

is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input

current draw is 240 μA with no load.

i TEXAS INSTRUMENTS _ _______________________ j H: s\wmWwwvwxsxswx

10 mV/div 10 V/div

VOUT ± AC Coupled

Time = 4 Ps/div

1 A/div

10 mV/div 10 V/div

VOUT ± AC Coupled

Time = 4 Ps/div

500 mA/div

IOUT = 100 mA

2 V/div 5 V/div

VIN

VOUT

Time = 20 ms/div

2 V/div

2 V/div 5 V/div

VIN

VOUT

Time = 2 ms/div

2 V/div

100 mV/div 1 A/div

IOUT

VOUT ±3.3V offset

Time = 100 Ps/div

10 mV/div 10 V/div

VIN

VOUT ±3.3V offset

Time = 4 ms/div

TPS54540B-Q1

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Product Folder Links: TPS54540B-Q1

8.2.1.3 Application Curves

Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.

Figure 38. Load Transient Figure 39. Line Transient (8 V to 40 V)

Figure 40. Start-Up With VIN Figure 41. Start-Up With EN

Figure 42. Output Ripple CCM Figure 43. Output Ripple DCM

i TEXAS INSTRUMENTS 1 i , J l . _ III. UL; _________ l 1 \\N‘\N‘\N‘\NNNNN\N \NNNN M WMMWWWW

100

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Efficiency (%)

IO - Output Current (A)

Series4

12V

24V

36V

C024

VIN = 12 V

VIN = 24 V VIN = 36 V

VOUT = 5 V, fsw = 400 kHz

VIN = 7 V

100

0.001 0.01 0.1 1

Efficiency (%)

IO - Output Current (A)

VIN=6V

VIN=12V

VIN=24V

C024

VIN = 12 V

VIN = 24 V

VIN = 36 V

VOUT = 5 V, fsw = 400 kHz

VIN = 7 V

20 mV/div 2 V/div

VOUT = 5 V

Time = 40 Ps/div

200 mA/div

No Load

EN Floating

VIN = 5.5 V

10 mV/div 10 V/div

VIN ± AC Coupled

Time = 4 Ps/div

500 mA/div

IOUT = 100 mA

200 mV/div 10 V/div

VIN ± AC Coupled

Time = 4 Ps/div

1 A/div

10 mV/div 10 V/div

VOUT ± AC Coupled

Time = 1 ms/div

200 mA/div

No Load

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Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.

Figure 44. Output Ripple PSM Figure 45. Input Ripple CCM

Figure 46. Input Ripple DCM Figure 47. Low Dropout Operation

Figure 48. Efficiency vs Load Current Figure 49. Light Load Efficiency

l TEXAS INSTRUMENTS

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Output Voltage Normalized (%)

Output Current (A)

C054

VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz

±0.20

±0.15

±0.10

±0.05

0.00

0.05

0.10

0.15

0.20

0 5 10 15 20 25 30 35 40 45

Output Voltage Normalized (%)

Input Voltage (V)

C055

VIN = 12 V, IOUT = 5 A, fsw = 400 kHz

100

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Efficiency (%)

IO - Output Current (A)

18in

Series1

Series3

C024

VIN = 18 V

VIN = 24 V

VIN = 36 V

VOUT = 12 V, fsw = 800 kHz

±180

±150

±120

±90

±60

±30

120

150

180

±60

±50

±40

±30

±20

±10

10 100 1k 10k 100k 1M

Phase (£)

Gain (dB)

Frequency (Hz)

Gain

Phase

C053

VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A

100

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Efficiency (%)

Load Current (A)

VIN = 6 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

C050

VIN = 6 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

VOUT = 3.3 V, fsw = 400 kHz

100

0.001 0.01 0.1 1

Efficiency (%)

Load Current (A)

VIN = 6 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

C051

VIN = 6 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

VOUT = 3.3 V, fsw = 400 kHz

TPS54540B-Q1

SLVSDX6 –FEBRUARY 2017

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Product Folder Links: TPS54540B-Q1

Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.

Figure 50. Efficiency vs Load Current Figure 51. Light Load Efficiency

Figure 52. Efficiency vs Output Current Figure 53. Overall Loop Frequency Response

Figure 54. Regulation vs Load Current Figure 55. Regulation vs Input Voltage

VIN

GND

BOOT

COMP

TPS54540B-Q1

RT /CLK

CPOLE

CZERO

RCOMP

CONEG

CBOOT

CIN

VIN

VONEG

GND

VOPOS

COPOS

VIN BOOT SW

GND

TPS54540B-Q1

COMP

RT/CLK

VIN

CIN CBOOT

GND

VOUT

RT CZERO CPOLE

RCOMP

TPS54540B-Q1

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Product Folder Links: TPS54540B-Q1

8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output

The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative

output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and

negative voltage power supply. For a more detailed example, see SLVA317.

Figure 56. TPS54540-Q1 Inverting Power Supply from SLVA317 Application Note

8.2.3 Split-Rail Power Supply

The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative

output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and

negative voltage power supply. For a more detailed example, see SLVA369.

Figure 57. TPS54540-Q1 Split Rail Power Supply Based on the SLVA369 Application Note

‘5‘ TEXAS INSTRUMENTS iTI

BOOT

VIN

RT/CLK

GND

COMP

Input

Bypass

Capacitor

UVLO

Adjust

Resistors

Frequency

Set Resistor

Compensation

Network Resistor

Divider

Output

Inductor

Output

Capacitor

Vout

Vin

Topside

Ground

Area Catch

Diode

Route Boot Capacitor

Trace on another layer to

provide wide path for

topside ground

Thermal VIA

Signal VIA

TPS54540B-Q1

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Product Folder Links: TPS54540B-Q1

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 4.5 V to 42 V. This input supply must

remain within this range. If the input supply is located more than a few inches from the TPS54540-Q1 converter,

additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic

capacitor with a value of 100 μF is a typical choice.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast

changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise

or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low-ESR

ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass

capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 58 for a PCB layout example.

The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad must be connected to internal PCB ground planes using multiple vias directly under the IC. The

SW pin should be routed to the cathode of the catch diode and to the output inductor. Because the SW

connection is the switching node, the catch diode and output inductor must be located close to the SW pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated

load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise

so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The

additional external components can be placed approximately as shown. It may be possible to obtain acceptable

performance with alternate PCB layouts; however, this layout has been shown to produce good results and is

meant as a guideline.

10.2 Layout Example

Figure 58. PCB Layout Example

l TEXAS INSTRUMENTS

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10.3 Estimated Circuit Area

Boxing in the components in the design of Figure 33 the estimated printed-circuit-board area is 1.025 in2

(661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be

done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

For the TPS54360 and TPS54361 Family Design Excel Tool, see the following:

• Design Calculator zip file (SLVC452)

11.1.2 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•Creating GSM Power Supply from TPS54260 (SLVA412)

•Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511 (SLVA464)

•Create an Inverting Power Supply from a Step-Down Regulator (SLVA317)

•Create a Split-Rail Power Supply with a Wide Input Voltage Buck Regulator (SLVA369)

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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Product Folder Links: TPS54540B-Q1

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS54540BQDDAQ1 ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 5454BQ

TPS54540BQDDARQ1 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 5454BQ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

OTHER QUALIFIED VERSIONS OF TPS54540B-Q1 :

•Catalog: TPS54540B

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

I TEXAS INSTRUMENTS

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

DDA 8 PowerPAD TM SOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

4202561/G

MECHANICAL DATA DC’ Powe’DAD W 3‘ AST‘C SMA‘ \ iOUi N7 {iﬁnm PAT: 7‘: m w sum mm m 5mm s-«EV VOTES' A AH \meur dime'ysors are n mﬂhmeiers Dvrensm'vng ard memncmg per ASME “4571994. 5. 'ms drawing is suaject :o mange w‘wom whee. C Body m'r‘ensm'vs co m mcmce mo‘d Hush m provusm'v no‘ to excess 0,15 D ’h‘s package 15 dcsw'gnud {a be smccrcd (a u thavma‘ pad or We bnurd Rafe! to Tuchw'wuu Er'uf‘ PowurFod 'rermauy Enhance: Pucmge, 'exas nsimments {mm M. swwoz m 'nformufmn regurqu reccmmended mm cywk This documeM is cvm‘uh‘e :1 www um See the addwtmnu‘ ﬁgue m [we Pronuct Dal: sree: {m detuﬂs 'egc'cmq (he exposen thermo‘ pud {eciures c'vd d'mensmns TM: package comp‘es m JEDEC M57012 va'mﬁnn EA PowerPAD is a trademavk MTexas \nsuuments. J5 TEXAS INSTRUMENTS wwwxi .com

THERMAL PAD MECHANICAL DATA DDA (R—PDSO—GB) PowerPADm PLASTiC SMALL OUTLiNE THERMAL iNFORMATION This PowerPADl'package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board (PCB). The thermal pad must be soldered directly to the PCB. Alter soldering. the PCB can he used as a heatsink. In addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively. can be attached to a special heatsink structure designed into the PCB, This design optimizes the heat transter trom the integrated circuit (iC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas instruments Literature No. SLMAOOZ and Application Brief, PowerPAD Made Easy, Texas instruments Literature No. SLMAOO4. Both documents are available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration. 8 5 H H H H T '— — —- — 1 Exposed Thermal Pad 2.40 |_ ‘ J 1.65 | ‘ i l L7 ~74 H H H H 1 ﬂ 4 2,55 Top new Exposed Thermal Pad Dimensions 420632276/L 05/12 NOTE: A, All linear dimensions are in millimeters PowerPAD is a trademark of Texas Instruments {I} TEXAS INSTRUMENTS www.ti.com

LAND PATTERN DATA DDA (R—PDSO—GS) PowerPADTM PLASTIC SMALL OUTLINE Example Board Layout o.i27mm Thicx stencil Design Example \ﬁa panern and mm, M 5iZe Reierence table below lor other may vary depending on layout constraints solder slencll thicknesses (Nate E) “LEO NOTES: F, Fame») is a tract solder mask over copper i.27 0,45» <_ it—i»="" l,27="" --------="" —="" 2,i5="" -—-—-—-—-—="" kilo»="" 5,="" 5="" y="" 2.40="" 5,75="" example="" solder="" mosx="" defined="" pad="" (see="" note="" c.="" d)="" mask="" defined="" pad="" xdmple="" solder="" mask="" opening="" \e="" .="" (nate="" f)="" center="" power="" pad="" solder="" stencil="" opening="" stencil="" thickness="" x="" y="" 0.1mm="" 3.3="" 2.6="" 0.l27mm="" 3.1="" 2.4="" 0.152mm="" 2.9="" 2.2="" pad="" geometry="" 0,l78mm="" 2.8="" 2.l="" (note="" c)="" all="" around="" 4208951-6/[1="" 04/12="" all="" linear="" dimensions="" are="" in="" millimeters.="" this="" drawing="" is="" subject="" to="" change="" without="" notice.="" publication="" ch77351="" is="" recommended="" tor="" alternate="" designs.="" this="" package="" is="" designed="" to="" be="" soldered="" to="" a="" thermal="" pad="" on="" the="" board="" reier="" to="" rechnical="" brier.="" pdwerpdd="" thermally="" enhanced="" package.="" texas="" lnstruments="" literature="" no.="" slmaooz,="" slmaoo4.="" and="" also="" the="" product="" data="" sheets="" ior="" speciﬁc="" thermal="" inlormation.="" v'la="" requirements,="" and="" recommended="" board="" layout.="" these="" documents="" are="" available="" at="" xwwticom="">. Publication che755l is recommended tar alternate designs. Laser culling apertures with trapezoidal walls and also rounding corners will otter better paste release. Customers should contact their board assembly site for stencil design recommendations. Example stencil design based on a sex volumetric metal load solder paste. Reler to ch—7525 tor other stencil recommendations. Customers should Contact Meir board lubrication sile for solder musk lolerunces between and around signal pads. amwk at Texas lnxlmmenls. {I} TEXAS INSTRUMENTS www.li.cam

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS54540B-Q1 Datasheet by Texas Instruments

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