ADS7887, ADS7888 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS Capvngm 92m Texas \nslmmzms mmmua
SCLK
+IN
VDD
CDAC
SAR
COMPARATOR
OUTPUT
LATCHES
AND
3−STATE
DRIVERS
CONVERSION
AND
CONTROL
LOGIC
SDO
ADS7887/ADS7888 CS
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7887
,
ADS7888
SLAS468A –JUNE 2005–REVISED AUGUST 2016
ADS788x 10-Bit, 8-Bit, 1.25-MSPS, Micro-Power,
Miniature SAR Analog-to-Digital Converters
1
1 Features
1• 1.25-MHz Sample Rate Serial Device
• 10-Bit Resolution (ADS7887)
• 8-Bit Resolution (ADS7888)
• Zero Latency
• 25-MHz Serial Interface
• Supply Range: 2.35 V to 5.25 V
• Typical Power Dissipation at 1.25 MSPS:
– 3.8 mW at 3-V VDD
– 8 mw at 5-V VDD
• ±0.35 LSB INL, DNL (ADS7887)
• ±0.15 LSB INL, ±0.1 LSB DNL (ADS7888)
• 61 dB SINAD, –84 dB THD (ADS7887)
• 49.5 dB SINAD, –67.5 dB THD (ADS7888)
• Unipolar Input Range: 0 V to VDD
• Power-Down Current: 1 µA
• Wide Input Bandwidth: 15 MHz at 3 dB
• 6-Pin SOT23 and SC70 Packages
2 Applications
• Base Band Converters in Radio Communication
• Motor Current and Bus Voltage Sensors in Digital
Drives
• Optical Networking (DWDM, MEMS-Based
Switching)
• Optical Sensors
• Battery-Powered Systems
• Medical Instrumentations
• High-Speed Data Acquisition Systems
• High-Speed Closed-Loop Systems
3 Description
The ADS7887 device is a 10-bit, 1.25-MSPS, analog-
to-digital converter (ADC), and the ADS7888 device
is a 8-bit, 1.25-MSPS ADC. These devices include a
capacitor-based SAR A/D converter with inherent
sample and hold. The serial interface in each device
is controlled by the CS and SCLK signals for glueless
connections with microprocessors and DSPs. The
input signal is sampled with the falling edge of CS,
and SCLK is used for conversion and serial data
output.
The devices operate from a wide supply range from
2.35 V to 5.25 V. The low power consumption of the
devices make them suitable for battery-powered
applications. The devices also include a power-
saving, power-down feature for when the devices are
operated at lower conversion speeds.
The high level of the digital input to the device is not
limited to device VDD. This means the digital input can
go as high as 5.25 V when device supply is 2.35 V.
This feature is useful when digital signals are coming
from other circuit with different supply levels. Also this
relaxes restriction on power-up sequencing.
The ADS7887 and ADS7888 are available in 6-pin
SOT-23 and SC70 packages and are specified for
operation from –40°C to 125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
ADS7887
ADS7888
SOT-23 (6) 2.90 mm × 1.60 mm
SC70 (6) 2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Companion Products............................................. 3
6 Device Comparison ............................................... 4
7 Pin Configuration and Functions......................... 5
8 Specifications......................................................... 6
8.1 Absolute Maximum Ratings ...................................... 6
8.2 ESD Ratings.............................................................. 6
8.3 Recommended Operating Conditions....................... 6
8.4 Thermal Information.................................................. 6
8.5 Electrical Characteristics – ADS7887 ....................... 7
8.6 Electrical Characteristics – ADS7888 ....................... 8
8.7 Timing Requirements................................................ 9
8.8 Typical Characteristics............................................ 10
9 Detailed Description............................................ 16
9.1 Overview ................................................................ 16
9.2 Functional Block Diagram....................................... 16
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 23
13 Device and Documentation Support ................. 24
13.1 Documentation Support ........................................ 24
13.2 Related Links ........................................................ 24
13.3 Receiving Notification of Documentation Updates 24
13.4 Community Resources.......................................... 24
13.5 Trademarks........................................................... 24
13.6 Electrostatic Discharge Caution............................ 24
13.7 Glossary................................................................ 24
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2005) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Changed Thermal Information table....................................................................................................................................... 6
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,
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5 Companion Products
PART NUMBER NAME
SN74LVTH245A 3.3-V ABT Octal Bus Transceivers With 3-State Outputs
LMV761 Low Voltage, Precision Comparator with Push-Pull Output
TPS54418 2.95V to 6V Input, 4A Synchronous Step-Down SWIFT™ Converter
LMV339 Quad General Purpose Low-Voltage Comparators
TPS730 Low-Noise, High PSRR, RF 200-mA Low-Dropout Linear Regulators
l TEXAS INSTRUMENTS
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6 Device Comparison
BIT < 300 KSPS 300 KSPS – 1.25 MSPS
12-Bit ADS7866 (1.2 VDD to 3.6 VDD) ADS7886 (2.35 VDD to 5.25 VDD)
10-Bit ADS7867 (1.2 VDD to 3.6 VDD) ADS7887 (2.35 VDD to 5.25 VDD)
8-Bit ADS7868 (1.2 VDD to 3.6 VDD) ADS7888 (2.35 VDD to 5.25 VDD)
l TEXAS INSTRUMENTS
Not to scale
1VDD 6 CS
2GND 5 SDO
3VIN 4 SCLK
5
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,
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7 Pin Configuration and Functions
DBV or DCK Package
6-Pin SOT-23 or SC70
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 VDD — Power supply input also acts like a reference voltage to ADC.
2 GND — Ground for power supply, all analog and digital signals are referred with respect to this pin.
3 VIN I Analog signal input
4 SCLK I Serial clock
5 SDO O Serial data out
6 CS I Chip select signal, active low
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SLAS468A –JUNE 2005–REVISED AUGUST 2016
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
+IN to AGND –0.3 VDD + 0.3 V
+VDD to AGND –0.3 7 V
Digital input voltage to GND –0.3 7 V
Digital output to GND –0.3 VDD + 0.3 V
Power dissipation, both packages (TJ(MAX) – TA) / RθJA
Lead temperature, soldering Vapor phase (60 s) 215 °C
Infrared (15 s) 220
Junction temperature, TJ(MAX) 150 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
TAOperating temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.4 Thermal Information
THERMAL METRIC(1)
ADS7887, ADS7888
UNITDBV (SOT-23) DCK (SC70)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 114.9 150.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.6 62.3 °C/W
RθJB Junction-to-board thermal resistance 36.5 43 °C/W
ψJT Junction-to-top characterization parameter 5.8 1.8 °C/W
ψJB Junction-to-board characterization parameter 36.2 42.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
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(1) Ideal input span; does not include gain or offset error.
(2) Refer Figure 31 for details on sampling circuit
(3) LSB means least significant bit
(4) Measured relative to an ideal full-scale input
(5) Offset error and gain error ensured by characterization.
(6) First transition of 000H to 001H at 0.5 × (Vref/210)
(7) Calculated on the first nine harmonics of the input frequency
8.5 Electrical Characteristics – ADS7887
+VDD = 2.35 V to 5.25 V, TA= –40°C to 125°C, and fsample = 1.25 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span(1) 0 VDD V
Absolute input voltage range +IN –0.2 VDD + 0.2 V
CiInput capacitance(2) 21 pF
IIlkg Input leakage current TA= 125°C 40 nA
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
INL Integral nonlinearity –0.75 ±0.35 0.75 LSB(3)
DNL Differential nonlinearity –0.5 ±0.35 0.5 LSB
EOOffset error(4)(5)(6) –1.5 ±0.5 1.5 LSB
EGGain error(5) –1 ±0.5 1 LSB
SAMPLING DYNAMICS
Conversion time 25-MHz SCLK 530 560 ns
Acquisition time 260 ns
Maximum throughput rate 25-MHz SCLK 1.25 MHz
Aperture delay 5 ns
Step Response 160 ns
Overvoltage recovery 160 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion(7) 100 kHz –84 –72 dB
SINAD Signal-to-noise and distortion 100 kHz 60.5 61 dB
SFDR Spurious free dynamic range 100 kHz 73 81 dB
Full power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
VIH High-level input voltage VDD = 2.35 V to 5.25 V VDD – 0.4 5.25 V
VIL Low-level input voltage VDD = 5 V 0.8 V
VDD = 3 V 0.4
VOH High-level output voltage At Isource = 200 µA VDD – 0.2 V
VOL Low-level output voltage At Isink = 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+VDD Supply voltage 2.35 3.3 5.25 V
Supply current (normal mode)
At VDD = 2.35 V to 5.25 V,
1.25-MHz throughput 2mA
At VDD = 2.35 V to 5.25 V, static state 1.5
Power-down state supply current SCLK off 1 µA
SCLK on (25 MHz) 200
Power dissipation
at 1.25-MHz throughput
VDD = 5 V 8 10 mW
VDD = 3 V 3.8 6
Power dissipation in static state VDD = 5 V 5.5 7.5 mW
VDD = 3 V 3 4.5
Power-down time 0.1 µs
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Electrical Characteristics – ADS7887 (continued)
+VDD = 2.35 V to 5.25 V, TA= –40°C to 125°C, and fsample = 1.25 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time 0.8 µs
Invalid conversions after power up 1
(1) Ideal input span; does not include gain or offset error.
(2) Refer Figure 31 for details on sampling circuit
(3) LSB means least significant bit
(4) Measured relative to an ideal full-scale input
(5) Offset error and gain error ensured by characterization.
(6) First transition of 000H to 001H at (Vref/28)
(7) Calculated on the first nine harmonics of the input frequency
8.6 Electrical Characteristics – ADS7888
+VDD = 2.35 V to 5.25 V, TA= –40°C to 125°C, and fsample = 1.25 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span(1) 0 VDD V
Absolute input voltage range +IN –0.2 VDD + 0.2 V
CiInput capacitance(2) 21 pF
IIlkg Input leakage current TA= 125°C 40 nA
SYSTEM PERFORMANCE
Resolution 8 Bits
No missing codes 8 Bits
INL Integral nonlinearity –0.3 ±0.15 0.3 LSB(3)
DNL Differential nonlinearity –0.3 ±0.1 0.3 LSB
EOOffset error(4) (5) (6) –0.5 ±0.15 0.5 LSB
EGGain error(5) –0.5 ±0.15 0.5 LSB
SAMPLING DYNAMICS
Conversion time 25-MHz SCLK 450 480 ns
Acquisition time 1.5 MSPS mode, see Figure 34 206 ns
Maximum throughput rate 25-MHz SCLK 1.25 MHz
Aperture delay 5 ns
Step Response 160 ns
Overvoltage recovery 160 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion(7) 100 kHz –67.5 –65 dB
SINAD Signal-to-noise and distortion 100 kHz 49 49.5 dB
SFDR Spurious free dynamic range 100 kHz 65 77 dB
Full power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
VIH High-level input voltage VDD = 2.35 V to 5.25 V VDD – 0.4 5.25 V
VIL Low-level input voltage VDD = 5 V 0.8 V
VDD = 3 V 0.4
VOH High-level output voltage At Isource = 200 µA VDD – 0.2 V
VOL Low-level output voltage At Isink = 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+VDD Supply voltage 2.35 3.3 5.25 V
Supply current (normal mode)
At VDD = 2.35 V to 5.25 V, 1.25-MHz
throughput 2mA
At VDD = 2.35 V to 5.25 V, static state 1.5
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Electrical Characteristics – ADS7888 (continued)
+VDD = 2.35 V to 5.25 V, TA= –40°C to 125°C, and fsample = 1.25 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-down state supply current SCLK off 1 µA
SCLK on (25 MHz) 200
Power dissipation at 1.25 MHz
throughput
VDD = 5 V 8 10 mW
VDD = 3 V 3.8 6
Power dissipation in static state VDD = 5 V 5.5 7.5 mW
VDD = 3 V 3 4.5
Power-down time 0.1 µs
Power-up time 0.8 µs
Invalid conversions after power up 1
(1) 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
8.7 Timing Requirements
All specifications typical at TA= –40°C to 125°C and VDD = 2.35 V to 5.25 V (unless otherwise noted; see Figure 32)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
tconv Conversion time
ADS7887 VDD = 3 V 14 × tSCLK
ns
VDD = 5 V 14 × tSCLK
ADS7888 VDD = 3 V 12 × tSCLK
VDD = 5V 12 × tSCLK
tqQuiet time Minimum time required from bus 3-state
to start of next conversion
VDD = 3 V 40 ns
VDD = 5 V 40
td1 Delay time CS low to first data (0) out VDD = 3 V 15 25 ns
VDD = 5 V 13 25
tsu1 Setup time CS low to SCLK low VDD = 3 V 10 ns
VDD = 5 V 10
td2 Delay time SCLK falling to SDO VDD = 3 V 15 25 ns
VDD = 5 V 13 25
th1 Hold time SCLK falling to data valid (with 50-pF
load)
VDD < 3 V 7 ns
VDD > 5 V 5.5
td3 Delay time 16th SCLK falling edge to SDO 3-state VDD = 3 V 10 25 ns
VDD = 5 V 8 20
tw1 Pulse duration CS VDD = 3 V 25 40 ns
VDD = 5 V 25 40
td4 Delay time CS high to SDO 3-state, see Figure 34 VDD = 3 V 17 30 ns
VDD = 5 V 15 25
twH Pulse duration SCLK high VDD = 3 V 0.4 × tSCLK ns
VDD = 5 V 0.4 × tSCLK
twL Pulse duration SCLK low VDD = 3 V 0.4 × tSCLK ns
VDD = 5 V 0.4 × tSCLK
Frequency SCLK VDD = 3 V 25 MHz
VDD = 5 V 25
td5 Delay time
Second falling edge of clock and CS to
enter in power down (use min spec not to
accidently enter in power down, see
Figure 35)
VDD = 3 V –2 5
ns
VDD = 5 V –2 5
td6 Delay time
CS and 10th falling edge of clock to enter
in power down (use max spec not to
accidently enter in power down, see
Figure 35)
VDD = 3 V 2 –5
ns
VDD = 5 V 2 –5
l TEXAS INSTRUMENTS who '5ch 14 :m
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 50 100 150 200 250 300 350 400 450
IDD − Supply Current − mA
fs− Sample Rate − KSPS
VDD = 5 V,
fSCLK = 25 MHz,
TA= 25°C,
Power Down SCLK = Free Running
30
20
10
0
−10
−20
−30
−40
−40 −20 20 8060 120
@ 5 V Input
@ 0 V Input
Leakage Current − nA
TA− Free-Air Temperature − °C
0 40 100
0
0.20
0.40
0.60
0.80
1
1.20
1.40
1.60
1.80
0 5 10 15 20 25
IDD − Supply Current − mA
fSCLK − SCLK Frequency − MHz
5 V VDD
2.35 V VDD
TA= 25°C
10
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8.8 Typical Characteristics
8.8.1 ADS7887 and ADS7888
Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs SCLK Frequency
Figure 3. Supply Current vs Sample Rate Figure 4. Analog Input Leakage Current
vs Free-Air Temperature
{9 TEXAS INSTRUMENTS vDo mu . 5.5.5 255;: .2: . E: Van mu . Eesms 2.3.5»: is». e:
80
80.5
81
81.5
82
82.5
83
83.5
84
84.5
85
110 100
SFDR − Spurious Free Dynamic Range − dB
fi− Input Frequency − kHz
fs= 1.25 MSPS,
TA= 25°C,
VDD = 5 V
80
80.5
81
81.5
82
82.5
83
83.5
84
84.5
85
2.35 3.075 3.8 4.525 5.25
SFDR − Spurious Free Dynamic Range − dB
fs= 1.25 MSPS,
fi= 100 kHz,
TA= 25°C
VDD − Supply Voltage − V
−90
−89
−88
−87
−86
−85
−84
−83
−82
−81
−80
1 10 100
fi− Input Frequency − kHz
fs= 1.25 MSPS,
TA= 25°C
VDD = 5 V
THD − T
otal Harmonic Distortion − dB
−90
−89
−88
−87
−86
−85
−84
−83
−82
−81
−80
2.35 3.075 3.8 4.525 5.25
fs= 1.25 MSPS,
fi= 100 kHz,
TA= 25°C
THD − T
otal Harmonic Distortion − dB
VDD − Supply Voltage − V
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
2.35 3.075 3.8 4.525 5.25
fs= 1.25 MSPS,
fi= 100 kHz,
TA= 25°C
SINAD − Signal-to-Noise and Distortion − dB
VDD − Supply Voltage − V
60.5
60.7
60.9
61.1
61.3
61.5
61.7
61.9
1 10 100 1000
fi− Input Frequency − kHz
SINAD − Signal-to-Noise and Distortion − dB
fs= 1.25 MSPS,
TA= 25°C,
VDD = 5 V
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8.8.2 ADS7887 Only
Figure 5. Signal-to-Noise and Distortion
vs Input Frequency Figure 6. Signal-to-Noise and Distortion
vs Supply Voltage
Figure 7. Total Harmonic Distortion
vs Input Frequency Figure 8. Total Harmonic Distortion
vs Supply Voltage
Figure 9. Spurious Free Dynamic Range
vs Input Frequency
Figure 10. Spurious Free Dynamic Range
vs Supply Voltage
l TEXAS INSTRUMENTS vDo
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
DNL − LSBs
Output Code
VDD = 2.35 V,
fs= 1.25 MSPS,
TA= 25 C°
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Output Code
INL − LSBs
VDD = 2.35 V,
fs= 1.25 MSPS,
TA= 25°C
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
2.35 3.075 3.8 4.525 5.25
EG− Gain Error − LSBs
fs= 1.25 MSPS,
TA= 25°C
VDD − Supply Voltage − V
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
−40 −20 0 20 40 60 80 100 120
EG− Gain Error − LSBs
TA− Free-Air Temperature − °C
fs= 1.25 MSPS,
VDD = 5 V
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
2.35 3.075 3.8 4.525 5.25
EO− Offset Error − LSBs
fs= 1.25 MSPS,
TA= 25°C
VDD − Supply Voltage − V
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
−40 −20 0 20 40 60 80 100 120
EO− Offset Error − LSBs
fs= 1.25 MSPS,
VDD = 5 V
TA− Free-Air Temperature − °C
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ADS7887 Only (continued)
Figure 11. Offset Error vs Supply Voltage Figure 12. Offset Error vs Free-Air Temperature
Figure 13. Gain Error vs Supply Voltage Figure 14. Gain Error vs Free-Air Temperature
Figure 15. DNL Figure 16. INL
{9 TEXAS INSTRUMENTS an mu 1 muzznia mu . 35...: 2.35;: .25 . 5: Von mu . 33...: 2:25“: .2: . E;
−70
−69.5
−69
−68.5
−68
−67.5
−67
−66.5
−66
−65.5
−65
1 10 100
THD − T
otal Harmonic Distortion − dB
VDD = 5 V,
fs= 1.25 MSPS,
TA= 25°C
fi− Input Frequency − kHz
−70
−69.5
−69
−68.5
−68
−67.5
−67
−66.5
−66
−65.5
−65
2.35 3.075 3.8 4.525 5.25
THD − T
otal Harmonic Distortion − dB
VDD − Supply Voltage − V
fi= 100 kHz,
fs= 1.25 MSPS,
TA= 25°C
49
49.1
49.2
49.3
49.4
49.5
49.6
49.7
49.8
49.9
50
2.35 3.075 3.8 4.525 5.25
SINAD − Signal-to-Noise and Distortion − dB
fs= 1.25 MSPS,
fi= 100 kHz,
TA= 25°C
VDD − Supply Voltage − V
49
49.1
49.2
49.3
49.4
49.5
49.6
49.7
49.8
49.9
50
1 10 100 1000
SINAD − Signal-to-Noise and Distortion − dB
fi− Input Frequency − kHz
fs= 1.25 MSPS,
TA= 25°C,
VDD = 5 V
−140
−120
−100
−80
−60
−40
−20
0
0 125000 250000 375000 500000 625000
Amplitude − dB
fi− Input Frequency − kHz
VDD = 2.35 V,
fs= 1.25 MSPS,
TA= 25°C
fi= 100 kHz,
8192 Points
13
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ADS7887 Only (continued)
Figure 17. FFT
8.8.3 ADS7888 Only
Figure 18. Signal-to-Noise and Distortion
vs Input Frequency Figure 19. Signal-to-Noise and Distortion
vs Supply Voltage
Figure 20. Total Harmonic Distortion
vs Input Frequency
Figure 21. Total Harmonic Distortion
vs Supply Voltage
l TEXAS INSTRUMENTS v. VD» ma n: u n: 0,3
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
−40 −7 26 59 92 125
EG− Gain Error − LSBs
fs= 1.25 MSPS,
TA= 25°C
TA− Free-Air Temperature − °C
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
2.35 3.075 3.8 4.525 5.25
EG− Gain Error − LSBs
fs= 1.25 MSPS,
TA= 25°C
VDD − Supply Voltage − V
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
−40 −7 26 59 92 125
EO− Offset Error − LSBs
fs= 1.25 MSPS,
VDD = 5 V
TA− Free-Air Temperature − °C
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
2.35 3.075 3.8 4.525 5.25
EO− Offset Error − LSBs
fs= 1.25 MSPS,
TA= 25°C
VDD − Supply Voltage − V
75
75.5
76
76.5
77
77.5
78
78.5
79
79.5
80
1 10 100
SFDR − Spurious Free Dynamic Range − dB
VDD = 5 V,
fs= 1.25 MSPS,
TA= 25°C
fi− Input Frequency − kHz
75
76
77
78
79
80
81
82
83
84
85
2.35 3.075 3.8 4.525 5.25
SFDR − Spurious Free Dynamic Range − dB
VDD − Supply Voltage − V
fi= 100 kHz,
fs= 1.25 MSPS,
TA= 25°C
14
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ADS7888 Only (continued)
Figure 22. Spurious Free Dynamic Range
vs Input Frequency
Figure 23. Spurious Free Dynamic Range
vs Supply Voltage
Figure 24. Offset Error vs Supply Voltage Figure 25. Offset Error vs Free-Air Temperature
Figure 26. Gain Error vs Supply Voltage Figure 27. Gain Error vs Free-Air Temperature
i TEXAS INSTRUMENTS Amplitude — dB mm“ “qu w ”Lunwmlll. WWW! [um 'I lwl mlhlllldhlfl W V mun" "‘H'I' m w .n m Uumulmm W n ‘. MW.” “HUM. 'IILJIM “MW \MJWL. ml IL HIM w‘lll‘
−120
−100
−80
−60
−40
−20
0
0 125000 250000 375000 500000 625000
Amplitude − dB
fi− Input Frequency − kHz
TA= 25°C
fi= 100 kHz,
8192 Points
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 64 128 192 256
DNL − LSBs
Output Code
VDD = 2.35 V,
fs= 1.25 MSPS,
TA= 25°C
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 64 128 192 256
Output Code
INL − LSBs
VDD = 2.35 V,
fs= 1.25 MSPS,
TA= 25°C
15
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ADS7888 Only (continued)
Figure 28. DNL Figure 29. INL
Figure 30. FFT
l TEXAS INSTRUMENTS \\ 1: 'n GND Cupyngmmoqe, Texas Insimmems Incurpura|ed
SCLK
+IN
VDD
CDAC
SAR
COMPARATOR
OUTPUT
LATCHES
AND
3−STATE
DRIVERS
CONVERSION
AND
CONTROL
LOGIC
SDO
ADS7887/ADS7888 CS
Copyright © 2016, Texas Instruments Incorporated
60 W
60 W16 pF
20 W
5 pF
VDD
IN
GND
16
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9 Detailed Description
9.1 Overview
The ADS788x devices are ADC converters. The serial interface in each device is controlled by the CS and SCLK
signals for easy interface with microprocessors and DSPs. The input signal is sampled with the falling edge of
CS, and SCLK is used for conversion and serial data output. They both operate in a wide supply range from 2.35
V to 5.25 V and low power consumption makes them suitable for battery-powered applications.
9.1.1 Driving the VIN and VDD Pins of the ADS7887 and ADS7888
The VIN input to the ADS7887 and ADS7888 must be driven with a low impedance source. In most cases
additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would
help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier
buffer.
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage
internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters must
be driven with a low impedance source and must be decoupled to the ground. A 1-µF storage capacitor and a
10-nF decoupling capacitor must be placed close to the device. Wide, low impedance traces must be used to
connect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from the
supply lines. The supply line can be driven by either:
• Directly from the system supply.
• A reference output from a low drift and low dropout reference voltage generator like REF3030 or REF3130.
The ADS7887 and ADS7888 can operate off a wide range of supply voltages. The actual choice of the
reference voltage generator would depend upon the system. Figure 41 shows one possible application circuit.
• A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be
used in cases where the system power supply is noisy. Take care to ensure that the voltage at the VDD input
does not exceed 7 V (especially during power up) to avoid damage to the converter. This can be done easily
using single-supply CMOS amplifiers like the OPA735. Figure 42 shows one possible application circuit.
Figure 31. Typical Equivalent Sampling Circuit
9.2 Functional Block Diagram
l TEXAS INSTRUMENTS
12 4 5614 15
CS
SCLK
SDO 00 0 D9 D8 D1 D0
13
0 0
16
td1 td2 th1
tconv
1/throughput
tq
td3
tw1
b
tsu1
a
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9.3 Feature Description
9.3.1 ADS7887 Operation
The cycle begins with the falling edge of CS. This point is indicated as ain Figure 32. With the falling edge of
CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the
conversion is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format
and padded by 2 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded
with two lagging zeros as shown in Figure 32. On the 16th falling edge of SCLK, SDO goes to the 3-state
condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the
first rising edge of SCLK after the 13th falling edge. This point is indicated by bin Figure 32.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by
pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is
necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase
and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any
time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.
Figure 32. ADS7887 Interface Timing Diagram
9.3.2 ADS7888 Operation
The cycle begins with the falling edge of CS . This point is indicated as ain Figure 33. With the falling edge of
CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the
conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and
padded by 4 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded
with four lagging zeros as shown in Figure 33. On the 16th falling edge of SCLK, SDO goes to the 3-state
condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the
first rising edge of SCLK after the 11th falling edge. This point is indicated by bin Figure 33.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by
pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is
necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase
and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any
time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.
l TEXAS INSTRUMENTS 7 ~— —H‘ w 4 / i 1 \ /T/JJ X \
1 2 3 4 5 9 10 16
CS
SCLK
SDO
td5 td6
12 4 5612
CS
SCLK
SDO 00 0 D7 D6 D1 D0
11
td1 td2 th1
tconv
1/throughput
tq
th1
tw1
b
tsu1
a
td4
12 4 5612 15
CS
SCLK
SDO 00 0 D7 D6 D1 D0
11
00
16
td1 td2 th1
tconv
1/throughput
tq
td3
tw1
b
tsu1
a
0
18
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Feature Description (continued)
Figure 33. ADS7888 Interface Timing Diagram
As shown in Figure 34, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th
falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at
the end of the quiet time (tq) after SDO goes to 3-state.
Figure 34. ADS7888 Interface Timing Diagram, Data Transfer With 12-Clock Frame
9.4 Device Functional Modes
9.4.1 Power-Down Mode
The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th
SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power-down condition as
shown in Figure 35.
Figure 35. Entering Power-Down Mode
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For
the device to come to the fully powered-up condition it takes 0.8 µs. CS can be pulled high any time after the
10th falling edge as shown in Figure 36. It is not necessary to continue until the 16th clock if the next conversion
starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.
l TEXAS INSTRUMENTS Device starts 4 x ,/ '|_|'I_"|_|'L|'|_|'|_|'L|'L|'|_|'|_|'L|'L|'L|'L|'L|'L|'L|'L SDO 4 Invalid Data Valid Data
Invalid Data Valid Data
SDO
1 5432 6 10987 131211 161514 1 5432 6 10987 131211 161514
SCLK
Device Fully
Powered-Up
Device Starts
Powering Up
CS
19
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Device Functional Modes (continued)
Figure 36. Exiting Power-Down Mode
‘5‘ TEXAS INSTRUMENTS 0PM
AVDD
AVDD
OPA365
VIN
GND
VDD
Device
Input Driver Device: 10-Bit / 8 bit , 1.25 MSPS,
Single-Ended Input
GND
33
+
±
+
680 pF
VSOURCE
±
Copyright © 2016, Texas Instruments Incorporated
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The primary circuits required to maximize the performance of a high-precision, the successive approximation
register (SAR) and analog-to-digital converter (ADC), are the input driver and the reference driver circuits. This
section details some general principles for designing the input driver circuit, references the driver circuit, and
provides some application circuits designed for the ADS7887 and ADS7888.
10.2 Typical Application
Figure 37. Typical Data Acquisition (DAQ) Circuit: Single-Supply DAQ
10.2.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7887
with SNR greater than 61 dB and THD less than –84 dB for input frequencies of 2 kHz to 100 kHz at a
throughput of 1.25 MSPS.
10.2.2 Detailed Design Procedure
To achieve a SINAD of 61 dB, the operational amplifier must have high bandwidth to settle the input signal within
the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise
below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 37,OPA365 is
selected for its high bandwidth (50 MHz) and low noise (4.5 nV√Hz).
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage
internally. The supply to these converters must be driven with a low impedance source and must be decoupled to
the ground. To drive supply pin of ADS7887 ultra low noise fast transient response low dropout voltage regulator
TPS73201 is selected. Alternatively one can drive supply pin with low impedance voltage reference similar to
REF3030.
For a step-by-step design procedure for low power, small form factor digital acquisition (DAQ) circuit based on
similar SAR ADCs refer to TI Precision Design, Three 12-Bit Data Acquisition Reference Designs Optimized for
Low Power and Ultra-Small Form Factor.
l TEXAS INSTRUMENTS A] 42 4)) 4n Imp‘nud- (an) 2 Imam-m. (an) E 42; 422 an .m .m 2 1mm mom mm mm m mm 1 mm 2mm 2mm 4mm 5mm zoom Fragmzy my mery my .m
21
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Typical Application (continued)
10.2.3 Application Curves
SNR: 61.9 dB THD: –86.8 dB SINAD: 61.3 dB
Figure 38. Test Results for the ADS7887 and OPA365 for a
2-kHz Input
SNR: 61.8 dB THD: –85.1 dB SINAD: 61.5 dB
Figure 39. Test Results for the ADS7887 and OPA365 for a
100-kHz Input
l TEXAS INSTRUMENTS 5v |_| TI |_||_| |_|
VDD
VIN
GND
CS
SDO
SCLK
10 nF1µF
1µF
7 V
_
+
R1
C1
R2
5 V
10 W
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 µF
GND
IN
OUT
3 V
1 µF
5 V
REF3030
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 µF
VDD
22
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11 Power Supply Recommendations
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage
internally. The supply to these converters must be driven with a low impedance source and must be decoupled to
the ground Decouple the VDD with 1-µF ceramic decoupling capacitors, as shown in Figure 40. Always set the
VDD supply to be greater than or equal to the maximum input signal to avoid saturation of codes.
Figure 40. Supply and Reference Decoupling Capacitors
Figure 41. Using the REF3030 Reference
Figure 42. Buffering With the OPA735
l TEXAS INSTRUMENTS Analog Digital Pins Pins E VDD 1— cs W T1 "F III ADS7887 2 W E] 5ND ADSTBBS SDO £ CFU E, VIN 3 SCLK W an
23
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12 Layout
12.1 Layout Guidelines
Figure 43 shows a board layout example for the ADS7887 and ADS7888. Some of the key considerations are:
1. Use a ground plane underneath the device and partition the PCB into analog and digital sections.
2. Avoid crossing digital lines with the analog signal path.
3. The power sources to the device must be clean and well-bypassed. Use 1-µF ceramic bypass capacitors in
close proximity to the supply pin (VDD).
4. Avoid placing vias between the VDD and bypass capacitors.
5. Connect ground pin to the ground plane using short, low-impedance path.
6. The fly-wheel RC filters are placed close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance
precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical
properties over voltage, frequency, and temperature changes.
12.2 Layout Example
Figure 43. ADS7887 and ADS7888 Example Layout
l TEXAS INSTRUMENTS
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•50MHz, Low-Distortion, High CMRR, RRI/O, Single-Supply Operational Amplifier (SBOS365)
•Cap-Free NMOS 250-mA Low Dropout Regulator With Reverse Current Protection (SGLS346)
•Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor
(TIDU390)
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
ADS7887 Click here Click here Click here Click here Click here
ADS7888 Click here Click here Click here Click here Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
l TEXAS INSTRUMENTS
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADS7887SDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BAWQ
ADS7887SDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BAWQ
ADS7887SDCKR ACTIVE SC70 DCK 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BNI
ADS7887SDCKT ACTIVE SC70 DCK 6 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BNI
ADS7888SDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BAZQ
ADS7888SDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BAZQ
ADS7888SDCKR ACTIVE SC70 DCK 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BNH
ADS7888SDCKT ACTIVE SC70 DCK 6 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BNH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension deswgned to accommodate the componem wwdlh ED Dimension desxgned to accommodate the componenl \engm K0 Dimenslun deswgned to accommodate the componem thickness , w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D Sprockemules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7887SDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
ADS7887SDBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
ADS7888SDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
ADS7888SDBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Sep-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7887SDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0
ADS7887SDBVT SOT-23 DBV 6 250 213.0 191.0 35.0
ADS7888SDBVR SOT-23 DBV 6 3000 213.0 191.0 35.0
ADS7888SDBVT SOT-23 DBV 6 250 213.0 191.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Sep-2021
Pack Materials-Page 2
3: fig,
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PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/C 06/2021
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
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EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
MECHANICAL DATA DCK (R-PDSO-GS) PLASTIC SMALL-OUTLINE PACKAGE E 18’) 6 4 7 H Fl H ‘fi «40 1233 \ ’i’ To enugemane Seanng Mane Pm 1/ ' ‘ ' ‘ ‘ maexArea Wm H m} j; / ‘ u / Um "4L 1—]; f Scamg Mane \\ \ / 31 409555574/8 U‘ /200/ , m m hmeters AH \mec' mmens‘mrs Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m FuHs an JFDFC M07763 vunuhcn AB NO'FS Umm> INSrRUMEm-s www.1i.com
LAND PATTERN DATA 7PJSOiC6> PLASTC SMALL OU’LME NOTES' maop> Exc'm‘e Boc'd Luyum stem Openings Based or a stencfl hickncss uf 127mm (005mm) * 1* :E /23\\der Musk Cpen‘wg “ 2m Geometry M \meur dimensmns are m m'flhrvete's Th's drawqu is sweat (a chc'vge mm: 'vuhce Custume's shoud p‘uce a new 01 We cvcmt buurd (abr'cahun c'awmg rm :0 uHer the ce'fle' smder musk defined and, ”Jbficuhon \PC77351 is reco'n'nended (Dr uHernme designs Laser cumrg opc'mvcs mm "apczmda wuHs and mo rouncmq corners wm am bcncr aosxc recuscv mstomcrs show can thew Guard assemwy sue for gene design recommencnmons Exomme sxercu deswgw basec on a 50% vo‘umemc bad My paste M‘cr m M4523 var other new rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
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