SN74LVC1GU04 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1GU04
SCES215Y –APRIL 1999–REVISED DECEMBER 2017
SN74LVC1GU04 Single Inverter Gate
1
1 Features
1• Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Unbuffered Output
• Maximum tpd of 3.7 ns at 3.3 V
• Low Power Consumption, 10-μA Maximum ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• AV Receivers
• Blu-ray Players and Home Theaters
• DVD Recorders and Players
• Desktop or Notebook PCs
• Digital Radio or Internet Radio Players
• Digital Video Cameras (DVC)
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Internet Devices
• Network Projector Front-Ends
• Portable Media Players
• Pro Audio Mixers
• Smoke Detectors
• Solid-State Drive (SSD): Enterprise
• High-Definition (HDTV)
• Tablets: Enterprise
• Audio Docks: Portable
• DLP Front Projection Systems
• DVR and DVS
• Digital Picture Frame (DPF)
• Digital Still Cameras
3 Description
This single inverter gate is designed for 1.65-V to
5.5-V VCC operation.
The SN74LVC1GU04 device contains one inverter
with an unbuffered output and performs the Boolean
function Y = A.
NanoFree package technology is a major
breakthrough in device packaging concepts, using the
die as the package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1GU04DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1GU04DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1GU04DRL SOT-5X3 (5) 1.60 mm × 1.20 mm
SN74LVC1GU04DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1GU04DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1GU04YZP DSBGA (5) 1.44 mm × 0.94 mm
SN74LVC1GU04YZV DSBGA (4) 0.91 mm × 0.91 mm
SN74LVC1GU04DPW X2SON (5) 0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
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SN74LVC1GU04
SCES215Y –APRIL 1999–REVISED DECEMBER 2017
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics: TA= –40°C to +85°C ...... 7
6.7 Switching Characteristics: TA= –40°C to +125°C .... 7
6.8 Operating Characteristics.......................................... 7
6.9 Typical Characteristic................................................ 7
7 Parameter Measurement Information .................. 8
8 Detailed Description.............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1 Documentation Support ........................................ 14
12.2 Community Resources.......................................... 14
12.3 Trademarks........................................................... 14
12.4 Electrostatic Discharge Caution............................ 14
12.5 Glossary................................................................ 14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision X (November 2017) to Revision Y Page
• Updated input voltage minimum from 0.5 V to –0.5 V in Absolute Maximum Ratings table.................................................. 5
Changes from Revision W (January 2016) to Revision X Page
• Changed values in the Thermal Information table to align with JEDEC standards................................................................ 6
• Updated Feature Description to include more detailed information about specific device features. ..................................... 9
• Changed Typical Application to oscillator circuit. ................................................................................................................. 11
• Added DPW layout example................................................................................................................................................. 13
Changes from Revision V (November 2013) to Revision W Page
• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics,Feature Description section, Device Functional Modes,Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision U (June 2011) to Revision V Page
• Updated document to new TI data sheet format.................................................................................................................... 1
• Updated operating free-air temperature range in Recommended Operating Conditions table.............................................. 5
l TEXAS INSTRUMENTS [C I] c [E j: c [E [E G [E 3] G [E I] c E j c G E G E ]
Y
VCC
A
NC
GND
2
A
VCC
5
1
N.C.
34
GNDGND Y
A
GND Y
VCC
A1 A2
B1 B2
34
GND
2
A
Y
5
1
N.C. VCC
3
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
DRL Package
5-Pin SOT
Top View
DCK Package
5-Pin SC70
Top View
YZV Package
4-Pin DSBGA
Top View
DPW Package
5-Pin SON
Top View
(1) NC – No internal connection
(2) See Mechanical, Packaging, and Orderable Information for dimensions
Pin Functions(1)(2)
PIN
I/O DESCRIPTION
NAME DBV, DRL,
DCK, DPW YZV
A 2 A1 I Input
GND 3 B1 — Ground
NC 1 – — Not connected
VCC 5 A2 — Positive Supply
Y 4 B2 O Output
l TEXAS INSTRUMENTS DD CID EDI EDD
A
GND
DNU VCC
Y
C2C1
B1 B2
A1 A2
A N.C.
N.C. 6
5
4
2
3
GND Y
VCC
1
N.C.
GND
A
VCC
Y
N.C.
6
5
4
2
3
1
4
SN74LVC1GU04
SCES215Y –APRIL 1999–REVISED DECEMBER 2017
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DSF Package
6-Pin SON
Top View DRY Package
6-Pin SON
Top View
YZP Package
6-Pin DSBGA
Top View
DNU – Do not use
(1) NC – No internal connection
(2) See Mechanical, Packaging, and Orderable Information for dimensions
Pin Functions(1)(2)
PIN I/O DESCRIPTION
NAME DSF, DRY YZP
A 2 B1 I Input
GND 3 C1 — Ground
NC 1, 5 A1, B2 — Not connected
VCC 6 A2 — Positive Supply
Y 4 C2 O Output
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in Recommended Operating Conditions .
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage(2) –0.5 6.5 V
VOVoltage applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJMaximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. For more information, see the
Implications of Slow or Floating CMOS Inputs application report.
6.3 Recommended Operating Conditions
See (1).
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VIH High-level input voltage IO= –100 μA 0.75 × VCC V
VIL Low-level input voltage IO= 100 μA 0.25 × VCC V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
IOH High-level output current
VCC = 1.65 V –4
mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
IOL Low-level output current
VCC = 1.65 V 4
mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
TAOperating free-air temperature –40 125 °C
l TEXAS INSTRUMENTS
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74LVC1GU04
UNIT
DBV
(SOT-23) DCK
(SC70) DRL
(SOT-5X3) DRY
(SON) DSF
(SON) DPW
(X2SON) YZV
(DSBGA) YZP
(DSBGA)
5 PINS 5 PINS 5 PINS 5 PINS 5 PINS 5 PINS 4 PINS 5 PINS
RθJA Junction-to-ambient
thermal resistance 231.5 276.1 296.2 369.6 410.3 511 168.2 144.4 °C/W
RθJC(top)
Junction-to-case
(top) thermal
resistance 139.4 178.9 137.3 257.6 208.4 241.9 2.1 1.3 °C/W
RθJB Junction-to-board
thermal resistance 71.1 70.9 145.3 230.8 262.6 374.2 55.9 39.9 °C/W
ψJT
Junction-to-top
characterization
parameter 45.2 47 14.7 77.2 36 45 1.1 0.5 °C/W
ψJB
Junction-to-board
characterization
parameter 70.7 69.3 145.9 231 262.3 373.3 56.3 39.7 °C/W
RθJC(bot)
Junction-to-case
(bottom) thermal
resistance N/A N/A N/A N/A N/A 168.0 N/A N/A °C/W
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
6.5 Electrical Characteristics
over recommended operating free-air temperature range, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH High-level output
voltage
VIL = 0 V, IOH = –100 µA, VCC = 1.65 V to 5.5 V VCC – 0.1
V
VIL = 0 V, IOH = –4 mA, VCC = 1.65 V 1.2
VIL = 0 V, IOH = –8 mA, VCC = 2.3 V 1.9
VIL = 0 V, IOH = –16 mA, VCC = 3 V 2.4
VIL = 0 V, IOH = –24 mA, VCC = 3 V 2.3
VIL = 0 V, IOH = –32 mA, VCC = 4.5 V 3.8
VOL Low-level output
voltage
VIH = VCC, IOL = 100 µA, VCC = 1.65 V to 5.5 V 0.1
V
VIH = VCC, IOL = 4 mA, VCC = 1.65 V 0.45
VIH = VCC, IOL = 8 mA, VCC = 2.3 V 0.3
VIH = VCC, IOL = 16 mA, VCC = 3 V 0.4
VIH = VCC, IOL = 24 mA, VCC = 3 V 0.55
VIH = VCC, IOL = 32 mA, VCC = 4.5 V 0.55
IIInput leakage current A Input:
VI= 5.5 V or GND, VCC = 0 V to 5.5 V ±5 μA
ICC Supply current VI= 5.5 V or GND, IO= 0, VCC = 1.65 V to 5.5 V 10 μA
CIInput capacitance VI= VCC or GND, VCC = 3.3 V, TA= –40°C to 85°C 7 pF
l TEXAS INSTRUMENTS
12345
VCC (V)
tpd(ns)
1
2
3
4
5
0
6
tpd(MIN)
tpd(MAX)
7
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6.6 Switching Characteristics: TA= –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 2)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tpd Propagation delay A-to-Y
VCC = 1.8 V ± 0.15 V 1.3 5
ns
VCC = 2.5 V ± 0.2 V 1 4
VCC = 3.3 V ± 0.3 V 1.1 3.7
VCC = 5 V ± 0.5 V 1 3
6.7 Switching Characteristics: TA= –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 2)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tpd Propagation delay A-to-Y
VCC = 1.8 V ± 0.15 V 1.3 5.5
ns
VCC = 2.5 V ± 0.2 V 1 4.5
VCC = 3.3 V ± 0.3 V 1.1 4.2
VCC = 5 V ± 0.5 V 1 3.5
6.8 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance f = 10 MHz
VCC = 1.8 V 9
pF
VCC = 2.5 V 11
VCC = 3.3 V 13
VCC = 5 V 27
6.9 Typical Characteristic
Figure 1. tpd vs VCC
‘5‘ TEXAS INSTRUMENTS A 3 I fl 3+3 3.133 3.1 W33 *3 31 3m
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
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GND
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DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
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VCC/2
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£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
8
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7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
GND
Logic
Input Output
VCC
Device
-IIK -IOK
A Y
2 4
9
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8 Detailed Description
8.1 Overview
The SN74LVC1GU04 device contains one inverter with an unbuffered output with a maximum sink current of
32 mA.
8.2 Functional Block Diagram
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high-drive capability of this device
creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be
followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst-case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals that are applied to the inputs need to have fast edge rates, as shown by Δt/Δv in the Recommended
Operating Conditions, to avoid excessive current consumption and oscillations. If a slow or noisy input signal is
required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard
CMOS input.
8.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in Figure 4.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output
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Feature Description (continued)
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Unbuffered Logic
A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function,
and the output inverter. Some devices have multiple stages at the input or output for various reasons. An
unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the
required logic function which is directly driven from the inputs and directly drives the outputs.
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use
an unbuffered inverter in an oscillator circuit, see Use of the CMOS Unbuffered Inverter in Oscillator Circuits.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1GU04.
Table 1. Function Table
INPUT
AOUTPUT
Y
H L
L H
l TEXAS INSTRUMENTS RF ~2.2 Mn SN74LVC1G 04 SN74LVC1G14 {>01 C as T w ~1 k0 f
U
Copyright © 2017, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. An example application circuit is
shown in Figure 5. To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use
of the CMOS Unbuffered Inverter in Oscillator Circuits application report.
9.2 Typical Application
Figure 5. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use of the CMOS
Unbuffered Inverter in Oscillator Circuits application report.
1. Recommended Input Conditions
– Specified high and low levels. See (VIH and VIL)inRecommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as (VImax) in Recommended Operating
Conditions at any valid VCC.
2. Absolute Maximum Output Conditions
– Load currents must not exceed (IOmax) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs must not be pulled above the voltage rated in the Absolute Maximum Ratings.
l TEXAS INSTRUMENTS IGUU
Frequency - MHz
Icc - µA
0 20 40 60 80
0
200
400
600
800
1000
1200
1400
1600
D001
Icc 1.8V
Icc 2.5V
Icc 3.3V
Icc 5V
12
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Typical Application (continued)
9.2.3 Application Curve
Figure 6. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1-
µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin
as possible for best results.
{L} TEXAS INSTRUMENTS /1W min. SK
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK,
TYP
8 mil
4 mil
8 mil
0402
0.1 …F
Bypass
Capacitor
8 mil
WORST BETTER BEST
13
SN74LVC1GU04
www.ti.com
SCES215Y –APRIL 1999–REVISED DECEMBER 2017
Product Folder Links: SN74LVC1GU04
Submit Documentation FeedbackCopyright © 1999–2017, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 7 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
An example layout is given in Figure 8 for the DPW (X2SON-5) package. This example layout includes a 0402
(metric) capacitor and uses the measurements found in the example board layout appended to this end of this
datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or it can be left out of the layout
11.2 Layout Example
Figure 7. Trace Example
Figure 8. Example Layout With DPW (X2SON-5) Package
l TEXAS INSTRUMENTS
14
SN74LVC1GU04
SCES215Y –APRIL 1999–REVISED DECEMBER 2017
www.ti.com
Product Folder Links: SN74LVC1GU04
Submit Documentation Feedback Copyright © 1999–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74LVC1GU04DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F Samples
74LVC1GU04DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F Samples
74LVC1GU04DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CU4F Samples
74LVC1GU04DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CD5
CDS Samples
74LVC1GU04DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CD5
CDS Samples
74LVC1GU04DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CD5
CDS Samples
74LVC1GU04DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 CDR Samples
SN74LVC1GU04DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CU45, CU4F, CU4J,
CU4R, CU4T)
(CU4H, CU4P, CU4S)
Samples
SN74LVC1GU04DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CU45, CU4F, CU4J,
CU4R)
(CU4H, CU4P, CU4S)
Samples
SN74LVC1GU04DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CD5, CDF, CDJ, CD
K, CDR, CDT)
(CDH, CDP, CDS)
Samples
SN74LVC1GU04DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CD5, CDF, CDJ, CD
K, CDR, CDT)
(CDH, CDP, CDS)
Samples
SN74LVC1GU04DPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CM Samples
SN74LVC1GU04DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 CDR Samples
SN74LVC1GU04DRY2 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD Samples
SN74LVC1GU04DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD Samples
Addendum-Page 1
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1GU04DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CD Samples
SN74LVC1GU04YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CDN Samples
SN74LVC1GU04YZVR ACTIVE DSBGA YZV 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CD
(7, N) Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Addendum-Page 3
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS Reel Dlameter Cavtty AD Dimension destgned to accommodate the component wmth Eu Dimension destgned to accommodate the componenl Iength K0 Dtmenston destgned to accommodate the component thickness 7 w Ovevau with at the earner tape i Pt PIlCh between successtve cavtty cemers i T ReelWidIh(W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O O C) O O O ispmckeIHuIes —> User Dtrecllnn OI Feed \I/ Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74LVC1GU04DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
74LVC1GU04DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
74LVC1GU04DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
74LVC1GU04DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1GU04DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1GU04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1GU04DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1GU04DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1GU04DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1GU04DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1GU04DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3
SN74LVC1GU04DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3
SN74LVC1GU04DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1GU04DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1GU04YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
SN74LVC1GU04YZVR DSBGA YZV 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74LVC1GU04DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
74LVC1GU04DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
74LVC1GU04DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
74LVC1GU04DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1GU04DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 2
I TEXAS INSTRUMENTS
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1GU04DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1GU04DPWR X2SON DPW 5 3000 205.0 200.0 33.0
SN74LVC1GU04DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1GU04DRY2 SON DRY 6 5000 202.0 201.0 28.0
SN74LVC1GU04DRY2 SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1GU04DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1GU04DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1GU04YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
SN74LVC1GU04YZVR DSBGA YZV 4 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 3
GENERIC PACKAGE VIEW DPW 5 XZSON - 0.4 mm max heigm PLASTIC SMALL OUTLINE , N0 LEAD Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 42112133/D I TEXAS INSTRI IMFNTS
www.ti.com
PACKAGE OUTLINE
C
4X 0.27
0.17
3X 0.288
0.188
0.4 MAX
0.05
0.00
2X
0.48
0.239
0.139
0.25 0.1
B0.85
0.75 A
0.85
0.75
(0.1)
4X (0.05) (0.324)
2X (0.26)
X2SON - 0.4 mm max heightDPW0005A
PLASTIC SMALL OUTLINE - NO LEAD
4223102/D 03/2022
PIN 1 INDEX AREA
SEATING PLANE
NOTE 3
1
2
3
4
0.1 C A B
0.05 C
5
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
NOTE 3
SCALE 12.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
TYP
(0.21) TYP
EXPOSED METAL
CLEARANCE
(0.48)
(0.78)
4X (0.42)
4X (0.22)
( 0.25)
4X (0.26)
4X (0.06)
( 0.1)
VIA
(R0.05) TYP
X2SON - 0.4 mm max heightDPW0005A
PLASTIC SMALL OUTLINE - NO LEAD
4223102/D 03/2022
SYMM
1
2
3
4
SYMM
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
5
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
(0.48)
(0.78)
4X (0.42)
4X (0.22)
4X (0.26)
4X (0.06)
( 0.24)
(0.21)
TYP
(R0.05) TYP
X2SON - 0.4 mm max heightDPW0005A
PLASTIC SMALL OUTLINE - NO LEAD
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
SYMM
1
2
3
4
SYMM
EDGE
SOLDER MASK
5
‘ ‘ E g ***** $1 Li, ‘0 Q) / n ‘ --II- (£4
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
5X 0.25
0.21
0.5
TYP
B E A
D
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
SCALE 8.000
D: Max =
E: Max =
1.44 mm, Min =
0.94 mm, Min =
1.38 mm
0.88 mm
www.ti.com
EXAMPLE BOARD LAYOUT
5X ( 0.23)
(0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
5X ( 0.25) (R0.05) TYP
METAL
TYP
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
MECHANICAL DATA YZV (SiXBGA7N4) DiE7$|ZE BALL GRID ARRAY E i i am. Seating Piane mamas/c 07/13 NOTES: A. Aii \ineav dimensions me in miiiimeieis. Dimensinning and ioiemnsing pH ASME mm—mm. a. This awning is subjecl to change niinnni nofice. c. NunoFree'“ package configuration. NannFIee is a trademalk 0' Texas inslmmenls. {I TEXAS INSTRUMENTS www.|i.com
D: Max =
E: Max =
0.918 mm, Min =
0.918 mm, Min =
0.858 mm
0.858 mm
www.ti.com
PACKAGE OUTLINE
C
1.7
1.5
2X 0.5
2X 1
5X 0.3
0.1
0.6 MAX
5X 0.18
0.08
5X 0.4
0.2
0.05
0.00 TYP
5X 0.27
0.15
B1.3
1.1
A
1.7
1.5
NOTE 3
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
15
PIN 1
ID AREA
34
SEATING PLANE
0.05 C
SCALE 8.000
0.1 C A B
0.05
SYMM
SYMM
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
AROUND 0.05 MIN
AROUND
5X (0.67)
5X (0.3)
(1.48)
2X (0.5)
(R0.05) TYP
(1)
4220753/B 12/2020
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
SYMM
1
34
5
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
vi“‘+\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(1.48)
2X (0.5)
5X (0.67)
5X (0.3)
(R0.05) TYP
(1)
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
SYMM
SYMM
1
34
5
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
www.ti.com
PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
5X 0.35
0.25
2X
1
0.6 MAX
0.05
0.00
3X 0.6
0.4
0.3
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
www.ti.com
PACKAGE OUTLINE
C
6X 0.22
0.12
6X 0.45
0.35
2X
0.7 4X
0.35
0.4 MAX
0.05
0.00
B1.05
0.95 A
1.05
0.95
(0.11) TYP
(0.1)
PIN 1 ID
4220597/B 06/2022
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
34
6
0.07 C B A
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
SCALE 10.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
6X (0.6)
6X (0.17)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/B 06/2022
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
SYMM
SYMM
1
34
6
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
““‘+“‘w‘
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.6)
6X (0.15)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/B 06/2022
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.09 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
SYMM
SYMM
1
34
6
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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