DAC53608, DAC43608 Datasheet by Texas Instruments

V'.‘ 1!. B I TEXAS INSTRUMENTS ‘V
VOUTA
DAC
Active
Registers
DAC
Buffer
Registers BUF
Channel A
Power Down LogicResistive Network
I2CTM Interface
Power On Reset
DACx3608
SCL
SDA
A0
DAC
VDD VREFIN
AGND
LDAC
Channel H VOUTH
CLR
THLD-HI +
+
THLD-LO
DACx3608 VOUT
VIO
RPULL-UP
R1
R2
VIN
RB
RA
VDAC
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC53608
,
DAC43608
SLASEQ4A –OCTOBER 2018–REVISED DECEMBER 2018
DACx3608 Octal, 10-Bit or 8-Bit, I
2
C
TM
Interface, Buffered Voltage Output DACs
in Tiny 3 × 3 WQFN Package
1
1 Features
1• ±1-LSB INL and DNL
• Wide Operating Range
– Power Supply: 1.8 V to 5.5 V
– Temperature Range: –40˚C to 125˚C
• I2CTM Serial Interface
– Standard, Fast, and Fast+ Mode
– 2.4-V, VIH with VDD = 5.5 V
• LDAC Pin For Simultaneous Output Update
• Very Low Power: 0.1 mA/Channel at 1.8 V
• Low Power Startup Mode: Outputs powered down
to 10K State
• Tiny Package
– 16-Pin WQFN (3 mm × 3 mm)
2 Applications
• Programmable Power Supplies
• Programmable Window Comparator
• VCOM Biasing in Display Panel
• Laser Driver In Multifunction Printers
• Auto Focus Digital Still Cameras Lens
• ATM Machines, Currency Counters, Barcode
Readers
• IP Network Cameras, Projectors
3 Description
The DAC53608 and DAC43608 (DACx3608) are low-
power, eight-channel, voltage-output, 10-bit or 8-bit
digital-to-analog converters (DACs) respectively. The
DACx3608 are specified monotonic by design across
a wide power supply range from 1.8 V to 5.5 V. Using
an external reference, the DACx3608 provides a full
scale output voltage range of 1.8 V to 5.5 V while
consuming 0.1-mA quiescent current per channel.
The DACx3608 also includes per channel, user
programmable, power down registers. These
registers facilitate the DAC output buffers to start in a
power down to 10K state and remain in this state until
a power up command is issued to these output
buffers.
Low quiescent current, wide power supply range, and
per channel power down option makes DACx3608
ideal for low power, battery operated systems.
The devices communicate through the I2CTM
interface. These devices support I2CTM standard
mode (100 kbps), fast mode (400 kbps), and fast+
mode (1 Mbps). These devices also have a load DAC
(LDAC) pin that allows simultaneous DAC updates.
The DACx3608 are available in small 3-mm × 3-mm,
16-pin WQFN package. The devices are fully
specified over the extended industrial temperature
range of –40°C to +125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DAC53608 WQFN (16) 3.00 mm × 3.00 mm
DAC43608 WQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, refer to the orderable addendum
at the end of the data sheet.
Simplified Block Diagram Programmable Window Comparator
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configurations and Functions....................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements: I2CTM Standard Mode ........... 7
7.7 Timing Requirements: I2CTM Fast Mode................... 7
7.8 Timing Requirements: I2CTM Fast+ Mode................. 8
7.9 Timing Requirements: Logic ..................................... 8
7.10 Typical Characteristics: 1.8 V ............................... 10
7.11 Typical Characteristics: 5.5 V ............................... 12
7.12 Typical Characteristics.......................................... 17
7.13 Typical Characteristics.......................................... 18
8 Detailed Description............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 21
8.5 Programming........................................................... 22
8.6 Register Map........................................................... 28
9 Application and Implementation ........................ 31
9.1 Application Information............................................ 31
9.2 Typical Applications ................................................ 31
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1 Documentation Support ........................................ 36
12.2 Related Links ........................................................ 36
12.3 Receiving Notification of Documentation Updates 36
12.4 Community Resources.......................................... 36
12.5 Trademarks........................................................... 36
12.6 Electrostatic Discharge Caution............................ 36
12.7 Glossary................................................................ 36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (October 2018) to Revision A Page
• Changed from Advance Information to Production Data ....................................................................................................... 1
l TEXAS INSTRUMENTS IN
16 CLR5SDA
1
VOUT A 12 VOUT H
15 VREF IN
6SCL
2
VOUT B 11 VOUT G
14 AGND
7A0
3
VOUT C 10 VOUT F
13 VDD
8LDAC
4
VOUT D 9 VOUT E
Not to scale
3
DAC53608
,
DAC43608
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5 Device Comparison Table
DEVICE RESOLUTION
DAC53608 10-Bit
DAC43608 8-Bit
6 Pin Configurations and Functions
RTE Package
16-Pin WQFN
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A0 7 I Four-state address input
AGND 14 GND Ground reference point for all circuitry on the device.
CLR 16 I Asynchronous clear pin (active low)
LDAC 8 I Load DAC pin for simultaneous output update (active low)
SCL 6 I Serial interface clock
SDA 5 I/O Data is clocked into or out of the input register. This pin is a bidirectional, open
drain data line that must be connected to the supply voltage with an external
pull-up resistor.
VDD 13 PWR Analog supply voltage (1.8 V to 5.5 V).
VOUTA 1 O Analog output voltage from DAC A
VOUTB 2 O Analog output voltage from DAC B
VOUTC 3 O Analog output voltage from DAC C
VOUTD 4 O Analog output voltage from DAC D
VOUTE 9 O Analog output voltage from DAC E
VOUTF 10 O Analog output voltage from DAC F
VOUTG 11 O Analog output voltage from DAC G
VOUTH 12 O Analog output voltage from DAC H
VREFIN 15 I/O Reference input to the device
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DAC43608
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(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage
VDD to AGND –0.3 6
VVREFIN to AGND –0.3 VDD + 0.3
Digital input(s) to AGND –0.3 VDD + 0.3
Output voltage VOUT to AGND –0.3 VDD + 0.3 V
Input Current Current into any pin –10 10 mA
Temperature Junction temperature,TJ–40 150 °C
Storage temperature, Tstg –65 150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.
7.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, allpins(1) ±1000
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2) ±500
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD to AGND Positive supply voltage to ground 1.8 5.5 V
VREFIN to AGND Reference input supply voltage to ground 1.8 VDD V
VIH Digital input high voltage, 1.8 ≤VDD ≤2.7 VDD – 0.3 V
VIH Digital input high voltage, 2.7 < VDD ≤5.5 2.4 V
VIL Digital input low voltage 0.5 V
TAAmbient temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1)
DACx3608
UNITRTE (WQFN)
16 PIN
RθJA Junction-to-ambient thermal resistance 49 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50 °C/W
RθJB Junction-to-board thermal resistance 24.1 °C/W
ΨJT Junction-to-top characterization parameter 1.1 °C/W
YJB Junction-to-board characterization parameter 24.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.7 °C/W
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(1) End point fit between codes Code 4 to Code 1016 for 10 bit, Code 1 to Code 251 for 8 bit
(2) Not production tested
7.5 Electrical Characteristics
all minimum/maximum specifications at TA= –40°C to +125°C and all typical specification at TA= 25°C, 1.8 V ≤VDD ≤5.5 V,
VREFIN = 2.5 V for VDD ≥2.7 V, VREFIN = 1.8 V for VDD ≤2.7 V, RL= 5 kΩto AGND, CL= 200 pF to AGND, and digital inputs at
VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53608 10 Bits
DAC43608 8
INL Relative accuracy(1)
DAC43608, 2.7 V ≤VDD ≤5.5 V –1 1
LSB
DAC43608, 1.8 V ≤VDD ≤2.7 V –1 1
DAC53608, 2.7 V ≤VDD ≤5.5 V –1 1
DAC53608, 1.8 V ≤VDD ≤2.7 V –1 1
DNL Differential nonlinearity(1)
DAC43608, 2.7 V ≤VDD ≤5.5 V –1 1
LSB
DAC43608, 1.8 V ≤VDD ≤2.7 V –1 1
DAC53608, 2.7 V ≤VDD ≤5.5 V –1 1
DAC53608, 1.8 V ≤VDD ≤2.7 V –1 1
Zero code error 2.7 V ≤VDD ≤5.5 V, code 0d into DAC 6 12 mV
1.8 V ≤VDD ≤2.7 V, code 0d into DAC 6 12
Zero code error temperature coefficient ±5 µV/°C
Offset error(1) 2.7 V ≤VDD ≤5.5 V –0.5 0.25 0.5 %FSR
1.8 V ≤VDD ≤2.7 V –0.5 0.25 0.5
Offset error temperature coefficient(1) ±0.0003 %FSR/°
C
Gain error(1) 2.7 V ≤VDD ≤5.5 V –0.5 0.25 0.5 %FSR
1.8 V ≤VDD ≤2.7 V –0.5 0.25 0.5
Gain error temperature coefficient(1) ±0.0004 %FSR/°
C
Full scale error
2.7 V ≤VDD ≤5.5 V, code 1023d into
DAC, no headroom –0.5 0.25 0.5
%FSR
1.8 V ≤VDD ≤2.7 V, code 1023d into
DAC, no headroom –1 0.5 1
Full scale error temperature coefficient ±0.0004 %FSR/°
C
OUTPUT CHARACTERISTICS
VOUTX Output voltage 0 5.5 V
CLCapacitive load(2) RL= Infinite 1 nF
RL= 5 kΩ2
Load regulation DAC at midscale, -10 mA ≤IOUT ≤10
mA, VDD = 5.5 V 0.1 mV/mA
Short circuit current
VDD = 1.8 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
10
mA
VDD = 2.7 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
25
VDD = 5.5 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
50
Output voltage headroom to VDD (DAC output unloaded) 0.05 V
Output voltage headroom(2)
to VDD (load current = 10 mA@VDD = 5.5
V, load current = 3 mA@VDD = 2.7 V,
load current = 1 mA@VDD = 1.8 V), DAC
code = full Scale
10 %FSR
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Electrical Characteristics (continued)
all minimum/maximum specifications at TA= –40°C to +125°C and all typical specification at TA= 25°C, 1.8 V ≤VDD ≤5.5 V,
VREFIN = 2.5 V for VDD ≥2.7 V, VREFIN = 1.8 V for VDD ≤2.7 V, RL= 5 kΩto AGND, CL= 200 pF to AGND, and digital inputs at
VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ZODC output impedance
DAC at midscale 0.25
ΩDAC at code 4d 0.25
DAC at code 1016 0.26
DC-
PSRR Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10% 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale
settling to 10%FSR, RL= 5 kΩ, CL= 200
pF, VDD = 5.5 V 10 µs
SR Slew rate RL= 5 kΩ, CL= 200 pF, VDD = 5.5 V 0.6 V/µs
Power on glitch magnitude RL= 5 kΩ, CL= 200 pF 110 mV
VnOutput noise 0.1 Hz to 10 Hz, DAC at midscale, VDD =
5.5 V 40 µVpp
VnOutput noise 0.1 Hz to 100 kHz bandwidth, DAC at
midscale, VDD = 5.5 V 0.05 mVrms
VnOutput noise density
measured at 1 kHz, DAC at midscale,
VDD = 5.5 V 0.2
µV/√Hz
measured at 10 kHz, DAC at midscale,
VDD = 5.5 V 0.2
AC-
PSRR Power supply rejection ratio (AC) 200 mV 50/60 Hz sine wave
superimposed on power supply voltage,
DAC at midscale –71 dB
Channel-to-channel AC crosstalk Full-scale swing on adjacent channel 1.5 nV-s
Channel-to-channel DC crosstalk Full-scale swing on all channel,
measured channel at zero or full scale 0.05 LSB
Code change glitch impulse ±1 LSB change around mid code
(including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code
(including feedthrough) 25 mV
VOLTAGE REFERENCE INPUT
Reference input impedance All channel powered on 12.5 kΩ
Reference input capacitance 50 pF
DIGITAL INPUTS
Digital feedthrough At SCLK = 1 MHz, DAC output static at
mid scale 20 nV-s
Pin capacitance Per pin 10 pF
POWER REQUIREMENTS
IVDD Current flowing into VDD Normal mode, all DACs at full scale. SPI
static. 3 5 mA
IVDD Current flowing into VDD All DACs power-down 50 µA
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7.6 Timing Requirements: I2CTM Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, 1.8 V ≤VREFIN ≤VDD, –40°C ≤TA≤+125°C, Vpull up
= VDD for 1.8 V ≤VDD ≤2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤VDD ≤5.5 V
MIN NOM MAX UNIT
fSCLK SCLK frequency 0.1 MHz
tBUF Bus free time between stop and start conditions 4.7 µs
tHDSTA Hold time after repeated start 4 µs
tSUSTA Repeated start setup time 4.7 µs
tSUSTO Stop condition setup time 4 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 250 ns
tLOW SCL clock low period 4700 ns
tHIGH SCL clock high period 4700 ns
tFClock and data fall time 300 ns
tRClock and data rise time 1000 ns
7.7 Timing Requirements: I2CTM Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, 1.8 V ≤VREFIN ≤VDD, –40°C ≤TA≤+125°C, Vpull up
= VDD for 1.8 V ≤VDD ≤2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤VDD ≤5.5 V
MIN NOM MAX UNIT
fSCLK SCLK frequency 0.4 MHz
tBUF Bus free time between stop and start conditions 1.3 µs
tHDSTA Hold time after repeated start 0.6 µs
tSUSTA Repeated start setup time 0.6 µs
tSUSTO Stop condition setup time 0.6 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 100 ns
tLOW SCL clock low period 1300 ns
tHIGH SCL clock high period 600 ns
tFClock and data fall time 300 ns
tRClock and data rise time 300 ns
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7.8 Timing Requirements: I2CTM Fast+ Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, 1.8 V ≤VREFIN ≤VDD, –40°C ≤TA≤+125°C, Vpull up
= VDD for 1.8 V ≤VDD ≤2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤VDD ≤5.5 V
MIN NOM MAX UNIT
fSCLK SCL frequency 1 MHz
tBUF Bus free time between stop and start conditions 0.5 µs
tHDSTA Hold time after repeated start 0.26 µs
tSUSTA Repeated start setup time 0.26 µs
tSUSTO Stop condition setup time 0.26 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 50 ns
tLOW SCL clock low period 0.5 µs
tHIGH SCL clock high period 0.26 µs
tFClock and data fall time 120 ns
tRClock and data rise time 120 ns
7.9 Timing Requirements: Logic
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, 1.8 V ≤VREFIN ≤VDD, –40°C ≤TA≤+125°C, Vpull up
= VDD for 1.8 V ≤VDD ≤2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤VDD ≤5.5 V
MIN NOM MAX UNIT
tLDACAH SCL fall edge to LDAC rise edge, 1.7 V ≤VDD ≤2.7 V 20 ns
tLDACAH SCL fall edge to LDAC rise edge, 2.7 V < VDD ≤5.5 V 20 ns
tLDACAL LDAC fall edge to SCL fall edge, 1.7 V ≤VDD ≤5.5 V 10 clock cycle
tLDACSH SCL fall edge to LDAC rise edge, 1.7 V ≤VDD ≤2.7 V 80 ns
tLDACSH SCL fall edge to LDAC rise edge, 2.7 V < VDD ≤5.5 V 50 ns
tLDACSL SCL fall edge to LDAC fall edge, 1.7 V ≤VDD ≤2.7 V 20 ns
tLDACSL SCL fall edge to LDAC fall edge, 2.7 V < VDD ≤5.5 V 20 ns
tLDACW LDAC low time, 1.7 V ≤VDD < 2.7 V 30 ns
tLDACW LDAC low time, 2.7 V ≤VDD ≤5.5 V 60 ns
tCLRW CLR low time, 1.7 V ≤VDD < 2.7 V 30 ns
tCLRW CLR low time, 2.7 V ≤VDD ≤5.5 V 60 ns
tCLRW
CLR
tLDACAL tLDACAH
tLDACSH
tLDACSL tLDACW
LDAC1
LDAC2
SCL
SDA
PS
tBUF
tHDSTA
tLOW tR
tHDDAT
tHIGH
tF
tSUDAT
tSUSTA
tHDSTA
S
tSUSTO
P
Low byte ACK cycle
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Figure 1. Serial Interface Timing Diagram
l TEXAS INSTRUMENTS
Temperature (oC)
Total Unadjusted Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D006
TUE Max
TUE Min
Code
Total Unadjusted Error (%FSR)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D003
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
INL Error Max-Min (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D004
INL Max
INL Min
Code
INL (LSB)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D001
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Code
DNL (LSB)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D002
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
10
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7.10 Typical Characteristics: 1.8 V
at TA= 25°C, VDD = 1.8 V, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
Figure 2. Integral Linearity Error vs Digital Input Code Figure 3. Differential Linearity Error vs Digital Input Code
Figure 4. Total Unadjusted Error vs Digital Input Code Figure 5. Integral Linearity Error vs Temperature
Figure 6. Differential Linearity Error vs Temperature Figure 7. Total Unadjusted Error vs Temperature
l TEXAS INSTRUMENTS
Temperature (oC)
Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D009
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Full Scale Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D010
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Zero Code Error (mV)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-6
-4
-2
0
2
4
6
D007
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Offset Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D008
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
11
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Typical Characteristics: 1.8 V (continued)
at TA= 25°C, VDD = 1.8 V, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
Figure 8. Zero Code Error vs Temperature Figure 9. Offset Error vs Temperature
Figure 10. Gain Error vs Temperature Figure 11. Full Scale Error vs Temperature
l TEXAS INSTRUMENTS
Temperature (oC)
DNL Error Max-Min (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D015
DNL Max
DNL Min
Temperature (oC)
Total Unadjusted Error Max-Min (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D016
TUE Max
TUE Min
Code
Total Unadjusted Error (%FSR)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D013
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
INL Error Max-Min (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D014
INL Max
INL Min
Code
INL (LSB)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D011
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Code
DNL (LSB)
0 128 256 384 512 640 768 896 1024
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D012
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
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7.11 Typical Characteristics: 5.5 V
at TA= 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
Figure 12. Integral Linearity Error vs Digital Input Code Figure 13. Differential Linearity Error vs Digital Input Code
Figure 14. Total Unadjusted Error vs Digital Input Code Figure 15. Integral Linearity Error vs Temperature
Figure 16. Differential Linearity Error vs Temperature Figure 17. Total Unadjusted Error vs Temperature
l TEXAS INSTRUMENTS
VREFIN (V)
Full Scale Error (%FSR)
1.8 2.725 3.65 4.575 5.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D034
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
D019
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Full Scale Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
D020
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Zero Code Error (mV)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
2
4
6
8
10
12
D017
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature (oC)
Offset Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
D018
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
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Typical Characteristics: 5.5 V (continued)
at TA= 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
Figure 18. Zero Code Error vs Temperature Figure 19. Offset Error vs Temperature
Figure 20. Gain Error vs Temperature Figure 21. Full Scale Error vs Temperature
Figure 22. Gain Error vs Reference Voltage Figure 23. Full Scale Error vs Reference Voltage
l TEXAS INSTRUMENTS
Temperature (oC)
IDD (PA)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
35
40
45
50
D039
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
Load Current (mA)
DAC Output (V)
-20 -16 -12 -8 -4 0 4 8 12 16 20
-2
-1
0
1
2
3
4
D041
Code 0x3FF
Code 0
Temperature (oC)
IDD (mA)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
D037
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
VDD (V)
IDD (mA)
1.8 2.725 3.65 4.575 5.5
0
0.5
1
1.5
2
2.5
3
D038
Code
IDD (mA)
0 128 256 384 512 640 768 896 1024
0
0.5
1
1.5
2
2.5
3
D035
Code
IDD (mA)
0 128 256 384 512 640 768 896 1024
0
0.5
1
1.5
2
2.5
3
D036
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Typical Characteristics: 5.5 V (continued)
at TA= 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
at VDD = 1.8 V and reference = 1.8 V
Figure 24. Supply Current vs Digital Input Code
at VDD = 5.5 V and reference = 5.5 V
Figure 25. Supply Current vs Digital Input Code
DAC code at mid-scale
Figure 26. Supply Current vs Temperature
DAC code at mid-scale and reference tied to VDD
Figure 27. Supply Current vs Supply Voltage
Figure 28. Power Down Current vs Temperature
at VDD = 1.8 V and reference = 1.8 V
Figure 29. Source and Sink Capability
l TEXAS INSTRUMENTS
Time (50 Ps/div)
DAC Output (mV)
-4
-2
0
2
4
6
8
10
12
14
16
18
D047
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Time (5 Ps/div)
D046
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
Time (1 Ps/div)
D044
VOUT (1 LSB/div)
LDAC (2.5 V/div)
Time (5 Ps/div)
D045
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
Load Current (mA)
DAC Output (V)
-20 -16 -12 -8 -4 0 4 8 12 16 20
0
1
2
3
4
5
6
D042
Code 0x3FF
Code 0
Time (1 Ps/div)
D043
VOUT (1 LSB/div)
LDAC (2.5 V/div)
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Typical Characteristics: 5.5 V (continued)
at TA= 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
at VDD = 5.5 V and reference = 5.5 V
Figure 30. Source and Sink Capability
DAC code transition from mid-scale – 1 to mid-scale, DAC output
loaded with 5 kΩ//200 pF
Figure 31. Glitch Impulse, Rising Edge, 1 LSB Step
DAC code transition from mid-scale to mid-scale – 1 LSB, DAC
output loaded with 5 kΩ//200 pF
Figure 32. Glitch Impulse, Falling Edge, 1 LSB Step
DAC code transition from 102d to 922d, typical channel shown,
DAC output loaded with 5 kΩ//200 pF
Figure 33. Full-Scale Settling Time, Rising Edge
DAC code transition from 922d to 102d, typical channel shown,
DAC output loaded with 5 kΩ//200 pF
Figure 34. Full-Scale Settling Time, Falling Edge
DAC output loaded with 5 kΩ//200 pF
Figure 35. Power-on Glitch
l TEXAS INSTRUMENTS mun
Frequency (Hz)
Noise (nV/—Hz)
10 2030 50 100 200 5001000 10000 100000
0
200
400
600
800
1000
D051
Code 0x20
Code 0x800
Code 0xFDC
Frequency (Hz)
AC PSRR (dB)
10 100 1000 10000 100000 1000000
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
D050
VNOISE (5 PV/div)
D052
Time (1 ms/div)
DAC Output (mV)
-20
-15
-10
-5
0
5
10
15
20
D048
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Time (1 Ps/div)
D049
VOUT (2 mV/div)
SCL (2.5 V/div)
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Typical Characteristics: 5.5 V (continued)
at TA= 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
DAC output loaded with 5 kΩ//200 pF
Figure 36. Power-off Glitch
DAC code at mid-scale and reference tied to VDD and output
loaded with 5 kΩ//200 pF
Figure 37. Clock Feedthrough with SCL = 1 MHz
DAC code at full-scale and output loaded with 5 kΩ//200 pF, VDD =
5.25 V + 0.2 VPP and VREFIN = 4.5 V
Figure 38. DAC Output AC PSRR vs Frequency
DAC code at mid-scale
Figure 39. DAC Output Noise 0.1 Hz to 10 Hz
Figure 40. DAC Output Noise Spectral Density
l TEXAS INSTRUMENTS
VDD (V)
Zero Code Error (mV)
1.8 2.725 3.65 4.575 5.5
0
2
4
6
8
10
12
D024
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
VDD (V)
INL Error Max-Min (LSB)
1.8 2.725 3.65 4.575 5.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D021
INL Max
INL Min
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7.12 Typical Characteristics
at TA= 25°C, and DAC outputs unloaded (unless otherwise noted)
Figure 41. Integral Linearity Error vs Supply Voltage Figure 42. Differential Linearity Error vs Supply Voltage
Figure 43. Total Unadjusted Error vs Supply Voltage Figure 44. Zero Code Error vs Supply Voltage
Figure 45. Offset Error vs Supply Voltage Figure 46. Gain Error vs Supply Voltage
l TEXAS INSTRUMENTS
VREFIN (V)
Zero Code Error (mV)
1.8 2.725 3.65 4.575 5.5
0
2
4
6
8
10
12
D031
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
VDD (V)
Full Scale Error (%FSR)
1.8 2.725 3.65 4.575 5.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D027
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
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7.13 Typical Characteristics
at TA= 25°C, VDD = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
Figure 47. Full Scale Error vs Supply Voltage Figure 48. Integral Linearity Error vs Reference Voltage
Figure 49. Differential Linearity Error vs Reference Voltage Figure 50. Total Unadjusted Error vs Reference Voltage
Figure 51. Zero Code Error vs Reference Voltage Figure 52. Offset Error vs Reference Voltage
l TEXAS INSTRUMENTS
VOUTA
DAC
Active
Registers
DAC
Buffer
Registers BUF
Channel A
Power Down LogicResistive Network
I2CTM Interface
Power On Reset
DACx3608
SCL
SDA
A0
DAC
VDD VREFIN
AGND
LDAC
Channel H VOUTH
CLR
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8 Detailed Description
8.1 Overview
The DAC53608 and DAC43608 are a pin-compatible family of eight-channel, buffered voltage-output digital-to-
analog converters (DACs) in 10- and 8-bit resolution. With an external reference ranging from 1.8 V to 5.5 V, full
scale output voltage of 1.8 V to 5.5 V can be achieved. These devices are guaranteed monotonic across the
power supply range.
Communication to the devices is done through I2CTM compatible interface. The I2CTM standard (100 kbps), fast
(400 kbps), and fast+ mode (1Mbps) are supported for these devices. These devices include a load DAC (LDAC)
pin for simultaneous DAC update.
The DACx3608 devices are characterized for operation over the temperature range of -40°C to +125°C and are
available in tiny QFN packages.
8.2 Functional Block Diagram
Figure 53. DACx3608 DAC Block Diagram
l TEXAS INSTRUMENTS
OUT REF
N
DACn_DATA
V X V IN
2
u
String DAC output
DAC
buffer
register
LDAC Trigger
(synchronous mode)
DAC
active
register
Serial interface
DAC data register
WRITE READ
(asynchronous mode)
VOUT
AGND
VREFIN VDD
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx3608 family of devices consists of string architecture with an output buffer
amplifier. Figure 54 shows a block diagram of the DAC architecture.
Figure 54. DACx3608 DAC Architecture
8.3.1.1 DAC Transfer Function
The device writes the input data to the individual DAC Data registers in straight binary format. After a power-on
or a reset event, the device sets all DAC registers to zero-code. Equation 1 shows DAC transfer function.
where:
• N = resolution in bits
– Either 10 (DAC53608) or 8 (DAC43608)
• DACn_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
• DACn_DATA ranges from 0 to 2N– 1
• VREFIN is the DAC reference voltage (1)
8.3.1.2 DAC Register Update and LDAC Functionality
The device stores the data written to the DAC Data registers in the DAC buffer registers. Transfer of data from
the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or
initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC outputs
change to their new values.
The update mode for each DAC channel is determined by the status of LDAC pin.
In asynchronous mode (LDAC = 0 before the DAC write command), a write to the DAC data register results in an
immediate update of the DAC active register and DAC output at the end of I2CTM frame.
In synchronous mode (LDAC = 1 before the DAC write command), writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC is pulled to 0. The
synchronous update mode enables simultaneous update of all DAC outputs.
8.3.1.3 CLR Functionality
The CLR pin is an asynchronous input pin to the DAC. When this pin is pulled low (logic 0), the DAC buffers and
the DAC active registers to zero code.
i Tans INSTRUMENTS
No power-on reset
Power-on reset
0.70
Undefined
0.00
1.70
1.80
5.50
VDD (V)
Specified supply
voltage range
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Feature Description (continued)
8.3.1.4 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
VDD.Equation 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
VREFIN pin
8.3.2 Reference
The DACx3608 requires an external reference to operate. However, the reference pin VREFIN and the supply pin
VDD can be tied together. The reference input pin voltage ranges from 1.8 V to VDD. The typical input impedance
of this pin when all the channels are powered on is 12.5 kΩ.
8.3.3 Power-on-Reset (POR)
The DACx3608 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to the default values, and communication with the device is valid only after a 5-ms after VDD reaches
DAC operating range. The default value for the DAC data registers is zero-code . The DAC output remains at the
power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in Figure 55, in order to make sure that the internal capacitors discharge and reset the
device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms.
When VDD drops to less than 1.7 V but remains greater than 0.7 V (shown as the undefined region), the device
may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR.
When VDD remains greater than 1.7 V, a POR does not occur.
Figure 55. Threshold Levels for VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SW-RST bit in the
TRIGGER register (address 2h).
8.4 Device Functional Modes
The DACx3608 has two modes of operation: normal and power-down.
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Device Functional Modes (continued)
8.4.1 Power-Down Mode
The DACx3608 DAC output amplifiers can be independently or globally powered down (10K to AGND) through the
DEVICE_CONFIG register. In this state, the device consumes 50 µA (VDD = 1.8 V). At power-up all output
channels buffer amplifiers start in power down to 10K mode until a power up command is issue by writing 0 to
the per channel power down registers.
8.5 Programming
The DACx3608 devices have a 2-wire serial interface: SCL, SDA, and one address pin, A0, as shown in Pin
Configurations and Functions. The I2CTM bus consists of a data line (SDA) and a clock line (SCL) with pull-up
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2CTM compatible devices
connects to the I2CTM bus through open drain I/O pins, SDA and SCL.
The I2CTM specification states that the device that controls communication is called a master, and the devices
that are controlled by the master are called slaves. The master device generates the SCL signal. The master
device also generates special timing conditions (start condition, repeated start condition, and stop condition) on
the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master
device on an I2CTM bus is typically a microcontroller or a digital signal processor (DSP). The DACx3608 family
operates as a slave device on the I2CTM bus. A slave device acknowledges master's commands and upon
master's control, receives or transmits data.
Typically, the DACx3608 family operates as a slave receiver. A master device writes to the DACx3608, a slave
receiver. However, if a master device requires the DACx3608 internal register data, the DACx3608 family
operates as a slave transmitter. In this case, the master device reads from the DACx3608 According to I2CTM
terminology, read and write refer to the master device.
The DACx3608 family is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast+ mode (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not output
current. The low-level output current would be 3 mA similar to the case of standard and fast modes. The
DACx3608 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports
the general call reset function. Sending the following sequence initiates a software reset within the device;
Start/Repeated Start, 0x00, 0x06, Stop. The reset is asserted within the device on the rise edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2CTM interface works with serial bytes. At the end of each byte, a ninth
clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low
during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the
high period of the ninth clock cycle as shown in Figure 56.
SCL
Stop
condition
SDA
Start
condition
SP
Data output
by Transmitter
Data output
by Receiver
SCL from
Master
12
S
Start
condition
89
Not acknowledge
Acknowledge
Clock pulse for
acknowledgement
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Programming (continued)
Figure 56. Acknowledge and Not Acknowledge on the I2CTM Bus
8.5.1 F/S Mode Protocol
1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 57. All I2CTM compatible devices
recognize a start condition.
Figure 57. Start and Stop Conditions
Ex:1
SCL
Data line stable
Data valid
SDA
Change of data
allowed
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Programming (continued)
Figure 58. Bit Transfer on the I2CTM Bus
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 58. All
devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge by pulling the SDA line low during the
entire high period of the 9th SCL cycle, as shown in Figure 56 by pulling the SDA line low during the entire
high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows the communication link
with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. So the acknowledge signal can
be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data
sequences consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 57). This action releases the bus and stops the communication
link with the addressed slave. All I2CTM-compatible devices recognize the stop condition. Upon receipt of a
stop condition, the bus is released, and all slave devices then wait for a start condition followed by a
matching address.
1 7 8 9 12 - 8 9
S
or
Sr
SDA
SCL
MSB
Address
START or
REPEATED
START
condition
Recognize
START or
REPEATED
START
condition
R/W
ACK
Acknowledgement
signal from Slave
Generate ACKNOWLEDGE
signal
Clock line held low while
interrupts are serviced
Sr
or
P
P
Sr
REPEATED
START or
STOP
condition
Recognize
STOP or
REPEATED
START
condition
ACK
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Programming (continued)
8.5.2 DACx3608 I2CTM Update Sequence
For a single update, the DACx3608 requires a start condition, a valid I2CTM address byte, a command byte, and
two data bytes ( the most significant data byte (MSDB) and least significant data byte (LSDB)), as listed in
Table 1.
Table 1. Update Sequence
MSB .... LSB ACK MSB ... LSB ACK MSB ... LSB ACK MSB ... LSB ACK
Address (A) byte Command byte MSDB LSDB
DB [32:24] DB [23:16] DB [15:8] DB [7:0]
After each byte is received, the DACx3608 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in Figure 59. These four bytes and acknowledge cycles make up
the 36 clock cycles required for a single update to occur. A valid I2CTM address byte selects the DACx3608
devices.
Figure 59. I2CTM Bus Protocol
The command byte sets the operational mode of the selected DACx3608 device. When the operational mode is
selected by this byte, the DACx3608 series must receive two data bytes, the most significant data byte (MSDB)
and least significant data byte (LSDB), for a data update to occur. The DACx3608 devices perform an update on
the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the
fast+ mode (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition is
received, the DACx3608 family releases the I2CTM bus and awaits a new start condition.
8.5.3 DACx3608 Address Byte
The address byte, as shown in Table 2, is the first byte received following the START condition from the master
device. The first four bits (MSBs) of the address are factory preset to 1001. The next 3 bits of the address are
controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is sampled
during the first byte of each data frame to determine the address. The device latches the value of the address pin
and consequently will respond to that particular address according to Table 3.
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The DACx3608 family supports broadcast addressing. Broadcast addressing can be used for synchronously
updating or powering down multiple DACx3608 devices. The DACx3608 family is designed to work with other
members of the family to support multichip synchronous update. Using the broadcast address, the DACx3608
devices respond regardless of the states of the address pins. Broadcast is supported only in write mode.
Table 2. DACx3608 Address Byte
COMMENT MSB LSB
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
General address 1 0 0 1 See Table 3 (slave address column) 0 or 1
Broadcast address 1 0 0 0 1 1 1 0
Table 3. Address Format
SLAVE ADDRESS A0 PIN
1001 000 AGND
1001 001 VDD
1001 010 SDA
1001 011 SCL
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8.5.4 DACx3608 Command Byte
The DACx3608 command byte (shown in Table 4) controls which command is executed and which register is
being accessed when writing to or reading from the DACx3608 series.
Table 4. DACx3608 Command Byte
B23 B22 B21 B20 B19 B18 B17 B16 COMMENT
0 0 0 0 0 0 0 1 DEVICE_CONFIG
0 0 0 0 0 0 1 0 STATUS/TRIGGER
0 0 0 0 0 0 1 1 BRDCAST
0 0 0 0 1 0 0 0 DACA_DATA
0 0 0 0 1 0 0 1 DACB_DATA
0 0 0 0 1 0 1 0 DACC_DATA
0 0 0 0 1 0 1 1 DACD_DATA
0 0 0 0 1 1 0 0 DACE_DATA
0 0 0 0 1 1 0 1 DACF_DATA
0 0 0 0 1 1 1 0 DACG_DATA
0 0 0 0 1 1 1 1 DACH_DATA
8.5.5 DACx3608 Data Byte (MSDB and LSDB)
The MSDB and LSDB contain the data that are passed to the register(s) specified by the command byte as
shown in Table 5. The DACx3608 family updates at the falling edge of the acknowledge signal that follows the
LSDB[0] bit.
Table 5. DACx3608 Data Byte
COMMAND BITS DATA BITS
MSDB LSDB
B19 - B16 B15 - B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEVICE_CONFIG x 0 0 0 PD
N-
All PDNH PDNG PDNF PDNE PDND PDNC PDNB PDNA
STATUS/TRIGGER x DEVICE_ID x x SW_RST
BRDCAST x BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB left aligned x x
DACA_DATA x DACA_DATA[9:0] / DACA_DATA[7:0] – MSB left aligned x x
DACB_DATA x DACB_DATA[9:0] / DACB_DATA[7:0] – MSB left aligned x x
DACC_DATA x DACC_DATA[9:0] / DACC_DATA[7:0] – MSB left aligned x x
DACD_DATA x DACD_DATA[9:0] / DACD_DATA[7:0] – MSB left aligned x x
DACE_DATA x DACE_DATA[9:0] / DACE_DATA[7:0] – MSB left aligned x x
DACF_DATA x DACF_DATA[9:0] / DACF_DATA[7:0] – MSB left aligned x x
DACG_DATA x DACG_DATA[9:0] / DACG_DATA[7:0] – MSB left aligned x x
DACH_DATA x DACH_DATA[9:0] / DACAH_DATA[7:0] – MSB left aligned x x
8.5.6 DACx3608 I2CTM Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to '1' for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
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An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register are
read out. All the registers in DACx3608 family can be read out with the exception of SW-RST register. Table 5
shows the read command set.
Note that it is not possible to use the broadcast address for reading.
Table 6. Read Sequence
S MSB … R/W
(0) ACK MSB … LSB ACK Sr MSB … R/W
(1) ACK MSB … LSB ACK MSB … LSB ACK
ADDRESS
BYTE COMMAND
BYTE Sr ADDRESS
BYTE MSDB LSDB
From Master Slave From Master Slave From Master Slave From Slave Master From Slave Master
8.6 Register Map
Table 7. Register Address
B23 B22 B21 B20 B19 B18 B17 B16 COMMENT
0 0 0 0 0 0 0 1 DEVICE_CONFIG
0 0 0 0 0 0 1 0 STATUS/TRIGGER
0 0 0 0 0 0 1 1 BRDCAST
0 0 0 0 1 0 0 0 DACA_DATA
0 0 0 0 1 0 0 1 DACB_DATA
0 0 0 0 1 0 1 0 DACC_DATA
0 0 0 0 1 0 1 1 DACD_DATA
0 0 0 0 1 1 0 0 DACE_DATA
0 0 0 0 1 1 0 1 DACF_DATA
0 0 0 0 1 1 1 0 DACG_DATA
0 0 0 0 1 1 1 1 DACH_DATA
Table 8. Register Map
COMMAND BITS DATA BITS
MSDB LSDB
B19 - B16 B15 - B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEVICE_CONFIG x 0 0 0 PD
N-
All PDNH PDNG PDNF PDNE PDND PDNC PDNB PDNA
STATUS/TRIGGER x DEVICE_ID x x SW_RST
BRDCAST x BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB left aligned x x
DACA_DATA x DACA_DATA[9:0] / DACA_DATA[7:0] – MSB left aligned x x
DACB_DATA x DACB_DATA[9:0] / DACB_DATA[7:0] – MSB left aligned x x
DACC_DATA x DACC_DATA[9:0] / DACC_DATA[7:0] – MSB left aligned x x
DACD_DATA x DACD_DATA[9:0] / DACD_DATA[7:0] – MSB left aligned x x
DACE_DATA x DACE_DATA[9:0] / DACE_DATA[7:0] – MSB left aligned x x
DACF_DATA x DACF_DATA[9:0] / DACF_DATA[7:0] – MSB left aligned x x
DACG_DATA x DACG_DATA[9:0] / DACG_DATA[7:0] – MSB left aligned x x
DACH_DATA x DACH_DATA[9:0] / DACAH_DATA[7:0] – MSB left aligned x x
Table 9. DACx3608 Register Names
OFFSET ACRONYM REGISTER NAME SECTION
01h DEVICE_CONFIG Device Configuration Register DEVICE_CONFIG Register (offset =
01h) [reset = 00FFh]
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Table 9. DACx3608 Register Names (continued)
OFFSET ACRONYM REGISTER NAME SECTION
02h STATUS/TRIGGER Status and Trigger Register STATUS/TRIGGER Register (offset =
02h) [reset = 0300h for DAC53608,
reset = 0500h for DAC43608]
03h BRDCAST Broadcast Data Register BRDCAST Register (offset = 03h)
[reset = 0000h]
08h - 0Fh DACn_DATA DACn Data Register DACn_DATA Register (offset = 08h to
0Fh) [reset = 0000h]
8.6.1 DEVICE_CONFIG Register (offset = 01h) [reset = 00FFh]
Figure 60. DEVICE_CONFIG Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don't Care 0 0 0 PDN-
Alll PDNH PDNG PDNF PDNE PDND PDNC PDNB PDNA
W R/W
Table 10. DEVICE_CONFIG Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
15-12 Don't Care W 0h Don't Care
11-9 RESERVED W 00 Reserved
8 PDN-All R/W 0 Global power down bit, When set to '1', all channels and all bias
blocks are powered down
7-0 PDNn R/W FFh DACn in power down mode (Output buffers power down 10K to
AGND) when this bit is set to '1' (default). At power-up all output
channels buffer amplifiers start in power down to 10K mode until
a power up command is issue by writing 0 to these registers.
8.6.2 STATUS/TRIGGER Register (offset = 02h) [reset = 0300h for DAC53608, reset = 0500h for
DAC43608]
Figure 61. STATUS/TRIGGER Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don't Care DEVICE_ID Don't
Care Don't
Care SW_RST
W R W W W
Table 11. STATUS/TRIGGER Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
15-12 Don't Care W 0h Don't Care
11-6 DEVICE_ID R DAC536
08:
001100
DAC436
08:
010100
Device Identification number
DAC53608: 001100
DAC43608: 010100
5-4 Don't Care W 0h Don't Care
3-0 SW_RST W 0h Device resets to default value when this register is set to 1010
8.6.3 BRDCAST Register (offset = 03h) [reset = 0000h]
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Figure 62. BRDCAST Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don't Care BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB Left aligned Don't
Care Don't
Care
W W W W
Table 12. BRDCAST Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
15-12 Don't Care W 0h Don't Care
11-2 BRDCAST_DATA[9:0] /
BRDCAST_DATA[7:0] W 000h Writing to the BRDCAST register forces the DAC channel to
update its active register data to the BRDCAST_DATA one.
Data is MSB aligned in straight binary format and follows the
format below:
DAC53608: { DATA[9:0] }
DAC43608: { DATA[7:0], x, x }
x – Don’t care bits
1-0 Don't Care W 00 Don't Care
8.6.4 DACn_DATA Register (offset = 08h to 0Fh) [reset = 0000h]
Figure 63. DACn_DATA Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don't Care BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB Left aligned Don't
Care Don't
Care
W W W W
Table 13. DACn_DATA Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
15-12 Don't Care W 0h Don't Care
11-2 DACn_DATA[9:0] /
DACn_DATA[7:0] W 000h Writing to the DACn_DATA register forces the respective DAC
channel to update its active register data to the DACn_DATA.
Data is MSB aligned in straight binary format and follows the
format below:
DAC53608: { DATA[9:0] }
DAC43608: { DATA[7:0], x, x }
x – Don’t care bits
1-0 Don't Care W 00 Don't Care
VDAC +
RSET
VCC
Q1
DAC53608
LED
ISET
ILED = ISET
VDAC
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DACx3608 is a buffered output, 8-channel, low power DAC available in a tiny 3X3 package. The multi-
channel, low power, and small package makes this DAC suitable for general purpose applications in wide range
of end equipments. Some of the most common applications for this devices are LED biasing in multi-function
printers, power supply supervision with programmable comparators, offset and gain trimming in precision circuits,
and power supply margining.
9.2 Typical Applications
9.2.1 Programmable LED Biasing
End equipments such as multi-function printers, projectors and electronic point-of-sale (EPOS) require a steady
luminous intensity from the LED. Figure 64 shows a simplified circuit diagram for biasing an LED using
DACx3608.
Figure 64. LED Biasing
9.2.1.1 Design Requirements
• Programmable Constant Current through an LED tied to power supply on one end
• DAC Output Range: 0 – 5 V
• LED Current Range: 0 – 20 mA
l TEXAS INSTRUMENTS ILEEI "VIN us 15 2 5 Von: (V) 3 :5 ‘5
DAC
SET
SET
V
IR
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The DAC is used to set the source current of a MOSFET using a unity-gain buffer as shown in Figure 64. The
LED is connected between the power supply and the drain of the MOSFET. This configuration allows the DAC to
control or set the amount of current through the LED. The buffer following the DAC controls the gate-source
voltage of the MOSFET inside the feedback loop thus compensating this drop and corresponding drift due to
temperature, current, and ageing of the MOSFET. The current set by the DAC that flows through the LED can be
calculated with Equation 2. in order to generate 0 – 20mA from a 0 – 5 V DAC output range, a 250-ΩRSETis
required.
(2)
The pseudocode for getting started with the LED biasing application is given below.
//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program mid code (or the desired voltage) on all channels
WRITE DACA_DATA(0x08), 0x07FC //10-bit MSB aligned
WRITE DACB_DATA(0x09), 0x07FC //10-bit MSB aligned
WRITE DACC_DATA(0x0A), 0x07FC //10-bit MSB aligned
WRITE DACD_DATA(0x0B), 0x07FC //10-bit MSB aligned
WRITE DACE_DATA(0x0C), 0x07FC //10-bit MSB aligned
WRITE DACF_DATA(0x0D), 0x07FC //10-bit MSB aligned
WRITE DACG_DATA(0x0E), 0x07FC //10-bit MSB aligned
WRITE DACH_DATA(0x0F), 0x07FC //10-bit MSB aligned
9.2.1.3 Application Curve
Figure 65. DC Transfer Characteristics of LED Biasing Circuit
‘5‘ TEXAS INSTRUMENTS 4-‘5
2
THLD-LO DAC
1 2
R
V =V × R +R
§ ·
¨ ¸
© ¹
THLD-HI +
+
THLD-LO
DACx3608 VOUT
VIO
RPULL-UP
R1
R2
VIN
RB
RA
VDAC
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Typical Applications (continued)
9.2.2 Programmable Window Comparator
End equipments that use a centralized power supply such as network servers, optical modules, and others
require the monitoring of power buses in order to protect the components. This monitoring or supervision is
accomplished using a window comparator. A window comparator monitors a signal input for upper and lower
threshold violations. A trigger signal is generated when the threshold violations occur. Multi-channel monitoring is
required in order to supervise all power supplies available in a module. DACx3608 provides a easy to use, low-
footprint method to address this requirement.
Figure 66. Programmable Window Comparator
9.2.2.1 Design Requirements
• Voltage to be Monitored: 5 V
• High Threshold: 5 V + 10%
• Low Threshold: 5 V – 10%
• Trigger Output: 3.3-V Open-Drain Single Output
9.2.2.2 Detailed Design Procedure
Figure 66 provides an example in which single DAC channel is used to compare both high and low thresholds. A
dual comparator is used per DAC channel as shown. A voltage divider formed by resistors RAand RBare used in
order to bring the signal level within the DAC range. Another pair of resistors R1and R2are used for setting the
low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel for
monitoring both high and low threshold levels. The comparators should be open-drain in order to provide the
following advantages.
• Generate a logic output level suitable for the monitoring processor
• Allow shorting of the two outputs in order to generate a single trigger
In the circuit depicted in Figure 66 the output of the circuit remains HIGH as long as the signal input remains
within the high and low threshold levels. Upon violation of any one threshold, the output goes LOW. Equation 3
provides the derivation of the low threshold voltage from the high threshold set by the DAC.
(3)
l TEXAS INSTRUMENTS Valngos (V) m Vuuv 9 w (Ailenuavedl w wuno a mmm 1 s 5 a 3 _ _ 2 1 o 2u22242525w3236353540624¢ Time (ms) Aswsufizfmssfiasn
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Typical Applications (continued)
In order to monitor a power supply of 5 V within ±10%, it is recommended to place the nominal value at the DAC
mid code. The output range of DACx3608 to be 0 – 5 V, thus the mid code voltage output is 2.5 V. Hence, RA
and RBcan be chosen in such a way that the voltage to be compared is 2.5 V. For this example, RAis equal to
RBand we can use 10-kΩresistors for both of them. One channel of the DACx3608 must be programmed to
VTHLD-HI, for example 2.5 V + 5% = 2.625 V. This corresponds to a 10-bit DAC code of (210÷5 V) × 2.625 V =
537.6 (0x21 Ah). In order to generate VTHLD-LO(for example, 2.5 V – 5% = 2.405 V) from 2.625 V, the values of R1
and R2can be calculated as 7.5 kΩand 82 kΩ, respectively using Equation 3. The pseudocode for getting
started with the programmable window comparator application with the desired DAC value is given below.
//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program 2.625V on channel A
WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned
9.2.2.3 Application Curve
Figure 67. Programmable Comparator Output Waveform
10 Power Supply Recommendations
The DACx3608 family of devices does not require specific supply sequencing. It requires a single power supply,
VDD. A 0.1-µF decoupling capacitor is recommended for the VDD pin.
Analog
Outputs
Analog
Outputs
Digital IO
VDD
VREF
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11 Layout
11.1 Layout Guidelines
The DACx3608 pinout separates the analog, digital, and power pins for an optimized layout. For signal integrity,
it is recommended that digital and analog traces be separated and decoupling capacitors places close with the
device pins.
11.2 Layout Example
Figure 68 shows an example layout drawing with decoupling capacitors and pull-up resistors.
Figure 68. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: DAC53608EVM User's Guide (SLAU790)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
DAC53608 Click here Click here Click here Click here Click here
DAC43608 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
TEXAS INSTRUMENTS Samples Sample: Sample: Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DAC43608RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D43608
DAC43608RTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D43608
DAC53608RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D53608
DAC53608RTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D53608
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC43608RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
DAC43608RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
DAC53608RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
DAC53608RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC43608RTER WQFN RTE 16 3000 367.0 367.0 35.0
DAC43608RTET WQFN RTE 16 250 210.0 185.0 35.0
DAC53608RTER WQFN RTE 16 3000 367.0 367.0 35.0
DAC53608RTET WQFN RTE 16 250 210.0 185.0 35.0
Pack Materials-Page 2
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GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WQFN - 0.8 mm max heightRTE 16
PLASTIC QUAD FLATPACK - NO LEAD
3 x 3, 0.5 mm pitch
4225944/A
‘D ’ E WW J w L f a: fib ca ,iwligig a 3 \ C 3773 ‘ C4 DJ/ H mm H 7 \ n 16 E $ 1% ' TEXAS
www.ti.com
PACKAGE OUTLINE
C
16X 0.30
0.18
1.68 0.07
16X 0.5
0.3
0.8 MAX
(DIM A) TYP
0.05
0.00
12X 0.5
4X
1.5
A3.1
2.9 B
3.1
2.9
WQFN - 0.8 mm max heightRTE0016C
PLASTIC QUAD FLATPACK - NO LEAD
4219117/B 04/2022
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
17 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.600
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(2.8)
(2.8)
(0.58)
TYP
( 1.68)
(R0.05)
ALL PAD CORNERS (0.58) TYP
WQFN - 0.8 mm max heightRTE0016C
PLASTIC QUAD FLATPACK - NO LEAD
4219117/B 04/2022
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
17
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
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EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.55)
(R0.05) TYP
WQFN - 0.8 mm max heightRTE0016C
PLASTIC QUAD FLATPACK - NO LEAD
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
ALL AROUND
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
4
58
9
12
13
16
17
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