SN74HCS10-Q1 Datasheet by Texas Instruments

V'.‘ I TEXAS INSTRUMENTS
Input Voltage
Supply Current
Schmitt-trigger
CMOS Input
Response
Waveforms
Standard
CMOS Input
Response
Waveforms
Input Voltage
Supply Current
Input
Voltage
Input Voltage Time
Current
Output
Voltage
Current
Output
Voltage
Input
Voltage
Time
Current
Output
VoltageCurrent
Output
Voltage
Input
Voltage
Input Voltage
Waveforms
Low Power Noise Rejection Supports Slow Inputs
Time Time
Time Time
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Folder
Order
Now
Technical
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Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS10-Q1
SCLS764A –AUGUST 2019–REVISED SEPTEMBER 2019
SN74HCS10-Q1 Automotive Triple 3-Input NAND Gates with Schmitt-Trigger Inputs
1
1 Features
1• AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C,
TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
• Wide operating voltage range: 2 V to 6 V
• Schmitt-trigger inputs allow for slow or noisy input
signals
• Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
• ±7.8-mA output drive at 5 V
2 Applications
•Alarm / tamper detect circuit
• S-R latch
3 Description
This device contains three independent 3-input NAND
Gates with Schmitt-trigger inputs. Each gate performs
the Boolean function Y = A ●B●C in positive logic.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCS10QDRQ1 SOIC (14) 8.70 mm × 3.90 mm
SN74HCS10QPWRQ1 TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Benefits of Schmitt-trigger Inputs
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 5
7 Parameter Measurement Information .................. 5
8 Detailed Description.............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Documentation Support ........................................ 13
12.2 Related Links ........................................................ 13
12.3 Community Resources.......................................... 13
12.4 Trademarks........................................................... 13
12.5 Electrostatic Discharge Caution............................ 13
12.6 Glossary................................................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to Revision A Page
• Added D package to Device Information table....................................................................................................................... 1
• Added D package column to Thermal Information table........................................................................................................ 4
l TEXAS INSTRUMENTS HHHHHHH HHHHHHH
1B
1A
2A
2B
2C
2Y
GND
1C
VCC
1Y
3C
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
3
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5 Pin Configuration and Functions
D or PW Package
14-Pin SOIC or TSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1B 2 Input Channel 1, Input B
2A 3 Input Channel 2, Input A
2B 4 Input Channel 2, Input B
2C 5 Input Channel 2, Input C
2Y 6 Output Channel 2, Output Y
GND 7 — Ground
3Y 8 Output Channel 3, Output Y
3A 9 Input Channel 3, Input A
3B 10 Input Channel 3, Input B
3C 11 Input Channel 3, Input C
1Y 12 Output Channel 1, Output Y
1C 13 Input Channel 1, Input C
VCC 14 — Positive Supply
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI< –0.5 V or VI> VCC +
0.5 V ±20 mA
IOK Output clamp current(2) VI< –0.5 V or VI> VCC +
0.5 V ±20 mA
IOContinuous output current VO= 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
TJJunction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C
l TEXAS INSTRUMENTS
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(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2 ±4000
V
Charged device model (CDM), per AEC Q100-
011 CDM ESD Classification Level C6 ±1500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
TAAmbient temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC
SN74HCS10-Q1
UNITPW (TSSOP) D (SOIC)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 151.7 133.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 79.4 89.0 °C/W
RθJB Junction-to-board thermal resistance 94.7 89.5 °C/W
ΨJT Junction-to-top characterization parameter 25.2 45.5 °C/W
ΨJB Junction-to-board characterization parameter 94.1 89.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VT+ Positive switching threshold
2 V 0.7 1.5
V4.5 V 1.7 3.15
6 V 2.1 4.2
VT- Negative switching threshold
2 V 0.3 1.0
V4.5 V 0.9 2.2
6 V 1.2 3.0
ΔVTHysteresis (VT+ - VT-)
2 V 0.2 1.0
V4.5 V 0.4 1.4
6 V 0.6 1.6
VOH High-level output voltage VI= VIH or VIL
IOH = -20 µA 2 V to 6 V VCC – 0.1 VCC – 0.002
VIOH = -6 mA 4.5 V 4.0 4.3
IOH = -7.8 mA 6 V 5.4 5.75
VOL Low-level output voltage VI= VIH or VIL
IOL = 20 µA 2 V to 6 V 0.002 0.1
VIOL = 6 mA 4.5 V 0.18 0.30
IOL = 7.8 mA 6 V 0.22 0.33
IIInput leakage current VI= VCC or 0 6 V ±100 ±1000 nA
ICC Supply current VI= VCC or 0, IO= 0 6 V 0.1 2 µA
CiInput capacitance 2 V to 6 V 5 pF
Cpd Power dissipation capacitance
per gate No load 2 V to 6 V 10 pF
l TEXAS INSTRUMENTS 055
VI ± Input Voltage (V)
ICC ± Supply Current (mA)
0 0.5 1 1.5 2 2.5 3 3.5
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
VI ± Input Voltage (V)
ICC ± Supply Current (mA)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
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6.6 Switching Characteristics
CL= 50 pF; over operating free-air temperature range; typical values measured at TA= 25°C (unless otherwise noted). See
Parameter Measurement Information.
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX UNIT
tpd Propagation delay A or B or C Y
2 V 14 40
ns4.5 V 6 17
6 V 5 16
ttTransition-time Y
2 V 9 16
ns4.5 V 5 9
6 V 4 8
6.7 Typical Characteristics
TA= 25°C
Figure 1. Output driver resistance in Low state Figure 2. Output driver resistance in High state
Figure 3. Typical supply current versus input voltage across
common supply values (2 V to 3.3 V) Figure 4. Typical supply current versus input voltage across
common supply values (4.5 V to 6 V)
7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤1 MHz, ZO= 50 Ω, tt< 2.5 ns.
• The outputs are measured one at a time, with one input transition per measurement.
l TEXAS INSTRUMENTS Tes| 77777 vc . \ i t m we I ° ‘ T +1 r» i W“ 777777 v: 5 m H HF ‘ ‘ ,7, m 0 \ % k—>F k—pk m
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
CL(1)
From Output
Under Test
Test
Point
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Parameter Measurement Information (continued)
CL= 50 pF and includes probe and jig capacitance.
Figure 5. Load Circuit Figure 6. Voltage Waveforms
Transition Times
The maximum between tPLH and TPHL is used for tpd.Figure 7. Voltage Waveforms
Propagation Delays
l TEXAS INSTRUMENTS
One of Three Channels
xA
xC
xYxB
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8 Detailed Description
8.1 Overview
This device contains three independent 3-input NAND Gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A ●B●C in positive logic.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVTin the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
‘5‘ TEXAS INSTRUMENTS ,,,,,,,,,,,,,,,,,,,,
GND
Logic
Input Output
VCC
Device
-IIK
+IIK +IOK
-IOK
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Feature Description (continued)
Figure 8. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1. Function Table
INPUTS OUTPUT
Y
ABC
H H H L
L X X H
X L X H
X X L H
l TEXAS INSTRUMENTS \\
System Controller
Tamper
Switch 1
RA
SAQ
R1
Tamper
Indicator
R2
SB
Tamper
Switch 2
RB
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In this application, two 3-input NAND gates are used to create an active-low SR latch as shown in Figure 9. The
additional gate can be used elsewhere in the system, or the inputs can be grounded and left unused.
The SN74HCS10-Q1 is used to drive the tamper indicator LED and provide one bit of data to the system
controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output remains HIGH until
the system controller addresses the event and sends a LOW signal to the R input which returns the Q output
back to LOW.
The inputs of this active-low SR latch can often be driven by open-drain outputs which can produce slow input
transition rates when they transition from LOW to Hi-Z. This makes the SN74HCS10-Q1 ideal for the application
because it has Schmitt-trigger inputs that do not have input transition rate requirements.
9.2 Typical Application
Figure 9. Typical application block diagram
9.2.1 Design Requirements
• All signals in the system operate at 5 V
• Avoid unstable state by not having LOW signals on both R and S inputs
• Q output is HIGH when any S input is LOW
– Q output remains HIGH until any R input is LOW
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS10-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
l TEXAS INSTRUMENTS
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Typical Application (continued)
The SN74HCS10-Q1 can drive a load with a total capacitance less than or equal to 50 pF connected to a high-
impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS10-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS10-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics. The plots in and provide a
typical relationship between output voltage and current for this device.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS10-
Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
‘5‘ TEXAS INSTRUMENTS
Q
R
S
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Typical Application (continued)
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Figure 10. Application timing diagram
*9 TEXAS INSTRUMENTS IIIIIII IIIIIII
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2B
2C
2Y
GND VCC
1C
1Y
3B
3A
3YGND
VCC
3C
2A
0.1 F
Unused inputs
tied to VCC
Bypass capacitor
placed close to
the device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused output
left floating
12
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
Figure 11. Example layout for the SN74HCS10-Q1
l TEXAS INSTRUMENTS Am
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•HCMOS Design Considerations
•CMOS Power Consumption and CPD Calculation
•Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HCS10QDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS10Q1
SN74HCS10QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS10Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF SN74HCS10-Q1 :
•Catalog: SN74HCS10
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HCS10QDRQ1 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCS10QPWRQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCS10QDRQ1 SOIC D 14 2500 356.0 356.0 35.0
SN74HCS10QPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0
Pack Materials-Page 2
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
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