DRV603 Datasheet by Texas Instruments

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DRV603
LEFT
RIGHT
-
+
-
+
DAC
DAC
DRV603
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
DirectPath™, 3-VRMS Line Driver With Adjustable Gain
Check for Samples: DRV603
1FEATURES DESCRIPTION
234• DirectPath™ The DRV603PW is a 3-VRMS pop-free stereo line
driver designed to allow the removal of the output
– Eliminates Pop/Clicks dc-blocking capacitors for reduced component count
– Eliminates Output DC-Blocking Capacitors and cost. The device is ideal for single-supply
– Provides Flat Frequency Response 20 electronics where size and cost are critical design
Hz–20 kHz parameters.
• Low Noise and THD Designed using TI’s patented DirectPath™
– SNR > 109 dB technology, The DRV603 is capable of driving 3 Vrms
into a 2.5-kΩload with 5-V supply voltage. The
– Typical Vn < 7 μVms device has differential inputs and uses external
– THD+N < 0.002% gain-setting resistors to support a gain range of ±1
• Output Voltage Into 2.5-kΩLoad V/V to ±10 V/V, and line outputs that have ±8 kV IEC
ESD protection. The DRV603 (occasionally referred
– 2 Vrms With 3.3-V Supply Voltage to as the ‘603) has built-in shutdown control for
– 3 Vrms With 5-V Supply Voltage pop-free on/off control. The DRV603 has an external
• Differential Input and internal undervoltage detector that mutes the
output.
• External Undervoltage Mute
Using the DRV603 in audio products can reduce
APPLICATIONS component count considerably compared to
• PDP / LCD TV traditional methods of generating a 3-Vrms output. The
DRV603 does not require a power supply greater
• Blu-ray Disc™, DVD Players than 5 V to generate its 8.5-Vpp output, nor does it
• Home Theater in a Box require a split-rail power supply. The DRV603
• Set-Top Boxes integrates its own charge pump to generate a
negative supply rail that provides a clean, pop-free
ground biased 3-Vrms output.
The DRV603 is available in a 14-pin TSSOP.
If the low noise and trimmed dc-offset and external
undervoltage mute function are not beneficial in the
application, TI recommends the footprint compatible
DRV602.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DirectPath is a trademark of Texas Instruments.
3Blu-ray Disc is a trademark of Blu-ray Disc Association.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TAPACKAGE TRANSPORT MEDIA, QUANTITY
DRV603PW RAIL, 90
–40°C to 85°C Tape and reel, 2000
DRV603PWR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range
VALUE UNIT
Supply voltage, VDD to GND –0.3 to 5.5 V
VIInput voltage VSS – 0.3 to VDD + 0.3 V
RLMinimum load impedance > 600 Ω
EN to GND –0.3 to VDD +0.3 V
TJMaximum operating junction temperature range –40 to 150 °C
Tstg Storage temperature range –40 to 150 °C
ESD Electrostatic discharge, IEC ESD OUTL, OUTR ±8 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
POWER RATING(1) POWER RATING(1)
PACKAGE RθJC (°C/W) RθJA (°C/W) AT TA≤25°C AT TA≤70°C
TSSOP-14 (PW) 35 115(2) 870 mW 348 mW
(1) Power rating is determined with a junction temperature of 125°C. This is the point where performance starts to degrade and long-term
reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C
for best performance and reliability.
(2) These data were taken with the JEDEC high-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the RθJA is 185°C/W.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VDD Supply voltage DC supply voltage 3 3.3 5.5 V
VIH High-level input voltage EN 60 % of VDD
VIL Low-level input voltage EN 40 % of VDD
TAOperating free-air temperature 0 70 °C
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ELECTRICAL CHARACTERISTICS
TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 3 V to 5 V, input grounded, unity gain 1 mV
PSRR Power-supply rejection ratio VDD = 3 V to 5 V 88 dB
VOH High-level output voltage VDD = 3.3 V, RL= 2.5 kΩ3.1 V
VOL Low-level output voltage VDD = 3.3 V, RL= 2.5 kΩ–3.05 V
|IIH| High-level input current (EN) VDD = 5 V, VI= VDD 1 µA
|IIL| Low-level input current (EN) VDD = 5 V, VI= 0 V 1 µA
VDD = 3.3 V, no load, EN = VDD 11
IDD Supply current VDD = 5 V, no load, EN = VDD 12.5 mA
Shutdown mode, VDD = 3 V to 5 V 1
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA= 25°C, RL= 2.5 kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ(unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD = 1%, VDD = 3.3 V, f = 1 kHz 2.05
VOOutput voltage (outputs in phase) THD = 1%, VDD = 5 V, f = 1 kHz 3.01 Vrms
THD = 1%, VDD = 5 V, f = 1 kHz, RL= 100 kΩ3.1
THD+N Total harmonic distortion plus noise VO= 2 Vrms, f = 1 kHz 0.001%
Crosstalk VO= 2 Vrms, f = 1 kHz –100 dB
IOMaximum output current VDD = 3.3 V 20 mA
RIN Input resistor range 1 10 47 kΩ
Rfb Feedback resistor range 4.7 20 100 kΩ
Slew rate 4.5 V/μs
Maximum capacitive load 220 pF
VNNoise output voltage BW = 20 Hz to 22 kHz, A-weighted 6 μVrms
VO= 3 Vrms, THD+N = 0.1%, BW = 22 kHz,
SNR Signal-to-noise ratio 112 dB
A-weighted
GBW Unity-gain bandwidth 8 MHz
AVO Open-loop voltage gain 150 dB
Vuvp External undervoltage detection 1.25 V
External undervoltage detection
IHys 5μA
hysteresis current
fcp Charge pump frequency 225 450 675 kHz
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1
+INR
2
3
4
-INR
OUTR
SGND
5
6
7 8
EN
PVSS
CN
9
10
11
12
13
14
CP
PVDD
PGND
OUTL
-INL
+IN
ChargePump
UVP
External
Under
Voltage
Detector
DRV603
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PW PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN I/O(1) DESCRIPTION
NAME NO.
+INR 1 I Right-channel OPAMP positive input
–INR 2 I Right-channel OPAMP negative input
OUTR 3 O Right-channel OPAMP output
SGND 4 P Signal ground
EN 5 I Enable input, active-high
PVSS 6 P Supply voltage
CN 7 I/O Charge-pump flying capacitor negative terminal
CP 8 I/O Charge-pump flying capacitor positive terminal
PVDD 9 P Positive supply
PGND 10 P Power ground
UVP 11 I Undervoltage protection input
OUTL 12 O Left-channel OPAMP output
–INL 13 I Left-channel OPAMP negative input
+INL 14 I Left-channel OPAMP positive input
(1) I = input, O = output, P = power
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Click&Pop
Suppression
ShortCircuit
Protection
SGND
Bias
Circuitry
PVSS
CN CP
PVDD
-INR
+INR
OUTL
-INL
OUTR
+INL
EN PGND
UVP
Line
Driver
Line
Driver
DRV603
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FUNCTIONAL BLOCK DIAGRAM
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100m 5200m 300m 500m 800m 2 3 4
V -OutputVoltage-V
O
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
100m 5200m 500m 800m 2 3 4
V -OutputVoltage-V
O
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
100m 5200m 500m 800m 2 3 4
V -OutputVoltage-V
O
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
100m 5200m 500m 800m 2 3 4
V -OutputVoltage-V
O
DRV603
SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
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TYPICAL CHARACTERISTICS
VDD = 3.3 V , TA= 25°C, RL= 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ(unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
VDD = 3.3 V, RL= 100 kΩ, f = 1 kHz VDD = 5 V, RL= 100 kΩ, f = 1 kHz
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
VDD = 3.3 V, RL= 2.5 kΩ, f = 1 kHz VDD = 5 V, RL= 600 Ω, f = 1 kHz
Figure 3. Figure 4.
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20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
0.0001
10
0.001
0.01
0.1
1
THD+N-TotalHarmonicDistortion+Noise-%
20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
-150
+150
-100
-50
+0
+50
+100
20 200k50 100 500 1k 2k 5k 10k 50k
f-Frequency-Hz
Phase-deg
0
+10
+1
+2
+3
+4
+5
+6
+7
+8
+9
20 200k
50 100 500 1k 2k 5k 10k 50k
f-Frequency-Hz
Gain-dBV
DRV603
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA= 25°C, RL= 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ(unless otherwise noted)
TOTAL HARMONIC DISTORTION+NOISE TOTAL HARMONIC DISTORTION+NOISE
vs vs
FREQUENCY FREQUENCY
VDD = 3.3 V, RL= 2.5 kΩ, VO= 2 Vrms VDD = 5 V, RL= 100 kΩ, VO= 2 Vrms
Figure 5. Figure 6.
PHASE GAIN
vs vs
FREQUENCY FREQUENCY
VDD = 5 V, RL= 100 kΩ, VO= 2 Vrms VDD = 5 V, RL= 100 kΩ, VO= 2 Vrms
Figure 7. Figure 8.
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-140
+0
-120
-100
-80
-60
-40
-20
0 20k5k 10k 15k
f-Frequency-Hz
FFT-dBr
DRV603
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA= 25°C, RL= 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ(unless otherwise noted)
FFT
vs QUIESCENT CURRENT
FREQUENCY vs
VDD = 5 V, RL= 100 kΩ, VO= 3 Vrms (-60 dB) SUPPLY VOLTAGE
Figure 9. Figure 10.
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OPAMP
Co
MuteCircuit
Output
Enable
+
+
+
-
ConventionalSolution
DRV603
MuteCircuit
Output
Enable
5 V
+
-
DRV603Solution
VDD
VSS
GND
VDD
VDD/2
GND
DirectPath
9-12V
DRV603
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APPLICATION INFORMATION
LINE DRIVER AMPLIFIERS
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 11
illustrates the conventional line-driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click
and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can
reduce the fidelity of the audio output signal.
Figure 11. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
Combining this with the built-in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc
blocking capacitors.
The bottom block diagram and waveform of Figure 11 illustrate the ground-referenced line-driver architecture.
This is the architecture of the DRV603.
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+
-
Inverting
RIN
RFB
+
-
CIN
-IN
Differential
Input
+IN
CIN RIN RFB
-IN
RIN
CIN
RFB
Rx
+
-
Cx
Non
Inverting
RIN
RFB
CIN
+IN
DRV603
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CHARGE PUMP FLYING CAPACITOR AND PVSS CAPACITOR
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are
smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications.
DECOUPLING CAPACITORS
The DRV603 is a DirectPath™ line-driver amplifier that requires adequate power supply decoupling to ensure
that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this
decoupling capacitor close to the DRV603 is important for the performance of the amplifier. For filtering
lower-frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also
help, but it is not required in most applications because of the high PSRR of this device.
GAIN-SETTING RESISTOR RANGES
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
DRV603 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR FEEDBACK RESISTOR DIFFERENTIAL INPUT NONINVERTING INPUT
INVERTING INPUT GAIN
VALUE, RIN VALUE, Rfb GAIN GAIN
22 kΩ22 kΩ1 V/V –1 V/V 2 V/V
15 kΩ30 kΩ1.5 V/V –1.5 V/V 2.5 V/V
33 kΩ68 kΩ2.1 V/V –2.1 V/V 3.1 V/V
10 kΩ100 kΩ10 V/V –10 V/V 11 V/V
Figure 12. Differential, Inverting and Non-Inverting Gain Configurations
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fcIN +1
2pRIN CIN CIN +1
2pfcIN RIN
or
--IN
DifferentialInput InvertingInput
DRV603
R1
R1
R2
R2
+
-
C3
C3
R3
R3 C1
C1
C2
R1
R2
+
-
C3 R3 C1
C2
+IN
-IN
DRV603
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INPUT-BLOCKING CAPACITORS
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV603. These capacitors block the dc portion of the audio source and allow the DRV603 inputs to be properly
biased to provide maximum performance.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1. Then the frequency and/or capacitance can be determined when one of the
two values is given.
(1)
USING THE DRV603 AS A SECOND-ORDER FILTER
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the DRV603, as it can be used like a standard OPAMP. Several filter topologies can be implemented, both
single-ended and differential. In Figure 13 , a multi-feedback (MFB) with differential input and single-ended input
is shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc-gain to 1, helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Figure 13. Second-Order Active Low-Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling capacitor. Using 5.6 kΩfor the resistors, C1 = 220 pF, and C2 = 470 pF, a DNR of
112 dB can be achieved with a 10-μF input ac-coupling capacitor.
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SupplyRamp
Supply
Enable
Timeforac-coupling
capacitorstocharge
R11
R12
R13
Cy
VSUP_MO
UVP pin11
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POP-FREE POWER UP
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power-supply ramp up and ramp
down. The SD pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the
SD pin high to achieve pop-less power up. Figure 14 illustrates the preferred sequence.
Figure 14. Power-Up Sequence
EXTERNAL UNDERVOLTAGE DETECTION
External undervoltage detection can be used to
mute/shut down the DRV603 before an input device
can generate a pop.
The shutdown threshold at the UVP pin is 1.25 V.
The user selects a resistor divider to obtain the
shutdown threshold and hysteresis for the specific
application. The thresholds can be determined as
follows:
VUVP = 1.25 V × (R11 + R12) / R12
Hysteresis = 5 μA × R13 × (R11 + R12) / R12
with the condition R13 >> R11//R12.
For example, to obtain VUVP = 5 V and 1-V
hysteresis, R11 = 3 kΩ,R12=1kΩand R13 = 50
kΩ.
CAPACITIVE LOAD
The DRV603 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ωor larger.
LAYOUT RECOMMENDATIONS
A proposed layout for the DRV603 can be seen in the DRV603EVM User's Guide (SLOU248), and the Gerber
files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/drv603evm.html. To access this
information, open the DRV603 product folder and look in the Tools and Software folder.
GAIN-SETTING RESISTORS
The gain-setting resistors, RIN and Rfb, must be placed close to the input pins to minimize capacitive loading on
these input pins and to ensure maximum stability of the DRV603. For the recommended PCB layout, see the
DRV603EVM user's guide (SLOU248).
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R3
+
C1
RIGHT
INPUT
+
-
LEFT
INPUT
LEFT
OUTPUT
RIGHT
OUTPUT
5 VSupply
C2
C1
R3
R2
R2
R1
R1
R3
+
-
C2 R3R1
R1
1mF
R2 C1
R2
C1
1mF
1mF
LinearLowDrop
Regulator
R11
R12
10mF
SystemSupply
C3
C3
C3
C3
+INL
-INL
OUTL
UVP
PGND
PVDD
CP
Line
Driver
Line
Driver
ShortCircuit
Protection
ClickandPop
Suppression
Bias
Circuitry
+INR
-INR
OUTR
SGND
EN
PVSS
CN
DRV603
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APPLICATION CIRCUIT
R1 = 5.6 kΩ, R2 = 5.6 kΩ, R3 = 5.6 kΩ, C1 = 220 pF, C2 = 470 pF
Differential-input, single-ended output, second-order filter
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REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision A (February 2009) to Revision B Page
• Changed Crosstalk spec from –80dB to –100dB ................................................................................................................. 3
• Added missing voltage value (1.25V) to External Undervoltage Detection threshold equation. ........................................ 12
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Changes from Revision B (October 2009) to Revision C Page
• Changed maximum operating junction temperature ............................................................................................................. 2
• In Dissipation Ratings section, changed θJx to RθJx in three places and 185°C to 185°C/W ............................................... 2
• Corrected reference to Figure 11 .......................................................................................................................................... 9
• Added cross-reference to Figure 13 ................................................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DRV603PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DRV603
DRV603PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DRV603
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
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I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DRV603PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV603PWR TSSOP PW 14 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 2
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
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