OPA2333A-Q1 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2333-Q1
SBOS463B –DECEMBER 2008–REVISED FEBRUARY 2020
OPA2333-Q1 Automotive, 1.8-V, Micropower, CMOS, Zero-Drift Operational Amplifier
1
1 Features
1• AEC qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
• Low offset voltage: 23 μV (Max)
• 0.01-Hz to 10-Hz noise: 1.1 μVPP
• Quiescent current: 17 μA
• Single-supply operation
• Supply voltage: 1.8 V to 5.5 V
• Rail-to-rail input/output
• Packages: 8-pin SOIC and VSSOP
2 Applications
•Pump
•Position sensor
•Vehicle occupant detection sensor
• Brake system
• Airbag
3 Description
The OPA2333-Q1 CMOS operational amplifiers use a
proprietary autocalibration technique to
simultaneously provide very low offset voltage (10 μV,
max), and near-zero drift over time and temperature.
These miniature high-precision low-quiescent-current
amplifiers offer high-impedance inputs that have a
common-mode range 100 mV beyond the rails and
rail-to-rail output that swings within 50 mV of the rails.
Single or dual supplies as low as 1.8 V (±0.9 V), and
up to 5.5 V (±2.75 V) can be used. This device is
optimized for low-voltage single-supply operation.
The OPA2333-Q1 offers excellent common-mode
rejection ratio (CMRR) without the crossover
associated with traditional complementary input
stages. This design results in superior performance
for driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
The OPA2333-Q1 is specified for operation from
–40°C to +125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
OPA2333-Q1 SOIC (8) 4.90 mm × 3.91 mm
VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
0.1-Hz to 10-Hz Noise
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: VS= 1.8 V to 5.5 V.......... 5
6.6 Typical Characteristics.............................................. 6
7 Detailed Description.............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8 Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Documentation Support ........................................ 16
11.2 Receiving Notification of Documentation Updates 16
11.3 Support Resources ............................................... 16
11.4 Trademarks........................................................... 16
11.5 Electrostatic Discharge Caution............................ 16
11.6 Glossary................................................................ 16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision A (June 2010) to Revision B Page
• Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions
table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Changed input offset voltage (over full temp range) from 22 µV to 15 µV in Electrical Characteristics table ...................... 5
• Added maximum value of 0.05 µV/°C to the VOS drift parameter in the Electrical Characteristics table ............................... 5
• Deleted Thermal resistance parameter from Electrical Characteristics table ....................................................................... 5
l TEXAS INSTRUMENTS
1OUT A 8 V+
2±IN A 7 OUT B
3+IN A 6 ±IN B
4V±5 +IN B
Not to scale
3
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5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 OUT A O Channel A output
2 –IN A I Channel A inverting input
3 +IN A I Channel A noninverting input
4 V– — Negative (lowest) supply voltage
5 +IN B I Channel B noninverting input
6 –IN B I Channel B inverting input
7 OUT B O Channel B output
8 V+ — Positive (highest) supply voltage
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short circuit to ground, one amplifier per package
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 7 V
VIInput voltage, signal input pins(2) –0.3 (V+) + 0.3 V
Output short-circuit(3) Continuous
TAOperating free-air temperature –40 125 °C
TJOperating virtual-junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2 ±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6 ±1000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VSSpecified supply voltage 1.8 5.5 V
TASpecified free-air temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
OPA2333-Q1
UNITD (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 124.0 180.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.7 48.1 °C/W
RθJB Junction-to-board thermal resistance 64.4 100.9 °C/W
ψJT Junction-to-top characterization parameter 18.0 2.4 °C/W
ψJB Junction-to-board characterization parameter 63.9 99.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
l TEXAS INSTRUMENTS
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(1) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
(2) See the Typical Characteristics section.
6.5 Electrical Characteristics: VS= 1.8 V to 5.5 V
At TA= 25°C, RL= 10 kΩconnected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS= 5 V 2 10 μV
VS= 5 V, TA= –40°C to +125°C 15 μV
dVOS/dTVOS drift VS= 5 V, TA= –40°C to 125°C 0.02 0.05 μV/°C
PSRR Power-supply rejection ratio VS= 1.8 V to 5.5 V,
TA= –40°C to +125°C 1 6 μV/V
Long-term stability(1) 1(1) µV
Channel separation, dc 0.1 μV/V
INPUT BIAS CURRENT
IBInput bias current ±70 ±200 pA
TA= –40°C to +125°C ±150 pA
IOS Input offset current ±140 ±400 pA
NOISE
Input voltage noise f = 0.01 Hz to 1 Hz 0.3 μVPP
f = 0.1 Hz to 10 Hz 1.1 μVPP
inInput current noise f = 10 Hz 100 fA/√Hz
INPUT VOLTAGE
VCM Common-mode supply voltage (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA= –40°C to +125°C 102 130 dB
INPUT CAPACITANCE
Differential 2 pF
Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 100 mV < VO< (V+) – 100 mV,
RL= 10 kΩ, TA= –40°C to +125°C 104 130 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL= 100 pF 350 kHz
SR Slew rate G = 1 0.16 V/μs
OUTPUT
Voltage output swing from rail RL= 10 kΩ30 50 mV
RL= 10 kΩ, TA= –40°C to +125°C 85 mV
ISC Short-circuit current ±5 mA
CLCapacitive load drive
(2)Open-loop output impedance f = 350 kHz, IO= 0 A 2 kΩ
POWER SUPPLY
IQQuiescent current per amplifier IO= 0 A 17 25 μA
IO= 0 A, TA= –40°C to +125°C 30 μA
Turn-on time VS= 5 V 100 μs
l TEXAS INSTRUMENTS E E _ F T r r r H r r r r Oflset anaqe 4w) D Offset Vonage Dnfl (“V/”Cr 120 250 MD 6 Frequency (sz Frequency (Hz) 120 3 Frequency (Hzr 1M OmDm Current (mm
PSRR (dB)
1
120
100
80
60
40
20
0
10k 100k1k10010
Frequency (Hz)
1M
+PSRR
−PSRR
Output Swing (V)
0
3
2
1
0
−1
−2
−3
1
Output Current (mA)
107 8 965432
−40°C
−40°C
−40°C
+25°C
+25°C
+25°C
+125°C
+125°C
VS=±2.75 V
VS=±0.9 V
CMRR (dB)
1
140
120
100
80
60
40
20
0
100k10k1k10010
Frequency (Hz)
1M
Population
0
0.0025
0.0050
0.0075
0.0100
0.0125
0.0150
0.0175
0.0200
0.0225
0.0250
0.0275
0.0300
0.0325
0.0350
0.0375
0.0400
0.0425
0.0450
0.0475
0.0500
Offset Voltage Drift (µV/°C)
Population
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Offset Voltage (µV)
6
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6.6 Typical Characteristics
At TA= 25°C, VS= 5 V, and CL= 0 pF (unless otherwise noted)
Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Production Distribution
Figure 3. Open-Loop Gain vs Frequency Figure 4. Common-Mode Rejection Ratio vs Frequency
Figure 5. Power-Supply Rejection Range vs Frequency Figure 6. Output Voltage Swing vs Output Current
l TEXAS INSTRUMENTS 100 CammonrMode Vanage 4V) 200 Temperamre cc) 125 Temperature 4°C} 125 ompuwnnage u V/dw) Tune (50 us’dw) ompuwnnage (so mV/dw) if? Twme (5 us’dlv) Twme150 us/dw)
Output Voltage (50 mV/div)
Time (5 µs/div)
G = +1
RL= 10 kΩ
2 V/div
0
1 V/div
0
Time (50 µs/div)
Input
Output
10 kW
1 kW
1/2
Device
–2.5 V
+2.5 V
IQ(µA)
−50
25
20
15
10
5
0
−25
Temperature (°C)
1251007550250
VS= 1.8 V
VS= 5.5 V
Output Voltage (1 V/div)
Time (50 µs/div)
G = 1
RL= 10 kΩ
IB(pA)
0
100
80
60
40
20
0
−20
−40
−60
−80
−100
1
Common-Mode Voltage (V)
5432
−IB
+IB
VS= 5 V
IB(pA)
−50
200
150
100
50
0
−50
−100
−150
−200
−25
Temperature ( )°C
1251007550250
VS= 5.5 V
VS= 1.8 V
−IB
−IB
+IB
+IB
7
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Typical Characteristics (continued)
At TA= 25°C, VS= 5 V, and CL= 0 pF (unless otherwise noted)
Figure 7. Input Bias Current vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature
Figure 9. Quiescent Current vs Temperature Figure 10. Large-Signal Step Response
Figure 11. Small-Signal Step Response Figure 12. Positive Over-Voltage Recovery
Voltage Noise (nV//Hz)
1
1000
100
10
Current Noise (fA//Hz)
1000
100
10
1k10010
Frequency (Hz)
10k
Current Noise
Voltage Noise
Continues with no 1/f (flicker) noise.
Overshoot (%)
10
40
35
30
25
20
15
10
5
0
100
Load Capacitance (pF)
1000
500 nV/div
1 s/div
Settling Time (µs)
1
600
500
400
300
200
100
0
10
Gain (dB)
100
0.001%
0.01%
4V Step
2 V/div
0
1 V/div
0
Time (50 µs/div)
Input
Output
10 kW
1 kW
+2.5 V
–2.5 V
1/2
Device
8
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Typical Characteristics (continued)
At TA= 25°C, VS= 5 V, and CL= 0 pF (unless otherwise noted)
Figure 13. Negative Over-Voltage Recovery Figure 14. Settling Time vs Closed-Loop Gain
Figure 15. Small-Signal Overshoot vs Load Capacitance Figure 16. 0.1-Hz to 10-Hz Noise
Figure 17. Current and Voltage Spectral Density vs Frequency
l TEXAS INSTRUMENTS em
5 k
(see Note)
W
1/2
OPA2333
10 mA max
+5 V
VIN
VOUT
IOVERLOAD
+IN
±IN
CHOP1 CHOP2
Notch
Filter GM2 GM3
OUT
GM_FF
GM1
C1
C2
9
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7 Detailed Description
7.1 Overview
The OPA2333-Q1 device is a zero-drift, low-power, rail-to-rail input and output operational amplifier. The device
operates from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low offset voltage and near-zero offset voltage drift.
The OPA2333-Q1 is unity-gain stable and free from unexpected output phase reversal. The device uses a
proprietary auto-calibration technique to provide low offset voltage and very low drift over time and temperature.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Rail-to-Rail Input Voltage
The OPA2333-Q1 input common-mode voltage range extends 0.1 V beyond the supply rails. The device is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers.
Normally, input bias current is approximately 70 pA; however, input voltages exceeding the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor (see Figure 18).
NOTE: A current-limiting resistor required if the input voltage exceeds the supply rails by ≥0.5 V.
Figure 18. Input Current Protection
7.3.2 Internal Offset Correction
The OPA2333-Q1 op amps use an auto-calibration technique with a time-continuous 350-kHz op amp in the
signal path. This amplifier is zero corrected every 8 μs using a proprietary technique. At power up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
7.4 Device Functional Modes
The OPA2333-Q1 has a single functional mode. The device is powered on as long as the power-supply voltage
is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
l TEXAS INSTRUMENTS
VOUT
Op Amp
V² = Ground
1/2
OPA2333
VIN
V+ = 5 V
ï5 V
Additional
Negative Supply
RP
20 k
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2333-Q1 is a unity-gain stable, precision operational amplifier with very low offset voltage drift. The
device is also free from output phase reversal. Applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
8.1.1 Achieving Output Swing to the Op Amp Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0 V,
near the lower output swing limit of a single-supply op amp. A good single-supply op amp may swing close to
single-supply ground, but does not reach ground. The output of the OPA2333-Q1 can be made to swing to
ground or slightly below on a single-supply power source. To do so requires the use of another resistor and an
additional, more negative, power supply than the op amp negative supply. A pulldown resistor may be connected
between the output and the additional negative supply to pull the output down below the value that the output
would otherwise achieve (see Figure 19).
Figure 19. VOUT Range to Ground
The OPA2333-Q1 has an output stage that allows the output voltage to be pulled to its negative supply rail, or
slightly below, using the technique previously described. This technique only works with some types of output
stages. The OPA2333-Q1 has been characterized to perform with this technique; however, the recommended
resistor value is approximately 20 kΩ.
NOTE
This configuration increases the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occurs below –2 mV, but
excellent accuracy returns as the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the op amp to swing even further below the negative rail. Resistances as low as 10 kΩcan be
used to achieve excellent accuracy down to –10 mV.
V+
ILOAD
A1
A2
Q1
Q2
+
+
+
±
VIN
RLOAD
RS1 IRS1
IRS2 IRS3
VRS2 VRS3
VRS1 VLOAD
V+
R5
330
R4
10 k
R2
10 k
RS2
470
RS3
4.7
R3
200
2 k
C7
2200 pF
C6
1000 pF
11
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8.2 Typical Application
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 20 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 21 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA333-Q1 device facilitate excellent dc accuracy for the circuit.
Figure 20. High-Side Voltage-to-Current (V-I) Converter
l TEXAS INSTRUMENTS 01
Input Voltage (V)
Output Current (A)
0 0.5 1 1.5
0
0.025
0.05
0.1
Load
0.075
2
D001
12
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Typical Application (continued)
8.2.1.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 5 V dc
• Input: 0 V to 2 V dc
• Output: 0 mA to 100 mA dc
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333-Q1 CMOS operational amplifier is a high-
precision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333-Q1 uses chopping techniques to provide low initial offset
voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in
the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2333-Q1 makes sure that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in the High-Side V-I
Converter reference design.
8.2.1.3 Application Curve
Figure 21. Measured Transfer Function for High-Side V-I Converter
1/2
OPA2333
ADS1100
Load
V
I2C
R1
4.99 k:
R3
4.99 k:
R4
48.7 k:
R2
49.9k:
5 V
3 V
REF3130
R7
1.18k:
RSHUNT
1:
R6
71.5k:RN
56 :
RN
56 :
(PGA Gain = 4)
FS = 3.0 V
Stray Ground-Loop Resistance
ILOAD
R1
VEX
VOUT
VREF
R1
1/2
OPA2333
R
R
R R
+5V
13
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Typical Application (continued)
8.2.1.4 Single Op Amp Bridge Amplifier
Figure 22 shows the basic configuration for a bridge amplifier.
Figure 22. Single Op-Amp Bridge Amplifier
8.2.1.5 Low-Side Current Monitor
A low-side current shunt monitor is shown in Figure 23. RNare operational resistors used to isolate the ADS1100
from the noise of the digital I2C bus. Because the ADS1100 is a 16-bit converter, a precise reference is essential
for maximum accuracy. If absolute accuracy is not required, and the 5-V power supply is sufficiently stable, the
REF3130 may be omitted.
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 23. Low-Side Current Monitor
*9 TEXAS INSTRUMENTS fi/Wx_
V1
ï
In
V2
+In
R1
R2
2
3
5
6
1
R2
1/2
OPA2333
VO
VO=(1 +2R2/R1) (V2ïV1)
1/2
OPA2333
OPA333
1/2
OPA2333
Output
RSHUNT
Load
V+
V+
RG
RL
R1(B)
10k:
RBIAS
+5V
zener(A)
Two zener
biasing methods
are shown.(C)
MOSFET rated to
standoff supply voltage
such as BSS84 for
up to 50 V.
14
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Typical Application (continued)
8.2.1.6 High-Side Current Monitor
Figure 24 shows the use case for a precision single-supply amplifier for a high-side current sensing circuit.
A. Zener rated for op amp supply capability (that is, 5.1 V for the OPA2333).
B. Current-limiting resistor.
C. Choose a Zener biasing resistor or dual NMOSFETs (FDG6301N, NTJD4001N, or Si1034).
Figure 24. High-Side Current Monitor
8.2.1.7 Precision Instrumentation Amplifier
Figure 25 shows a three op amp implementation for a high-CMRR instrumentation amplifier..
Figure 25. Precision Instrumentation Amplifier
‘5‘ TEXAS INSTRUMENTS Mace mmwuems mesa
NC
±IN
+IN
V±
V+
OUTPUT
NC
NC
VS+
VS±GND
Ground (GND) plane on another layer
VOUT
VIN
GND
Run the input traces
as far away from
the supply lines
as possible RF
RG
Place components close
to device and to each
other to reduce parasitic
errors
Use low-ESR,
ceramic bypass
capacitor
GND
Use a low-ESR,
ceramic bypass
capacitor
15
OPA2333-Q1
www.ti.com
SBOS463B –DECEMBER 2008–REVISED FEBRUARY 2020
Product Folder Links: OPA2333-Q1
Submit Documentation FeedbackCopyright © 2008–2020, Texas Instruments Incorporated
9 Power Supply Recommendations
The OPA2333-Q1 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages greater than 7 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors near the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more details on bypass capacitor placement, see the Layout section.
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The OPA2333-Q1 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring they are equal on
both input terminals. Other layout and design considerations include:
• Use low-thermoelectric-coefficient connections (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
10.2 Layout Example
Figure 26. Layout Example
l TEXAS INSTRUMENTS Am
16
OPA2333-Q1
SBOS463B –DECEMBER 2008–REVISED FEBRUARY 2020
www.ti.com
Product Folder Links: OPA2333-Q1
Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, ADS1100 Self-Calibrating, 16-Bit Analog-to-Digital Converter data sheet
• Texas Instruments, REF31xx 15ppm/°C Maximum, 100-μA, SOT-23 Series Voltage Reference data sheet
• Texas Instruments, INAx321 microPower, Single-Supply, CMOS Instrumentation Amplifier data sheet
• Texas Instruments, INA32x Precision, Rail-to-Rail I/O Instrumentation Amplifier data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA2333AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR OCOQ
OPA2333AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 02333Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF OPA2333-Q1 :
•Catalog: OPA2333
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA2333AQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
OPA2333AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2333AQDGKRQ1 VSSOP DGK 8 2500 367.0 367.0 38.0
OPA2333AQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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