ADS62C17 by Texas Instruments Datasheet

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1

FEATURES

DESCRIPTION

ADS62C17

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Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

•Programmable Gain up to 6dB for SNR/SFDRTrade-off•Maximum Sample Rate: 200 MSPS

•DC Offset Correction•11-bit Resolution with No Missing Codes

•Gain Tuning Capability in Fine Steps (0.001•90 dBc SFDR at Fin = 10 MHz

dB) Allows Channel-to-channel Gain Matching•79.8 dBFS SNR at 125 MHz IF, 20 MHz BW

•Supports Input Clock Amplitude Down to 400using TI proprietary SNRBoost technology

mV p-p Differential•Total Power 1.1 W at 200 MSPS

•Internal and External Reference Support•90 dB Cross-talk

•64-QFN Package (9 mm × 9 mm)•Double Data Rate (DDR) LVDS and ParallelCMOS Output Options

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and lowpower consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-widthcommunications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due toquantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digitalfunctions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gaintuning capability, each channel ’ s gain can be set independently to improve channel-to-channel gain matching.The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includesinternal references while the traditional reference pins and associated decoupling capacitors have beeneliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range ( – 40 ° C to 85 ° C).

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

‘5; TEXAS INSTRUMENTS Am

CONTROL

INTERFACE

INA_P

INA_M

CLKP

CLKM

VCM

SCLK

SEN

SDATA

AVDD

AGND

DRVDD

DRGND

14 bit

ADC

INB_P

INB_M

RESET

CTRL1

CTRL2

CTRL3

CLKOUTP/M

LVDS

INTERFACE

ADS62C17

DA0P/M

DA2P/M

DA4P/M

DA6P/M

DA8P/M

DA10P/M

DB0P/M

DB2P/M

DB4P/M

DB6P/M

DB8P/M

DB10P/M

14 bit

ADC

Digital

Processing

Block

Channel A

SNRBoost

Digital

Processing

Block

Channel B

11 bit

SDOUT

DDR

Serializer

DDR

Serializer

OUTPUT

CLOCK

BUFFER

SNRBoost

Sample

&

Hold

CLOCKGEN

REFERENCE

Sample

&

Hold

ADS62C17

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

Figure 1. ADS62C17 Block Diagram

PACKAGE/ORDERING INFORMATION

TRANSPORTPACKAGE- PACKAGE SPECIFIEDPRODUCT PACKAGE MARKING ORDERING NUMBER MEDIA,LEAD DESIGNATOR TEMPERATURE RANGE

QUANTITY

ADS62C17IRGCRADS62C17 QFN-64 RGC – 40 ° C to 85 ° C AZ62C17 Tape and ReelADS62C17IRGCT

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THERMAL CHARACTERISTICS

(1)

ABSOLUTE MAXIMUM RATINGS

(1)

ADS62C17

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over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS TYP UNIT

R

θJA

(2)

Soldered thermal pad, no airflow 22

Soldered thermal pad, 200 LFM 15 ° C/W

R

θJT

(3)

Bottom of package (thermal pad) 0.57

(1) With a JEDEC standard high K board and 5x5 via array. See Exposed Pad in the Application Information.(2) R

θJA

is the thermal resistance from the junction to ambient.(3) R

θJT

is the thermal resistance from the junction to the thermal pads.

VALUE UNIT

Supply voltage range AVDD -0.3 to 3.9

VSupply voltage range DRVDD – 0.3 to 2.2

Voltage between AGND and DRGND – 0.3 to 0.3

Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 to 3.3 V

Voltage between DRVDD to AVDD (when DRVDD leads AVDD) – 1.5 to 1.8

Voltage applied to external pin, VCM (in external refersnce mode) – 0.3 to 2.0

– 0.3V to minimumVoltage applied to analog input pins – INP_A, INM_A, INP_B, INM_B

V(3.6, AVDD + 0.3V)

Voltage applied to input pins – CLKP, CLKM

(2)

, RESET, SCLK, SDATA, SEN, CTRL1,

– 0.3V to ADD + 0.3VCTRL2, CTRL3

T

A

Operating free-air temperature range – 40 to 85 ° C

T

J

Operating junction temperature range 125 ° C

T

stg

Storage temperature range – 54 to 150 ° C

ESD, human body model 2 kV

(1) Stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operatingconditions ” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. Thisprevents the ESD protection diodes at the clock input pins from turning on.

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RECOMMENDED OPERATING CONDITIONS

(1)

ADS62C17

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MIN TYP MAX UNIT

SUPPLIES

AVDD Analog supply voltage 3.15 3.3 3.8 V

DRVDD Digital supply voltage 1.7 1.8 1.9 V

ANALOG INPUTS

Differential input voltage range 2 V

PP

Input common-mode voltage 1.5 ± 0.1 V

Voltage applied on CM in external reference mode 1.5 ± 0.05 V

Maximum analog input frequency with 2V pp input amplitude

(1)

500 MHz

Maximum analog input frequency with 1V pp input amplitude

(1)

800 MHz

CLOCK INPUT

Input clock sample rate 1 200 MSPS

Input Clock amplitude differential (V

CLKP

– V

CLKM

)

Sine wave, ac-coupled 0.2 3.0 V

PP

LVPECL, ac-coupled 1.6 V

PP

LVDS, ac-coupled 0.7 V

PP

LVCMOS, single-ended, ac-coupled 3.3 V

Input clock duty cycle 40% 50% 60%

DIGITAL OUTPUTS

C

L

Maximum external load capacitance from each output pin to DRGND 5 pF

R

L

Differential external load resistance between the LVDS output (LVDS interface) 100 Ω

T

A

Operating free-air temperature – 40 85 ° C

(1) See Theory of Operation in the application section.

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ELECTRICAL CHARACTERISTICS

(1)

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Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, – 1dBFSdifferential analog input, internal reference mode, LVDS and CMOS interfaces unless otherwise noted.Min and max values are across the full temperature range T

MIN

= – 40 ° C to T

MAX

= 85 ° C, AVDD = 3.3V, DRVDD = 1.8V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 11 bits

ANALOG INPUTS

Differential input voltage range 2.0 V

PP

Differential input resistance (at dc) See Figure 44 > 1 M Ω

Differential input capacitance See Figure 45 3.5 pF

Analog input bandwidth 700 MHz

Analog input common mode current (per channel) 3.6 µA/MSPS

VCM common mode voltage output 1.5 V

VCM output current capability ± 4 mA

POWER SUPPLY

IAVDD Analog supply current 262 mA

IDRVDD Output buffer supply current LVDS interface With 100 Ωexternal 120 mAtermination

IDRVDD Output buffer supply current CMOS interface No external load 87 mAcapacitance

Analog power 865 1025 mW

Digital power LVDS interface 216 306 mW

Global power down 45 75 mW

No missing codes Assured

DC ACCURACY

DNL Differential Non-Linearity Fin = 170 MHz -0.6 ± 0.2 0.6 LSB

INL Integral Non-Linearity Fin = 170 MHz -2.5 ± 0.75 2.5 LSB

Offset Error -20 ± 2 20 mV

Offset error temperature coefficient 0.02 mV/C

Offset error variation with supply 0.5 mV/V

There are two sources of gain error – internal reference inaccuracy and channel gain error

Gain error due to internal reference inaccuracy alone -1 ± 0.2 1 % FS

Gain error of channel alone

(2)

-1 +0.2 1 % FS

Channel gain error temperature coefficient 0.002 Δ%/ ° C

Difference in gain errorsbetween two channels -2 2within the same deviceGain matching

(3)

% FSDifference in gain errorsbetween two channels -4 4across two devices

(1) In CMOS interface, the DRVDD current scales with the sampling frequency and the load capacitance on output pins.(2) This is specified by design and characterization; it is not tested in production.(3) For two channels within the same device, only the channel gain error matters, as the reference is common for both channels.

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ELECTRICAL CHARACTERISTICS

ADS62C17

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Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, – 1dBFSdifferential analog input, internal reference mode, SNRBoost disabled, LVDS and CMOS interfaces unless otherwise noted.Min and max values are across the full temperature range T

MIN

= – 40 ° C to T

MAX

= 85 ° C, AVDD = 3.3V, DRVDD = 1.8V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Fin = 20 MHz 67Signal to noise ratio

Fin = 70 MHz 66.8

dBFSLVDS

Fin = 170 MHz 0 dB gain 64.5 66.3

6 dB gain 64.4

Table 1. SNR Enhancement With SNRBoost Enabled

SNRBoost bath-tub centered at Fsx0.25, – 1 dBFS input applied at Fin = 125MHz, Sampling frequency = 200MSPS

SNR Within Specified bandwidth, dBFS

Bandwidth, MHz In Default Mode ( SNRBoost Disabled) With SNRBoost Enabled

(1)

MIN TYP MAX MIN TYP MAX

5 78.8 79.6 83 85.6

10 75.8 76.6 80 82.6

15 74 74.9 78.2 80.9

20 72.7 73.6 77 79.6

30 71 71.9 74.4 76.4

40 69.8 70.6 72.7 74.5

(1) Using recommended SNRBoost coefficients. See note on SNRBoost in application section.

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ELECTRICAL CHARACTERISTICS

ADS62C17

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Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, – 1dBFSdifferential analog input, internal reference mode, SNRBoost disabled, 0dB gain, LVDS and CMOS interfaces unlessotherwise noted.Min and max values are across the full temperature range T

MIN

= – 40 ° C to T

MAX

= 85 ° C, AVDD = 3.3V, DRVDD = 1.8V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Fin= 20 MHz 66.9

Fin = 70 MHz 66.6SINAD

dBFSSignal to Noise and Distortion Ratio

0 dB gain 63.5 65.7Fin = 170 MHz

6 dB gain 64.2

Fin= 20 MHz 85

Fin = 70 MHz 83SFDR

dBcSpurious Free Dynamic Range

0 dB gain 73 78Fin = 170 MHz

6 dB gain 81

Fin= 20 MHz 83

Fin = 70 MHz 81THD

dBcTotal Harmonic Distortion

0 dB gain 71.5 75.5Fin = 170 MHz

6 dB gain 79

Fin= 20 MHz 94

Fin = 70 MHz 90HD2

dBcSecond Harmonic Distortion

0 dB gain 73 83Fin = 170 MHz

6 dB gain 92

Fin= 20 MHz 85

Fin = 70 MHz 83HD3

dBcThird Harmonic Distortion

0 dB gain 73 78Fin = 170 MHz

6 dB gain 81

Fin= 20 MHz 94Worst Spur

Fin = 70 MHz 92 dBcOther than second, third harmonics

Fin = 170 MHz 80 90

IMD

F1 = 185 MHz, F2 = 190 MHz, Each tone at – 7 dBFS 87 dBFS2-Tone Inter-modulation Distortion

Recovery to within 1% (of final value) for 6-dB overload with 1 clockInput Overload recovery

sine wave input at Fclk/4 cycles

Cross-talk Up to 200 MHz cross-talk frequency 90 dB

PSRR

For 100 mV pp signal on AVDD supply 25 dBAC Power Supply Rejection Ratio

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DIGITAL CHARACTERISTICS — ADS62C17

GNDGND

Logic0

V =-350mV*

ODL

Logic1

V =+350mV*

ODH

VOCM

DAnP /DBnP

DAnM/DBnM

*Withexternal100 terminationW

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The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logiclevel 0 or 1. AVDD = 3.3V, DRVDD = 1.8V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS – CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN

(1)

High-level input voltage 1.3All digital inputs support 1.8 V and 3.3 V CMOS

Vlogic levels.Low-level input voltage 0.4

SDATA, SCLK

(2)

V

HIGH

= 3.3 V 16High-level input current µASEN

(3)

V

HIGH

= 3.3 V 10

SDATA, SCLK V

LOW

= 0 V 0Low-level input current µASEN V

LOW

= 0 V – 20

Input capacitance 4 pF

DIGITAL OUTPUTS – CMOS INTERFACE (DA0-DA10, DB0-DB10, CLKOUT, SDOUT)

Ioh = 1mA DRVDD – DRVDDHigh-level output voltage V0.1

Low-level output voltage Iol = 1mA 0 0.1 V

Output capacitance (internal to device) 2 pF

DIGITAL OUTPUTS – LVDS INTERFACE (DA0P/M TO DA10P/M, DB0P/M TO DB10P/M, CLKOUTP/M)

VODH, High-level output differential voltage With external 100 Ωtermination +275 +350 +425 mV

VODL, Low-level output differential voltage With external 100 Ωtermination. – 425 – 350 – 275 mV

VOCM, Output common-mode voltage 1.0 1.15 1.40 V

Capacitance inside the device from each output 2 pFOutput Capacitance

to ground

(1) SCLK, SDATA, SEN function as digital input pins in serial configuration mode.(2) SDATA, SCLK have internal 200 k Ωpull-down resistor(3) SEN has internal 100 k Ωpull-up resistor to AVDD.

Figure 2. LVDS Output Voltage Levels

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TIMING CHARACTERISTICS — LVDS AND CMOS MODES

(1)

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Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, sine wave input clock, C

LOAD

=5pF

(2)

, R

LOAD

= 100 Ω

(3)

, no internal termination, LOW SPEED mode disabled, unless otherwise noted.Min and max values are across the full temperature range T

MIN

= – 40 ° C to T

MAX

= 85 ° C, AVDD = 3.3V, DRVDD = 1.7V to1.9V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

a

Aperture delay 0.7 1.2 1.7 ns

Aperture delay matching between two channels of the same device ± 50 ps

t

j

Aperture jitter 145 fs rms

Time to valid data after coming out of STANDBY mode 1 3

µsWake-up time Time to valid data after coming out of global powerdown 20 50

Time to valid data after stopping and restarting the input clock 10

Clock

cyclesADC Latency

(4)

Default, after reset 22

DDR LVDS MODE

(5)

t

su

Data setup time

(6)

Data valid

(7)

to zero-crossing of CLKOUTP 0.8 1.15 ns

t

h

Data hold time

(7)

Zero-crossing of CLKOUTP to data becoming invalid

(7)

0.8 1.15 ns

t

PDI

Clock propagation delay Input clock falling edge cross-over to output clock rising edge t

PDI

= 0.69 × Ts + t

delaycross-over

100 MSPS ≤Sampling frequency ≤200 MSPSt

delay

4.2 5.7 7.2 nsTs = 1/Sampling frequency

Difference in t

delay

between two devices operating at samet

delay

skew ± 500 pstemperature & SVDD supply voltage.

Duty cycle of differential clock, (CLKOUTP-CLKOUTM)LVDS bit clock duty cycle 52%100 MSPS ≤Sampling frequency ≤200 MSPS

Rise time measured from – 100 mV to +100 mVt

RISE

, t

FALL

Data rise time, Data fall time Fall time measured from +100 mV to – 100 mV 0.14 ns1MSPS ≤Sampling frequency ≤200 MSPS

Rise time measured from – 100 mV to +100 mVOutput clock rise time,t

CLKRISE

,

Fall time measured from +100 mV to – 100 mV 0.14 nst

CLKFALL

Output clock fall time

1 MSPS ≤Sampling frequency ≤200 MSPS

t

OE

Output buffer enable to data delay Time to valid data after output buffer becomes active 100 ns

PARALLEL CMOS MODE at Fs=200 MSPS

(8)

t

START

Input clock to data delay Input clock falling edge cross-over to start of data valid

(7)

2.5 ns

t

DV

Data valid time Time interval of valid data

(7)

1.7 2.7 ns

t

PDI

Clock propagation delay Input clock falling edge cross-over to output clock rising edge t

PDI

= 0.28 × Ts + t

delaycross-over

100 MSPS ≤Sampling frequency ≤150 MSPSt

delay

5.5 7.5 8.5 nsTs = 1/Sampling frequency

Duty cycle of output clock, CLKOUTOutput clock duty cycle 43100 MSPS ≤Sampling frequency ≤150 MSPS

Rise time measured from 20% to 80% of DRVDDt

RISE

, t

FALL

Data rise time, Data fall time Fall time measured from 80% to 20% of DRVDD 1.2 ns1≤Sampling frequency ≤200 MSPS

Rise time measured from 20% to 80% of DRVDDOutput clock rise time,t

CLKRISE

,

Fall time measured from 80% to 20% of DRVDD 0.8 nst

CLKFALL

Output clock fall time

1≤Sampling frequency ≤150 MSPS

Output buffer enable (OE) to datat

OE

Time to valid data after output buffer becomes active 100 nsdelay

(1) Timing parameters are ensured by design and characterization and not tested in production.(2) C

LOAD

is the effective external single-ended load capacitance between each output pin and ground(3) R

LOAD

is the differential load resistance between the LVDS output pair.(4) At higher frequencies, t

PDI

is greater than one clock period and overall latency = ADC latency + 1.(5) Measurements are done with a transmission line of 100 Ωcharacteristic impedance between the device and the load.Setup and hold time specifications take into account the effect of jitter on the output data and clock.(6) Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV.(7) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.(8) For Fs > 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).

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Table 2. LVDS Timings at Lower Sampling Frequencies

Setup Time, ns Hold Time, nsSampling Frequency, MSPS

MIN TYP MAX MIN TYP MAX

185 0.9 1.25 0.85 1.25

150 1.15 1.6 1.1 1.5

125 1.6 2 1.45 1.85

< 100 Enable LOW SPEED mode 2 2

t

PDI

, ns

1≤Fs ≤100 Enable LOW SPEED mode MIN TYP MAX

12.6

Table 3. CMOS Timings at Lower Sampling Frequencies

Timings Specified With Respect to Input Clock

Sampling Frequency, MSPS t

START

, ns Data Valid Time, ns

MIN TYP MAX MIN TYP MAX

190 1.9 2 3

170 0.9 2.7 3.7

150 6 3.6 4.6

Timings Specified With Respect to CLKOUT

Sampling Frequency, MSPS Setup Time, ns Hold Time, ns

MIN TYP MAX MIN TYP MAX

150 2.8 4.4 0.5 1.2

125 3.8 5.4 0.8 1.5

< 100 Enable LOW SPEED mode 5 1.2

t

PDI

, ns

1≤Fs ≤100 Enable LOW SPEED mode MIN TYP MAX

9

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OEOEOEOEOEEOEOEOEOE O

N

N-1 N+1

22 clock cycles *

INPUT

CLOCK

CLKOUTM

CLKOUTP

OUTPUT DATA

DXP, DXM

DDR

LVDS

N-22 N-21 N-20 N-19 N-

18 N-1 N N+1 N+2

22 clock cycles *

CLKOUT

OUTPUT DATA

D0:D10

PARALLEL

CMOS

INPUT

SIGNAL

Sample

N

N+1 N+2 N+3 N+4

tPDI

ta

E – Even bits D0, D2, D4...

O – Odd bits D1, D3, D5...

tPDI

CLKM

CLKP

N+2

N-22 N-21 N-20 N-19

N+22

N+23 N+24

CLKOUTMCLKOUTM

CLKOUTPCLKOUTP

Output

data pair

Output

data pair

tsu

Dn* Dn+1*

th

thtsu

tsu th

th

DAnP/M

DBnP/M

DAnP/M

DBnP/M

tPDI

CLKPCLKP

CLKMCLKM

Output

clock

Output

clock

Input

clock

Input

clock

*Dn – BitsD1,D3,D5...

*Dn+1 – Bits D0,D2,D4...

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Figure 3. Latency Diagram

Figure 4. LVDS Interface Timing

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CLKOUTCLKOUT

su

Dn*

CLKPCLKP

CLKMCLKM

CLKPCLKP

CLKMCLKM

InputClock

OutputClock

DAn,DBn

OutputData

InputClock

DAn,DBn

OutputClock

tPDI

tsu th

tSTART

tDV

Dn*

*Dn-BitsD0,D1,D2....ofchannel A andB

DEVICE CONFIGURATION

PARALLEL CONFIGURATION ONLY

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Figure 5. CMOS Interface Timing

ADS62C17 can be configured independently using either parallel interface control or serial interfaceprogramming.

To put the device in parallel configuration mode, keep RESET tied to high (AVDD).

Now, pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC.The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described inTable 3 to Table 6 . There is no need to apply reset and SDATA can be kept low.

In this mode, SEN and SCLK function as parallel interface control pins. Frequently used functions can becontrolled in this mode – Power down modes, internal/external reference, selection between LVDS/CMOSinterface and output data format.

Table 4 has a brief description of the modes controlled by the four parallel pins.

Table 4. PARALLEL PIN DEFINITION

PIN CONTROLS MODES

SCLK Analog control pins (controlled by analog Internal or External referencevoltage level, see Figure 5SEN LVDS/CMOS interface and Output DataFormat

CTRL1 Digital control pints (controlled by digital

Control SNRBoost, Standby and MUXlogic levels)CTRL2

mode.CTRL3

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SERIAL INTERFACE CONFIGURATION ONLY

USING BOTH SERIAL INTERFACE and PARALLEL CONTROLLS

DETAILS OF PARALLEL CONFIGURATION ONLY

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To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to bekept low.

SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internalregisters of the ADC.

The registers can be reset either by applying a pulse on RESET pin or by setting the < RESET > bit high. Theserial interface section describes the register programming and register reset in more detail.

For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pinsCTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltagesettings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used toaccess the internal registers of ADC. The registers must first be reset to their default values either by applying apulse on RESET pin or by setting bit < RST > = 1. After reset, the RESET pin must be kept low. The serialinterface section describes the register programming and register reset in more detail.

The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins isshown in Figure 6 .

Table 5. SCLK Control Pin

SCLK DESCRIPTION

0

Internal reference+200mV/-0mV

(3/8)AVDD External reference± 200mV

(5/8)2AVDD External reference± 200mV

AVDD Internal reference+0mV/-200mV

Table 6. SEN Control Pin

SEN DESCRIPTION

0 Offset binary and DDR LVDS output+200mV/-0mV

(3/8)AVDD 2 ’ s complement format and DDR LVDS output± 200mV

(5/8)2AVDD 2 ’ s complement format and parallel CMOS output± 200mV

AVDD Offset binary and parallel CMOS output+0mV/-200mV

Table 7. CTRL1, CTRL2 and CTRL3 Pins

CTRL1 CTRL2 CTRL3 DESCRIPTION

LOW LOW LOW Normal operation

LOW LOW HIGH SNRBoost enabled for Channel B

(1)

LOW HIGH LOW SNRBoost enabled for Channel A

(1)

LOW HIGH HIGH SNRBoost enabled for Channel A and B

(1)

HIGH LOW LOW Global power down

HIGH LOW HIGH Channel B standby

(1) To enable & disable SNRBoost mode using the CTRL pins, reset the register bits < SNRBoost Enable -CHA > = 0 & < SNRBoost Enable - CHB > = 0.

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l TEXAS INSTRUMENTS 40 of K )AVDD GED

(5/8)AVDD

(3/8)AVDD

GND AVDD

(5/8)AVDD

(3/8)AVDD

AVDD

GND

ToParallelPin

SERIAL INTERFACE

Register Initialization (when using serial interface only)

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

REGISTER ADDRESS REGISTERDATA

SDATA

SCLK

SEN

RESET

tSCLK tDSU tDH

tSLOADS tSLOADH

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Table 7. CTRL1, CTRL2 and CTRL3 Pins (continued)

CTRL1 CTRL2 CTRL3 DESCRIPTION

HIGH HIGH LOW Channel A standby

HIGH HIGH HIGH MUX mode of operation, Channel A and B data is multiplexed and outputon DA10 to DA0 pins.

Figure 6. Simple Scheme to Configure Parallel Pins

The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).

Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edgeof SCLK when SEN is active (low). The serial data is loaded into the register at every 16

th

SCLK falling edgewhen SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can beloaded in multiple of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can workwith SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK dutycycle.

After power-up, the internal registers MUST be initialized to their default values. This can be done in one of twoways:

1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 7

OR

2. By applying software reset. Using the serial interface, set the < RESET > bit (D7 in register 0x00) to HIGH. This initializes internalregisters to their default values and then self-resets the < RESET > bit to low. In this case the RESET pin is kept low.

Figure 7. Serial Interface Timing

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Serial Register Readout

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Typical values at 25 ° C, min and max values across the full temperature range T

MIN

= – 40C to T

MAX

= 85 ° C, AVDD = 3.3V,DRVDD = 1.8V, unless otherwise noted.

PARAMETER MIN TYP MAX UNIT

f

SCLK

SCLK frequency (= 1/ t

SCLK

) > DC 20 MHz

t

SLOADS

SEN to SCLK setup time 25 ns

t

SLOADH

SCLK to SEN hold time 25 ns

t

DS

SDATA setup time 25 ns

t

DH

SDATA hold time 25 ns

The device includes an option where the contents of the internal registers can be read back. This may be usefulas a diagnostic check to verify the serial interface communication between the external controller and the ADC.a. First, set register bit < SERIAL READOUT > = 1 to put the device in serial readout mode. This disables any further writes into theregisters, EXCEPT the register at address 0. Note that the < SERIAL READOUT > bit is also located in register 0. The device can exitreadout mode by writing < SERIAL READOUT > to 0. Also, only contents of register at adress 0 cannot be read in the register readoutmode.

b. Initiate a serial interface cycle specifying the address of the register (A7 – A0) whose content has to be read.

c. The device outputs the contents (D7 – D0) of the selected register on the SDOUT pin.

d. The external controller can latch the contents at the falling edge of SCLK.

e. To exit the serial readout mode, reset register bit < SERIAL READOUT > = 0, which enables writes into all registers of the device.

The serial register readout works with both CMOS and LVDS interfaces.

When < SERIAL READOUT > is disabled, SDOUT pin is forced low by the device (and not put inhigh-impedance). If serial readout is not used, SDOUT pin has to be floated.

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00 0 0 0 0 0 0 0 0 0 0 0 0 0 1

REGISTER ADDRESS (A7:A0) = 0x00 REGISTER DATA (D7:D0) = 0x01

SDATA

SCLK

SEN

A)Enableserialreadout(<SERIAL READOUT>=1)

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDATA

SCLK

SEN

SDOUT

B) Read contents of register 0x3F.

Thisregisterhasbeeninitializedwith0x04

(device is put in global power down mode)

REGISTER ADDRESS (A7:A0) = 0x3F REGISTER DATA (D7:D0 ) = XX (don’t care)

SDOUT 10 00000

Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1)

0

Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0)

RESET TIMING (WHEN USING SERIAL INTERFACE ONLY)

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Figure 8. Serial Readout

Typical values at 25 ° C, min and max values across the full temperature range T

MIN

= – 40 ° C to T

MAX

= 85 ° C, unless otherwisenoted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

t

1

Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 1 ns

t

2

Reset pulse width Pulse width of active RESET signal 10 ns

1

(1)

µs

t

3

Register write delay Delay from RESET disable to SEN active 100 ns

(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1usec, the device couldenter the parallel configuration mode briefly and then return back to serial interface mode.

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NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.For parallel interface operation, RESET has to be tied permanently HIGH.

Figure 9. Reset Timing Diagram

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Table 8. Summary of Functions Supported by Serial Interface

(1)

REGISTER

REGISTER FUNCTIONSADDRESS

A7 - A0

D7 D6 D5 D4 D3 D2 D1 D0IN HEX

< RESET >

< SERIAL00 0 0 0 0 0 0Software

READOUT >Reset

< ENABLE

LOW20 0 0 0 0 0 0 0SPEED

mode >

< REF >

< STAND3F 0 0 0 0 0BY >Internal or external reference

40 0 0 0 0 < POWER DOWN MODES >

< LVDS

CMOS >41 0 0 0 0 0 0 0Output

interface

44 < CLKOUT EDGE CONTROL > 0 0

< DATA FORMAT >< ENABLE50 0 INDEPENDENT 0 0 0 02s comp or offsetCHANNEL CONTROL >

binary

51 < CUSTOM PATTERN LOW > 0 0 0

52 0 0 < CUSTOM PATTERN HIGH >

< OFFSET CORRECTION53 0 ENABLE – Common/Ch 0A >

< GAIN PROGRAMMABILITY – Common/Ch A > < OFFSET CORRECTION TIME55

0 to 6 dB in 0.5 dB steps CONSTANT – Common/ Ch A >

56 < SNRBoost Coeff 1 – Common/ Ch A >< SNRBoost Coeff 2 – Common/ Ch A >

< FINE GAIN ADJUST – Common/ Ch A >57 0

+0.001 dB to +0.134 dB, in 128 steps

< SNRBoost

Enable –59 0 0 0 0 0 0 0

Common/ Ch A>

62 0 0 0 0 0 < TEST PATTERNS - Common/ Ch A >

63 0 0 < OFFSET PEDESTAL – Common/ Ch A >

< OFFSET CORRECTION66 0 0 0 0 0 0 0ENABLE – Ch B >

< GAIN PROGRAMMABILITY – Ch B > < OFFSET CORRECTION TIME68

0 to 6 dB in 0.5 dB steps CONSTANT – Ch B >

69 < SNRBoost Coeff 1 – Ch B > < SNRBoost Coeff 2 – Ch B >

< FINE GAIN ADJUST – Ch B >6A 0

+0.001 dB to +0.134 dB, in 128 steps

< SNRBoost6C 0 0 0 0 0 0 0

Enable – ChB >

75 0 0 0 0 0 < TEST PATTERNS - Ch B >

76 0 0 < OFFSET PEDESTAL – Ch B >

(1) Multiple functions in a register can be programmed in a single write operation.

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DESCRIPTION OF SERIAL REGISTERS

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

00 < RESET > 0 0 0 0 0 0 < SERIAL

READOUT >Software Reset

D7 < RESET >

1 Software reset applied – resets all internal registers and self-clears to 0.

D0 < SERIAL READOUT >

0 Serial readout disabled. SDOUT is forced high or low by the device (and not out in high impedancestate).

1 Serial readout enabled, Pin SDOUT functions as serial data readout. This mode is available only withCMOS output interface. With LVDS interface, pin 56 becomes CLKOUTM.

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

20 0 0 0 0 0 < ENABLE LOW 0 0SPEED MODE >

D2 < ENABLE LOW SPEED MODE >

0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS.

1 Enable LOW SPEED mode for sampling frequencies < = 100 MSPS.

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

3F 0 < REF > 0 0 0< STANDBY > 0

D6-D5 < REF > Internal or external reference selection

01 Internal reference enabled

11 External reference enabled

D1 < STANDBY >

0 Normal operation

1 ADC is powered down for both channels. Internal references, output buffers are active. This results inquick wake-up time from standby.

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

40 0 0 0 0 POWER DOWN MODES

D3-D0 < POWER DOWN MODES >

0000 Pins CTRL1, CTRL2 & CTRL3 determine power down modes.

1000 Normal operation

1001 Output buffer disabled for channel B

1010 Output buffer disabled for channel A

1011 Output buffer disabled for channel A and B

1100 Global power down

1101 Channel B standby

1110 Channel A standby

1111 Multiplexed mode, MUX – (only with CMOS interface)Channel A and B data is multiplexed and output on DA10 to DA0 pins.

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

41 < LVDS 0 0 0 0 00 0CMOS >

D7 < LVDS CMOS >

0 Parallel CMOS interface

1 DDR LVDS interface

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

44 < CLKOUT EDGE CONTROL > 0 0Output clock edge control

LVDS Interface

D7-D5 < CLKOUT POSN > Output clock rising edge position

000, 100 Default output clock position (refer to timing specification table)

101 Rising edge shifted by + (4/26)Ts

110 Rising edge aligned with data transition

111 Rising edge shifted by – (4/26)Ts

D4-D2 < CLKOUT POSN > Output clock falling edge position

000, 100 Default output clock position (refer to timing specification table)

101 Falling edge shifted by + (4/26)Ts

110 Falling edge aligned with data transition

111 Falling edge shifted by – (4/26)Ts

CMOS INterface

D7-D5 < CLKOUT POSN > Output clock rising edge position

000, 100 Default output clock position (refer to timing specification table)

101 Rising edge shifted by + (4/26)Ts

110 Rising edge shifted by – (6/26)Ts

111 Rising edge shifted by – (4/26)Ts

D4-D2 < CLKOUT POSN > Output clock falling edge position

000, 100 Default output clock position (refer to timing specification table)

101 Falling edge shifted by + (4/26)Ts

110 Falling edge shifted by – (6/26)Ts

111 Falling edge shifted by – (4/26)Ts

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

50 0 < ENABLE INDEPENDENT 0 0 0 < DATA FORMAT > 0CHANNEL CONTROL > 2s complement or offset binary 0

D6 < ENABLE INDEPENDENT CHANNEL CONTROL >

0Common control – both channels use common control settings for test patterns, offset correction,gain, gain correction and SNRBoost functions. These settings can be specified in a single set ofregisters.

1Independent control – both channels can be programmed with independent control settings for testpatterns, offset correction and SNRBoost functions. Separate registers are available for eachchannel.

D2-D1 < DATA FORMAT >

10 2s complement

11 Offset binary

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

51 < Custom Pattern Low > 00 0

52 0 0 < Custom Pattern High >

D7-D3 < CUSTOM LOW >

5 lower bits of custom pattern available at the output instead of ADC data

D5-D0 < CUSTOM HIGH >

6 upper bits of custom pattern available at the output instead of ADC data

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

53 0 < OFFSET CORRECTION ENABLE – 0 0 0 00 0Common/Ch A >Offset correction enable

D6 < OFFSET CORRECTION ENABLE – Common/Ch A >

Offset correction enable control for both channels ( with common control) or for channel A only ( withindependent control).

0 Offset correction disabled

1 Offset correction enabled

See Offset Correction

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

55 < GAIN PROGRAMMABILITY – Common/Ch A > < OFFSET CORR TIME CONSTANT – Common/Ch A >Offset correction time constant

D7-D4 < GAIN PROGRAMMABILITY – Common/Ch A >

Gain control for both channels (with common control) or for channel A only (with independentcontrol).

0000 0 dB gain, default after reset

0001 0.5 dB gain

0010 1.0 dB gain

0011 1.5 dB gain

0100 2.0 dB gain

0101 2.5 dB gain

0110 3.0 dB gain

0111 3.5 dB gain

1000 4.0 dB gain

1001 4.5 dB gain

1010 5.0 dB gain

1011 5.5 dB gain

1100 6.0 dB gain

D3-D0 < OFFSET CORR TIME CONSTANT – Common/Ch A >

Correction loop time constant in number of clock cycles.

Applies to both channels (with common control) or for channel A only (with independent control).

0000 256 k

0001 512 k

0010 1 M

0011 2 M

0100 4 M

0101 8 M

0110 16 M

0111 32 M

1000 64 M

1001 128 M

1010 256 M

1011 512 M

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

56 < SNRBoost Coeff 1 – Common/CH A > < SNRBoost Coeff 2 – Common/CH A >

See SNR enhancement using SNRBoost

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

57 0 < FINE GAIN ADJUST – Common/Ch A > +0.001 dB to +0.134 dB, in 128 steps

Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is onlyadditive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmedchannel gain is:

ΔChannel Gain = 20 × log10[1 + (FINE GAIN ADJUST/8192)]

Note that the total device gain = ADC gain + ΔChannel gain. The ADC gain is determined by register bits < GAINPROGRAMMABILITY>

A7 – A0 IN D7 D6 D5 D4 D3 D2 D1 D0HEX

59 0 0 0 0 0 0 0 < SNRBoost Enable – CH A >

D0 < SNRBoost Enable – CH A >

SNRBoost control for both channels ( with common control) or for channel A only ( with independentcontrol).

0 SNRBoost disabled

1 SNRBoost enabled

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

62 0 0 0 0 0 < TEST PATTERNS >

D2-D0 < TEST PATTERNS > Test Patterns to verify data capture.

Applies to both channels ( with common control) for channel A only ( with independent control)

000 Normal operation

001 Outputs all zeros

010 Outputs all ones

Outputs toggle pattern011

Output data < D10:D0 > alternates between 01010101010 and 10101010101 every clock cycle.

Outputs digital ramp100

Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047.

101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)

110 Unused

111 Unused

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

63 0 0 < OFFSET PEDESTAL – Common/Ch A >

D5-D0 < OFFSET PEDESTAL – Common/Ch A >

When the offset correction is enabled, the final converged value after the offset is corrected will bethe ADC mid-code value. A pedestal can be added to the final converged value by programmingthese bits. See " Offset Correction " in application section.

Applies to both channels ( with common control) or for channel A only ( with independent control).

011111 PEDESTAL = 31 LSB

011110 PEDESTAL = 30 LSB

011101 PEDESTAL = 29 LSB

....

000000 PEDESTAL = 0 LSB

....

111111 PEDESTAL = – 1 LSB

111110 PEDESTAL = – 2 LSB

....

100000 PEDESTAL = – 32LSB

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

66 0 < OFFSET CORRECTION ENABLE 0 0 0 0 0 0– CH B >Offset correction enable

D6 < OFFSET CORRECTION ENABLE – CH B >

Offset correction enable control for channel B ( only with independent control).

0 offset correction disabled

1 offset correction enabled

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

68 < GAIN PROGRAMMABILITY – CH B > < OFFSET CORR TIME CONSTANT – CH B >Offset correction time constant

D7-D4 < GAIN – CH B > Gain programmability in 0.5 dB steps

Applies to channel B ( only with independent control).

0000 0 dB gain, default after reset

0001 0.5 dB gain

0010 1.0 dB gain

0011 1.5 dB gain

0100 2.0 dB gain

0101 2.5 dB gain

0110 3.0 dB gain

0111 3.5 dB gain

1000 4.0 dB gain

1001 4.5 dB gain

1010 5.0 dB gain

1011 5.5 dB gain

1100 6.0 dB gain

D3-D0 < OFFSET CORR TIME CONSTANT – CH B > Time constant of correction loop in number of clockcycles.

Applies to channel B ( only with independent control)

0000 256 k

0001 512 k

0010 1 M

0011 2 M

0100 4 M

0101 8 M

0110 16 M

0111 32 M

1000 64 M

1001 128 M

1010 256 M

1011 512 M

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

69 < SNRBoost Coeff 1 – CH B > < SNRBoost Coeff 2 – CH B >

See SNR enhancement using SNRBoost

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

6A < GAIN CORRECTION – CH B > +0.001 dB to +0.134 dB, in 128 steps

Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is onlyadditive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmedchannel gain is:

ΔChannel Gain = 20 × log10[1 + (FINE GAIN ADJUST/8192)]

Note that the total device gain = ADC gain + ΔChannel gain. The ADC gain is determined by register bits < GAINPROGRAMMABILITY>

A7 – A0 IN D7 D6 D5 D4 D3 D2 D1 D0HEX

6C 0 0 0 0 0 00< SNRBoost Enable – CH B >

D0 < SNRBoost Enable – CH B >

SNRBoost control for channel B ( only with independent control).

0 SNRBoost disabled

1 SNRBoost enabled

A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

75 0 0 0 < TEST PATTERNS – CH B >

D2-D0 < TEST PATTERNS > Test Patterns to verify data capture

Applies to both channels ( with common control) for channel A only ( with independent control)

000 Normal operation

001 Outputs all zeros

010 Outputs all ones

Outputs toggle pattern011

Output data < D10:D0 > alternates between 01010101010 and 10101010101 every clock cycle.

Outputs digital ramp100

Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047.

101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)

110 Unused

111 Unused

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A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0

76 0 0 < OFFSET PEDESTAL – Common/Ch A >

D5-D0 < OFFSET PEDESTAL – Ch B >

When the offset correction is enabled, the final converged value after the offset is corrected will bethe ADC mid-code value. A pedestal can be added to the final converged value by programmingthese bits. See " Offset Correction " in application section.

Applies to both channels ( with common control) or for channel A only ( with independent control).

011111 PEDESTAL = 31 LSB

011110 PEDESTAL = 30 LSB

011101 PEDESTAL = 29 LSB

....

000000 PEDESTAL = 0 LSB

....

111111 PEDESTAL = – 1 LSB

111110 PEDESTAL = – 2 LSB

....

100000 PEDESTAL = – 32LSB

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PIN CONFIGURATION (LVDS INTERFACE) – ADS62C17

AGND

INP_B

NC

INM_A

AGND

CLKP

CLKM

CTRL 3

AVDD

CTRL 1

CTRL 2

AGND

AVDD

INM_B

AGND

INP_A

AGND

18 19 20 21 22 23 24 3130

2928272625

63 62 60 59 58 57 56 5052535455 51

64 61

2

3

4

5

6

7

9

10

8

11

12

13

14

15

1

16

36

35

34

48

47

46

45

44

43

42

41

40

39

38

37

32

DRVDD

DB4M

DB4P

DB6P

DB6M

DB8P

DB8M

DB10P

DB10M

SDATA

SCLK

RESET

SEN

AVDD

DRVDD

DA4P

DA2P

DA4M

DA0P

DA2M

DA0M

DRGND

DRVDD

DA6P

DA6M

CLKOUTP

CLKOUTM

DB0M

DB0P

SDOUT

DRGND

DA10M

DA10P

DA8M

DA8P

DRGND

DRVDD

DB2P

DB2M

NC

PAD(ConnectedtoDRGND)

VCM

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Figure 10. Pin Configuration

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PIN ASSIGNMENTS (LVDS INTERFACE) – ADS62C17

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PIN NO.

DESCRIPTIONOF

TYPENAME NUMBER

PINS

AVDD 16, 33, 34 3 I Analog power supply

AGND 17,18,21,24, 8 I Analog ground27,28,31,32

CLKP, CLKM 25, 26 2 I Differential clock input

INP_A, INM_A 29, 30 2 I Differential analog input, Channel A

INP_B, INM_B 19, 20 2 I Differential analog input, Channel B

VCM 23 1 IO Internal reference mode – Common-mode voltage output.

External reference mode – Reference input. The voltage forced on this pin sets theinternal references.

RESET 12 1 I Serial interface RESET input.

When using the serial interface mode, the user must initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin or by usingsoftware reset option. Refer to Serial Interface section.

In parallel interface mode, the user has to tie RESET pin permanently high. (SCLKand SEN are used as parallel control pins in this mode)

The pin has an internal 100 k Ωpull-down resistor.

SCLK 13 1 I This pin functions as serial interface clock input when RESET is low.

It controls selection of internal or external reference when RESET is tied high. SeeTable 5 for detailed information.

The pin has an internal 100 k Ωpull-down resistor.

SDATA 14 1 I Serial interface data input.

The pin has an internal 100 k Ωpull-down resistor.

The pin has no function in parallel interface mode and can be tired to ground.

SEN 15 1 I This pin functions as serial interface enable input when RESET is low.

It controls selection of data format and interface type when RESET is tied high.See Table 6 for detailed information.

The pin has an internal 100 k Ωpull-up resistor to AVDD

SDOUT 64 1 O This pin functions as serial interface register readout, when the < SERIALREADOUT > bit is enabled.

When < SERIAL READOUT > = 0, this pin forces logic LOW & is not tri-stated.

CTRL1 35 1 I

Digital control input pins. Together, they control SNRBoost control and power downCTRL2 36 1 I

modes.CTRL3 37 1 I

CLKOUTP 57 1 O Differential output clock, true

CLKOUTM 56 1 O Differential output clock, complement

DA0P, DA0M 2 O Differential output data pair, D0 and 0 multiplexed – Channel A

DA2P, DA2M 2 O Differential output data D1 and D2 multiplexed, true – Channel A

DA4P, DA4M 2 O Differential output data D3 and D4 multiplexed, true – Channel A

DA6P, DA6M 2 O Differential output data D5 and D6 multiplexed, true – Channel A

DA8P, DA8M 2 O Differential output data D7 and D8 multiplexed, true – Channel A

DA10P, DA10M 2 O Differential output data D9 and D10 multiplexed, true – Channel ARefer toFigure 10DB0P, DB0M 2 O Differential output data pair, D0 and 0 multiplexed – Channel B

DB2P, DB2M 2 O Differential output data D1 and D2 multiplexed, true – Channel B

DB4P, DB4M 2 O Differential output data D3 and D4 multiplexed, true – Channel B

DB6P, DB6M 2 O Differential output data D5 and D6 multiplexed, true – Channel B

DB8P, DB8M 2 O Differential output data D7 and D8 multiplexed, true – Channel B

DB10P, DB10M 2 O Differential output data D9 and D10 multiplexed, true – Channel B

DRVDD 1,38,48,58 4 I Output buffer supply

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PIN CONFIGURATION (CMOS INTERFACE) – ADS62C17

AGND

INP_B

NC

INM_A

AGND

CLKP

CLKM

UNUSED

DRVDD

CTRL 3

DB0

SDOUT

DRGND

DB 4

DB 5

DB 7

DB 6

DB 9

DB 8

DB10

DA10

DA8

DA9

DA3

DA4

DA1

DA2

DA0

AVDD

SDATA

SCLK

CTRL 1

CTRL 2

AGND

AVDD

INM_B

AGND

INP_A

AVDD

AGND

18 19 20 21 22 23 24 3130

2928272625

63 62 60 59 58 57 56 5052535455 51

64 61

2

3

4

5

6

7

9

10

8

11

12

13

14

15

1

16

36

35

34

48

47

46

45

44

43

42

41

40

39

38

37

DRGND

DRVDD

DRGND

DRVDD

DB3

DB2

DA7

DA6

32

NC

DA5

NC

DB1

NC

CLKOUT

PAD(ConnectedtoDRGND)

DRVDD

RESET

SEN

VCM

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

PIN NO.

DESCRIPTIONOF

TYPENAME NUMBER

PINS

DRGND 39,49,59,PAD 4 I Output buffer ground

NC Refer to Do not connectFigure 10

Figure 11. Pin Configuration

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PIN ASSIGNMENTS (CMOS INTERFACE) – ADS62C17

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

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PIN NO.

DESCRIPTIONOF

TYPENAME NUMBER

PINS

AVDD 16, 33, 34 3 I Analog power supply

AGND 17,18,21,24, 8 I Analog ground27,28,31, 32

CLKP, CLKM 25, 26 2 I Differential clock input

INP_A, INM_A 29, 30 2 I Differential analog input, Channel A

INP_B, INM_B 19, 20 2 I Differential analog input, Channel B

VCM 23 1 IO Internal reference mode – Common-mode voltage output.

External reference mode – Reference input. The voltage forced on this pin setsthe internal references.

RESET 12 1 I Serial interface RESET input.

When using the serial interface mode, the user MUST initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin or by usingsoftware reset option. Refer to SERIAL INTERFACE section.

In parallel interface mode, the user has to tie RESET pin permanently high.(SDATA and SEN are used as parallel control pins in this mode)

The pin has an internal 100 k Ωpull-down resistor.

SCLK 13 1 I This pin functions as serial interface clock input when RESET is low.

It controls selection of internal or external reference when RESET is tied high.See Table 5 for detailed information.

The pin has an internal 100 k Ωpull-down resistor.

SDATA 14 1 I Serial interface data input.

The pin has an internal 100 k Ωpull-down resistor.

The pin has no function in parallel interface mode and can be tired to ground.

SEN 15 1 I This pin functions as serial interface enable input when RESET is low.

It controls selection of data format and interface type when RESET is tied high.See Table 6 for detailed information.

The pin has an internal 100 k Ωpull-up resistor to AVDD

SDOUT 64 1 O This pin functions as serial interface register readout, when the < SERIALREADOUT > bit is enabled.

When < SERIAL READOUT > = 0, this pin forces logic LOW & is not tri-stated.

CTRL1 35 1 I

Digital control input pins. Together, they control SNRBoost control & power downCTRL2 36 1 I

modes.CTRL3 37 1 I

CLKOUT 57 1 O CMOS output clock

DA0, DA10 11 O Channel A 11-bit ADC output data bits, CMOS levelsRefer to Figure 11DB0-DB10 11 O Channel B 11-bit ADC output data bits, CMOS levels

DRVDD 1,38,48,58 4 I Output buffer supply

DRGND 39,49,59,PAD 3 I Output buffer ground

NC Refer to Figure 11 Do not connect

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TYPICAL CHARACTERISTICS

-140

-120

-100

-80

-60

-40

-20

0

0 10 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Amplitude-dB

Ain=-1dBFS,

SFDR=83.8dBc,

SNR=67dBFS,

SINAD=66.9dBFS,

THD=83.3dBc

-140

-120

-100

-80

-60

-40

-20

0

0 10 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Amplitude-dB

Ain=-1dBFS,

SFDR=83.6dBc,

SNR=66.8dBFS,

SINAD=66.8dBFS,

THD=83dBc

-140

-120

-100

-80

-60

-40

-20

0

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Amplitude-dB

Ain=-1dBFS,

SFDR=74.2dBc,

SNR=66.3dBFS,

SINAD=65.7dBFS,

THD=73.5dBc

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

FFT for 20 MHz INPUT SIGNAL

Figure 12.

FFT for 60 MHz INPUT SIGNAL

Figure 13.

FFT for 170 MHz INPUT SIGNAL

Figure 14.

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010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

Ain=-1dBFS,

SFDR=71.7dBc,

SNR=65.7dBFS,

SINAD=64.8dBFS,

THD=70.8dBc

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-7dBFSeachtone,

Fin1=185MHz,

Fin2=190MHz,

AMD3=87.5dBFS,

SFDR=90dBFS

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-35dBFSeachtone,

Fin1=185MHz,

Fin2=190MHz,

IMD3=107dBFS,

SFDR=104dBFS

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

FFT for 270 MHZ INPUT SIGNAL

Figure 15.

FFT for 2-TONE INPUT SIGNAL(INTERMODULATION DISTORTION)

Figure 16.

FFT for 2-TONE INPUT SIGNAL(INTERMODULATION DISTORTION)

Figure 17.

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-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-36dBFS,

SNRBoostCoeff1=0x0,

,

SFDR=51.8dBc,

THD=51dBc,

SNRover5MBW(47.5Mto52.5M) ,

SNRBoostCoeff2=0x0

=88.4dBFS

SNRover10MBW(45Mto55M)=84.5dBFS,

SNRover15MBW(42.5Mto57.5M)=82.5dBFS

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-36dBFS,

SNRBoostCoeff1=0xF,

,

SFDR=52dBc,

THD=52.8dBc,

SNRover20MBW(40Mto60M)

SNRBoostCoeff2=0x1

=80.9dBFS

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-36dBFS,

SNRBoostCoeff1=0xD,

,

SFDR=52.7dBc,

THD=53.1dBc,

SNRover30MBW(35Mto65M)

SNRBoostCoeff2=0x3

=78.4dBFS

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

FFT with SNRBOOST ENABLED

for5MHz, 10MHZ, and 15 MHz BANDWIDTHS, Fin = 150 MHz, Fcenter = Fs/4

Figure 18.

FFT with SNRBOOST ENABLED

for20 MHz BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4

Figure 19.

FFT with SNRBOOST ENABLED

for30MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4

Figure 20.

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-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

010 20 30 40 50 60 70 80 90 100

f-Frequency-MHz

Ain=-36dBFS,

SNRBoostCoeff1=0xD,

,

SFDR=54.4dBc,

THD=53.8dBc,

SNRover40MBW(30Mto70M)

SNRBoostCoeff2=0x3

=75.8dBFS

78

80

82

84

86

88

90

SNR

(37.5Mto42.5M)

SNR

(42.5Mto47.5M)

SNR

(47.5Mto52.5M)

SNR

(52.5Mto57.5M)

SNR

(57.5Mto62.5M)

SNR-dBFS

SNRBoostEnabled

SNRBoostDisabled

Ain=-36dBFS,

Fin=150.2MHz,

,

Optimizedfor20MHzBandwidth,

SNRover20MBW(SNRBoostDisabled) ,

SNRBoostCoeff2=0x1

=73.7dBFS

SNRover20MBW( )=80.9dBFSSNRBoostEnabled

66

70

74

78

82

86

90

0 100 200 300 400 500

InputFrequency-MHz

SFDR-dBc

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

FFT with SNRBOOST ENABLED

for40MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4

Figure 21.

SNR with SNRBOOST ENABLEand DISABLED SFDR ACROSS INPUT FREQUENCY

Figure 22. Figure 23.

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63

64

65

66

67

68

0 100 200 300 400 500

InputFrequency-MHz

SNR-dBFS

68

72

76

80

84

88

92

0 100 200 300 400 500

InputFrequency-MHz

Gain=0dB

Gain=2dB

Gain=5dB

Gain=6dB

Gain=3dB

Gain=4dB

SFDR-dBc

Gain=1dB

62

63

64

65

66

67

68

0 50 100 150 200 250 300 350 400 450

InputFrequency-MHz

Gain=0dB

Gain=1dB

Gain=2dB

Gain=3dB

Gain=4dB

Gain=6dB

500

SINAD-dBFS

Gain=5dB

40

50

60

70

80

90

100

-40 -35 -30 -25 -20 -15 -10 -5 0

65

65.5

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

SFDR-dBc

Input Amplitude-dBFs

SNR-dBFS

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

SNR ACROSS INPUT FREQUENCY SFDR ACROSS GAIN

Figure 24. Figure 25.

PERFORMANCE ACROSS INPUT AMPLITUDESINAD SCROSS GAIN SINGLE TONE

Figure 26. Figure 27.

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80

81

82

83

84

85

86

1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7

InputCommonModeVoltage-V

65

65.5

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

SFDR-dBc

SNR-dBFS

InputFrequency=60

82

86

90

94

98

102

106

110

-7 -12 -18 -24 -30 -36 -42 -48

Input Amplitudeofeachtone-dBFS

SFDR-dBFS

IMD3,SFDR,dBFS

IMD3-dBFS

65.5

66

66.5

67

67.5

-40 -25 25 55 85

AVDD=3V

AVDD=3.3V

AVDD=3.6V

SNR-dBFS

T -Free-AirTemperature-°C

A

InputFrequency=60MHz

82

83

84

85

86

87

88

89

90

-40 -25 25 55 85

AVDD=3V

AVDD=3.3V

AVDD=3.6V

InputFrequency=60MHz

SFDR-dBc

T -Free-AirTemperature-°C

A

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

INTER-MODULATION with 2-TONE INPUT PERFORMANCE ACROSS INPUTACROSS INPUT AMPLITUDE COMMON-MODE VOLTAGE

Figure 28. Figure 29.

SFDR ACROSS TEMPERATURE SNR ACROSS TEMPERATUREvs vsAVDD SUPPLY AVDD SUPPLY

Figure 30. Figure 31.

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l TEXAS INSTRUMENTS SNR - dBFS

83

84

85

86

87

1.6 1.7 1.8 1.9

DRVDD-SupplyVoltage-V

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

InputFrequency=60MHz,

AVDD=3.3V

SFDR-dBc

SNR,dBFS

81

82

83

84

85

InputClock Amplitude,V Differential

PP

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

SFDR-dBc

SNR,dBFS

0.11 0.31 0.52 0.73 0.94 1.15 1.36 1.57 1.77 1.97 2.15

InputFrequency=60MHz

82

83

84

85

86

1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7

VoltageForcedonVCMPin-V

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

SFDR-dBc

85

86

87

88

89

30 35 40 45 50 55 60 65 70

InputClockDutyCycle-%

66

66.5

67

67.5

68

SFDR-dBc

SNR-dBFS

InputFrequency=20MHz

SFDR-dBc

SNR,dBFS

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

PERFORMANCE ACROSS PERFORMANCE ACROSSDRVDD SUPPLY VOLTAGE INPUT CLOCK AMPLITUDE

Figure 32. Figure 33.

PERFORMANCEPERFORMANCE ACROSS ACROSSINPUT CLOCK DUTY CYCLE EXTERNAL REFERENCE MODE

Figure 34. Figure 35.

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0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

025 50 75 100 125 150 175 200

Samplingfrequency-MSPS

TotalPower-W

CMOS

(NoloadCapacitance)

LVDS

-70

-65

-60

-55

-50

-45

-40

-35

-30

20 40 60 80 100 130 170 230 270

Common-ModeFrequency-MHz

CMRR-dB

0.4

20.4

60.4

80.4

100.4

120.4

140.4

0 25 50 75 100 125 150 175 200

SamplingFrequency-MSPS

40.4

DRVDDCurrent-mA

Fin=2.5MHz

CMOS15pF

LoadCapacitance

LVDS

CMOS

NoloadCapacitance

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

CMRR

vs POWER DISSIPATION ACROSSFREQUENCY SAMPLING FREQUENCY

Figure 36. Figure 37.

DRVDD CURRENT ACROSSSAMPLING FREQUENCY

Figure 38.

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200

180

160

140

120

100

80

20 50 100 150 200 250 300 350 400 450 500

70 75 80 85 90 95

SamplingFrequency-MSPS

200

180

160

140

120

100

80

SamplingFrequency-MSPS

6560

100 200 300 400 500 600 700 800

70 75 80 85 90

20

ADS62C17

www.ti.com

............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

SFDR CONTOUR

0 dB GAINup to 500 MHz

Figure 39.

SFDR CONTOUR

6 dB GAINup to 800 MHz

Figure 40.

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I TEXAS INSTRUMENTS 53 63.5 65.5 66 66.5 51 60 50.5 61 61.5 62 62.5 63 63.5 64 54.5 65 65.5

200

180

160

140

120

100

80

20 50 100 150 200 250 300 350 400 450 500

63 64 65 66 67

SamplingFrequency-MSPS

63.5 64.5 65.5 66.5

200

180

160

140

120

100

80

SamplingFrequency-MSPS

60 60.5

100 200 300 400 500 600 700 800

61 62 63 64 65

20

61.5 62.5 63.5 65.564.5

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, SNRBoost disabled, internal referencemode, 0 dB gain, LVDS output interface (unless otherwise noted)

SNR CONTOUR

0 dB GAINup to 500 MHz

Figure 41.

SNR CONTOUR

6 dB GAINup to 800 MHz

Figure 42.

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APPLICATION INFORMATION

THEORY OF OPERATION

ANALOG INPUT

INP

INM

10 W

RCRFilter

Sampling

capacitor

Sampling

switch

Sampling

switch

Ron

15 W

Ron

100 W

3pF

Lpkg~ 2 nH Sampling

capacitor

Ron

10 W

Lpkg~ 2 nH

C

~1pF

bond

R

200 W

R

200 W

C

~1pF

bond

3pF

100 W

C2

0.5pF

C1

0.25pF

C2

0.5pF

15 W

C

2pF

samp

C

2pF

samp

10 W

Drive Circuit Requirements

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

ADS62C17 is a low power 11-bit pipeline A/D converters with maximum sampling rate up to 200 MSPS.

At every falling edge of the input clock, the analog input signal of each channel is sampled simultaneously. Thesampled signal in each channel is converted by a pipeline of low resolution stages. In each stage, the sampledand held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between thestage input and its quantized equivalent is gained and propagates to the next stage. At every clock, eachsucceeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages arecombined in a digital correction logic block and processed digitally to create the final 11 bit code, after a datalatency of 22 clock cycles.

The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary orbinary 2s complement format.

The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with2V pp amplitude) and about 800MHz (with 1V pp amplitude).

The analog input consists of a switched-capacitor based differential sample and hold architecture.

This differential topology results in very good AC performance even for high input frequencies at high samplingrates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available onVCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically betweenVCM + 0.5V and VCM – 0.5V, resulting in a 2Vpp differential input swing.

Figure 43. Analog Input Circuit

For optimum performance, the analog inputs must be driven differentially. This improves the common-modenoise immunity and even order harmonic rejection. A 5 Ωto 15 Ωresistor in series with each input pin isrecommended to damp out ringing caused by package parasitic.

SFDR performance can be limited due to several reasons - the effect of sampling glitches (described below),non-linearity of the sampling circuit & non-linearity of the quantizer that follows the sampling circuit.

Depending on the input frequency, sample rate & input amplitude, one of these plays a dominant part in limitingperformance.

At very high input frequencies (> about 300 MHz), SFDR is determined largely by the device ’ s sampling circuitnon-linearity. At low input amplitudes, the quantizer non-linearity usually limits performance.

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0.01

0.10

1

10

100

0 100 200 300 400 500 600 700 800 900 1000

f-Frequency-MHz

Resistance-kW

ADS62C17

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Glitches are caused by the opening & closing of the sampling switches. The driving circuit should present a lowsource impedance to absorb these glitches. Otherwise, this could limit performance, mainly at low inputfrequencies (up to about 200 MHz). It is also necessary to present low impedance ( < 50 Ω) for the commonmode switching currents. This can be achieved by using two resistors from each input terminated to the commonmode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb thesampling glitches inside the device itself. The cut-off frequency of the R-C filter involves a trade-off.

A lower cut-off frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the otherhand, with a higher cut-off frequency (smaller C), bandwidth support is maximized. But now, the samplingglitches need to be supplied by the external drive circuit. This has limitations due to the presence of the packagebond-wire inductance.

In ADS62C17, the R-C component values have been optimized while supporting high input bandwidth (up to 700MHz). However, in applications with input frequencies up to 200-300MHz, the filtering of the glitches can beimproved further using an external R-C-R filter (as shown in Figure 46 and Figure 47 ).

In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over thedesired frequency range and matched impedance to the source. While doing this, the ADC input impedancemust be considered. Figure 44 and Figure 45 show the impedance (Zin = Rin || Cin) looking into the ADC inputpins.

Figure 44. ADC Analog Input Resistance (Rin) Across Frequency

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1

1.5

2

2.5

3

3.5

4

4.5

0 100 200 300 400 500 600 700 800 900 1000

f-Frequency-MHz

Capacitance-pF

Driving Circuit

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Figure 45. ADC Analog Input Capacitance (Cin) Across Frequency

Two example driving circuit configurations are shown in Figure 46 and Figure 47 – one optimized for lowbandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies.

In Figure 46 , an external R-C-R filter using 22pF has been used. Together with the series inductor (39nH), thiscombination forms a filter and absorbs the sampling glitches. Due to the large capacitor (22pF) in the R-C-R andthe 15 Ωresistors in series with each input pin, the drive circuit has low bandwidth and supports low inputfrequencies ( < 100MHz).

To support high input frequencies (up to about 300MHz, see Figure 47 ), the capacitance used in the R-C-R isreduced to 3.3pF and the series inductors are shorted out. Together with the lower series resistors (5 Ω), thisdrive circuit provides high bandwidth and supports high input frequencies.

Transformers such as ADT1-1WT or ETC1-1-13 can be used up to 300MHz.

Without the external R-C-R filter, the drive circuit has very high bandwidth & can support very high inputfrequencies (> 300MHz). For example, a transmission line transformer such as ADTL2-18 can be used(Figure 48 ).

Note that both the drive circuits have been terminated by 50 ohms near the ADC side. The termination isaccomplished by a 25 ohms resistor from each input to the 1.5V common-mode (VCM) from the device. Thisallows the analog inputs to be biased around the required common-mode voltage.

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INP

INM

VCM

1:1

15 W

0.1uF

1:1

22 pF

25 W

50 W

39 nH

0.1 Fm

50 W

25 W

15 W

50 W

INP

INM

VCM

1:1 1:1

3.3 pF

0.1 Fm

0.1 Fm25 W

25 W

5W

50 W

INP

INM

VCM

0.1 Fμ 25 Ω

25 Ω

0.1 Fμ

T1 T2

ADS62C17

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Figure 46. Drive Circuit With Low Bandwidth (for low input frequencies)

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-orderharmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch andgood performance is obtained for high frequency input signals. An additional termination resistor pair may berequired between the two transformers as shown in the figures. The center point of this termination is connectedto ground to improve the balance between the P and M sides. The values of the terminations between thetransformers and on the secondary side have to be chosen to get an effective 50 Ω(in the case of 50 Ωsourceimpedance).

Figure 47. Drive Circuit With High Bandwidth (for high input frequencies)

Figure 48. Drive circuit with very high bandwidth (> 300 MHz)

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PETE

INP

INM

VCM

1:4

5 Ω

0.1 Fμ

5 Ω

100 Ω

25 Ω

15pF72nH

Differential

input signal

Input common-mode

REFERENCE

_

+

_

+

INTERNAL

REFERENCE

INTREF

EXTREF

REFM

REFP

VCM

Internal reference

ADS62C17

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All these examples show 1:1 transformers being used with a 50 ohms source. As explained in the "Drive CircuitRequirements", this helps to present a low source impedance to absorb the sampling glitches. With a 1:4transformer, the source impedance will be 200 ohms. The higher impedance can lead to degradation inperformance, compared to the case with 1:1 transformers. For applications where only a band of frequencies areused, the drive circuit can be tuned to present a low impedance for the sampling glitches. Figure 49 shows anexample with 1:4 transformer, tuned for a band around 150MHz.

Figure 49. Drive circuit with 1:4 transformer

To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1 µF low-inductance capacitorconnected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADCsinks a common-mode current in the order of 3.6 µA / MSPS (about 720 µA at 200 MSPS).

ADS62C17 has built-in internal references REFP and REFM, requiring no external components. Design schemesare used to linearize the converter load seen by the references; this and the on-chip integration of the requisitereference capacitors eliminates the need for external decoupling. The full-scale input range of the converter canbe controlled in the external reference mode as explained below. The internal or external reference modes canbe selected by programming the serial interface register bit < REF>.

Figure 50. Reference Section

When the device is in internal reference mode, the REFP and REFM voltages are generated internally.Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analoginput pins

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External reference

SNR ENHANCEMENT USING SNRBOOST

-140

-120

-100

-80

-60

-40

-20

0

Amplitude-dB

00.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

f-Frequency-MHz

CenterFrequency

=FSx0.25

Fs=200MSPS

Fin=150MHz

SNRBoostCoeff1=0x0F,

SNRBoostCoeff2=0x01,

ADS62C17

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When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on theVCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differentialinput voltage corresponding to full-scale is given by the following:

Full-scale differential input pp = (Voltage forced on VCM) × 1.33

In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.

SNRBoost technology makes it possible to overcome SNR limitations due to quantization noise. With SNRBoost,enhanced SNR can be obtained for any bandwidth (less than Nyquist or Fs/2, see Table 1 ). The SNRimprovement is achieved without affecting the default harmonic performance. SNRBoost is disabled after reset; itcan be enabled using register bit < SNRBoost Enable> or using the control pins CTRL1, 2, 3.

(While using the register bits to control SNRBoost, keep CTRL1, CTRL2, CTRL3 low. To use the CTRL pins asSNRBoost control, reset the < SNRBoost Enable> register bits).

When it is enabled, the noise floor in the spectrum acquires a typical bath-tub shape as shown in Figure 51 . Thebath-tub is centered around a specific frequency (called center frequency). The center frequency is locatedmid-way between two corner frequencies, which are specified by the SNRBoost coefficients (Register bits< SNRBoost Coeff1> and SNRBoost Coeff2>).

Table 9 shows the relation between each coefficient and its corner frequency. By choosing appropriatecoefficients, the bath-tub can be positioned over the frequency range 0 to Fs/2 (Table 10 shows someexamples). By positioning the bath-tub within the desired signal band, SNR improvement can be achieved (seeTable 1 ). Note that as the bandwidth is increased, the amount of SNR improvement reduces.

Figure 51. Specturm with SNRBoost Enabled

Table 9. Setting the Corner Frequency

SNRBoost Coefficient Value Normalized Corner Frequency SNRBoost Coefficient value Normalized Corner Frequency(f/fs) (f/fs)

7 0.420 F 0.230

6 0.385 E 0.210

5 0.357 D 0.189

4 0.333 C 0.167

3 0.311 B 0.143

2 0.290 A 0.115

1 0.270 9 0.080

0 0.250 8 0.000

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l TEXAS INSTRUMENTS \ h—H data slzns

A7 A6 A1 A0 D7 D6 D1 D0

Register address = 0x59 Register data = 0x01

SDATA

SCLK

SEN

CLKM

CLKP

N-26

Output

Data

clock

cycle 1

clock

cycle 9

clock

cycle 10

N-25

Serial register write to enable SNRBoost

10 clock cycles after the 16th SCLK

falling edge, the device starts

giving out valid SNRBoost data

Valid SNRBoost

data starts

N-1

NN+1

Analog

Input

Signal

CLOCK INPUT

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Table 10. Positioning the Corner Frequency (Some Examples)

SNRBoost Coefficient1, Normalized Corner SNRBoost Coefficient1, Normalized Corner Center FrequencyFrequency1 Frequency2< SNRBoost Coeff1 > < SNRBoost Coeff2 >(f/fs) (f/fs)

0 0.250 0 0.250 Fs × 0.25

F 0.230 1 0.270 Fs × 0.25

6 0.385 2 0.290 Fs × 0.3375

D 0.189 B 0.143 Fs × 0.166

9 0.080 7 0.420 Fs × 0.25

Figure 52. SNRBoost Active Delay

SNRBoost does not introduce any group delay in the input signal path. The ADC latency increases by four clockcycle (to 26 clock cycles). When it is enabled using the serial interface, the mode becomes fully active 10 inputclock cycles after the 16

th

SCLK falling edge. When it is disabled, normal data (without SNRBoost) resumes after6 clock cycle.

ADS62C17 clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), withlittle or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCMusing internal 5-k Ωresistors as shown in Figure 53 . This allows using transformer-coupled drive circuits for sinewave clock or ac-coupling for LVPECL, LVDS clock sources (Figure 54 and Figure 55 ).

Product Folder Link(s): ADS62C17

CLKP

VCM

2 pF

Lpkg

~ 2 nH

Lpkg

~2 nH

CLKM

Clockbuffer

Ceq Ceq

Ceq~ 1 to 3 pF, equivalentinputcapacitanceofclockbuffer

C

~1pF

bond

R

~100 W

20 W

C

~1pF

bond

R

~100 W

5kW

CLKP

CLKM

0.1 Fm

Differentialsine-wave

orPECL orLVDSclockinput

ADS62C17

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Figure 53. Internal Clock Buffer

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-modenoise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-passfiltering of the clock source can help reduce the effect of jitter. There is no change in performance with anon-50% duty cycle clock input.

Figure 54. Differential Clock Driving Circuit

Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM tied to 1.5V common-mode voltage.As shown in Figure 55 , CLKM can be tied to VCM pin.

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CLKP

CLKM

VCM

0.1 Fm

CMOSclockinput

GAIN PROGRAMMABILITY

OFFSET CORRECTION

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Figure 55. Single-Ended Clock Driving Circuit

ADS62C17 includes gain settings that can be used to get improved SFDR performance (compared to 0dB gain).The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scalerange scales proportionally, as shown in Table 11 .

The SFDR improvement is achieved at the expense of SNR; for each 1dB gain step, the SNR degrades about1dB. The SNR degradation is less at high input frequencies. As a result, the gain is very useful at high inputfrequencies as the SFDR improvement is significant with marginal degradation in SNR.

So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.

Table 11. Full-Scale Range Across Gains

Gain, dB Full-Scale, Vpp

0 2V

1 1.78

2 1.59

3 1.42

4 1.26

5 1.12

6 1.00

ADS62C17 has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mV. Thecorrection can be enabled using the serial register bit < OFFSET CORRECTION ENABLE>. Once enabled, thealgorithm estimates the channel offset and applies the correction every clock cycle. The time constant of thecorrection loop is a function of the sampling clock frequency. The time constant can be controlled using registerbits < OFFSET CORR TIME CONSTANT> as described in Table 12 .

After the offset is estimated, the correction can be frozen by setting < OFFSET CORRECTION ENABLE> = 0.

Once frozen, the last estimated value is used for offset correction every clock cycle. The correction does notaffect the phase of the signal. Note that offset correction is disabled by default after reset.

Figure 56 shows the time response of the offset correction algorithm, after it is enabled.

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l TEXAS INSTRUMENTS Time - ms

1019

1020

1021

1022

1023

1024

1025

1026

-2 0 2 4 6 8 10 12 14 16 18

Time-ms

OutputCodesm-LSB

1018

20

Offsetcorrection

disabled

Offsetcorrection

enabled

Outputdatawith

offsetcorrected

Outputdatawith

4LSBoffset

POWER DOWN

ADS62C17

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Table 12. Time Constant of Offset Correction Algorithm

< OFFSET CORR TIME Time Constant (TCCLK), Time Constant, secCONSTANT >

Number of Clock Cycles (=TC

CLK

x 1/Fs)

(1)

D3-D0

0000 256 k 1.2 ms

0001 512 k 2.5 ms

0010 1 M 5 ms

0011 2 M 10 ms

0100 4 M 20 ms

0101 8 M 40 ms

0110 16 M 80 ms

0111 32 M 0.16 s

1000 64 M 0.32 s

1001 128 M 0.64 s

1010 256 M 1.28 s

1011 512 M 2.5 s

1100 RESERVED

1101 RESERVED

1110 RESERVED

1111 RESERVED

(1) Sampling frequency, Fs = 200 MSPS

Figure 56. Time Response of Offset Correction

ADS62C17 has three power down modes – power down global, individual channel standby and individualchannel output buffer disable. These can be set using either the serial register bits or using the control pinsCTRL1 to CTRL3.

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Power Down Global

Channel Power Down (individual or both channels)

Output Buffer Disable (individual or both channels)

Input Clock Stop

POWER SUPPLY SEQUENCE

DIGITAL OUTPUT INTERFACE

DDR LVDS Interface

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Table 13. Power Down Controls

POWER DOWN MODES CONFIGURE USING WAKE-UP

TIMESERIAL INTERFACE PARALLEL CONTROL

PINS

Normal operation < POWER DOWN MODES > =0000 low low low –

Output buffer disabled for channel B < POWER DOWN MODES > =1001 The pins do not –support output bufferOutput buffer disabled for channel A < POWER DOWN MODES > =1010 –disableOutput buffer disabled for channel A and B < POWER DOWN MODES > =1011 Fast (100 ns)

Global power down < POWER DOWN MODES > =1100 high low low Slow (20 µs)

Channel B standby < POWER DOWN MODES > =1101 high low high Fast (1 µs)

Channel A standby < POWER DOWN MODES > =1110 high high low Fast (1 µs)

Multiplexed (MUX) mode – Output data of channel A < POWER DOWN MODES > =1111 high high high –and B is multiplexed & available on DA10 to DA0pins.

In this mode, the entire chip including both the A/D converters, internal reference and the output buffers arepowered down resulting in reduced total power dissipation of about 45mW. The output buffers are in highimpedance state. The wake-up time from the global power down to data becoming valid in normal mode istypically 20 µs.

Here, each channel ’ s A/D converter can be powered down. The internal references are active, resulting in quickwake-up time of 1 µs. The total power dissipation in standby is about 450 mW.

Each channel ’ s output buffer can be disabled and put in high impedance state – wakeup time from this mode isfast, about 100 ns.

In addition to the above, the converter enters a low-power mode when the input clock frequency falls below1MSPS. The power dissipation is about 275 mW.

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies areseparated in the device.

ADS62C17 provides 11-bit data and an output clock synchronized with the data.

Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can beselected using the serial interface register bit < LVDS_CMOS> or using DFS pin in parallel configuration mode.

In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two databits are multiplexed and output on each LVDS differential pair.

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l TEXAS INSTRUMENTS V V

CLKOUTP

CLKOUTM

DB0_P

DB0_M

DB2_P

DB2_M

DB4_P

DB4_M

DB6_P

DB6_M

DB8_P

DB8_M

DB10_P

DB10_M

OutputClock

DatabitD0

DatabitsD1,D2

DatabitsD3,D4

DatabitsD5,D6

DatabitsD7,D8

DatabitsD9,D10

ADS62C17 LVDSBuffers

11bit ADCdata

ChannelB

ADS62C17

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Figure 57. DDR LVDS Outputs

Even data bits D0, D2, D4 … are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5 … areoutput at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to captureall the data bits (Figure 58 ).

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l TEXAS INSTRUMENTS SAMPLE N SAMPLE Na1

SAMPLE NSAMPLE N

CLKOUTMCLKOUTM

CLKOUTPCLKOUTP

DA0, DB0DA0, DB0

SAMPLE N+1SAMPLE N+1

DA2, DB2DA2, DB2

DA4,DB4DA4,DB4

DA6,DB6DA6,DB6

DA8,DB8DA8,DB8

DA10,DB10DA10,DB10

D0

D1 D2

D3 D4

D5 D6

D7 D8

D9 D10

D0

D1 D2

D3 D4

D5 D6

D7 D8

D9 D10

00

LVDS Buffer

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Figure 58. DDR LVDS Interface

The equivalent circuit of each LVDS output buffer is shown in Figure 59 . The buffer is designed to present anoutput impedance of 100 Ω(Rout). The differential outputs can be terminated at the receive end by a 100 Ω

termination.

The buffer output impedance behaves like a source-side series termination. By absorbing reflections from thereceiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and itsvalue cannot be changed.

Product Folder Link(s): ADS62C17

_______

Whenthe “High” switchesareclosed , OUTP = 1.375 V, OUTM = 1.025 V

Whenthe “Low” switchesareclosed , OUTP = 1.025 V, OUTM = 1.375 V

Switchimpedanceis

nominally 50 W(+/- 10%)

Whenthe “High” (or “Low”) switchesareclosed, Rout = 100 W

1.2 V

+ 0.35 V

- 0.35 V

OUTP

OUTM

Rout

ADS62C18

Low

High

Low High

Parallel CMOS Interface

ADS62C17

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Figure 59. LVDS Buffer Equivalent Circuit

In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The risingedge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to150 MSPS).

Up to 150MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It isrecommended to minimize the load capacitance seen by data and clock output pins by using short traces to thereceiver. Also, match the output data and clock traces to minimize the skew between them.

For sampling frequencies above 150 MSPS, it is recommended to use an external clock to capture data. Thedelay from input clock to output data and the data valid times are specified for the higher sampling frequencies.These timings can be used to delay the input clock appropriately and use it to capture the data.

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DA0

DA1

DA2

DA8

Pins

DA9

DA10

CLKOUT

11 bit ADC data

Channel A

SDOUT

11 bit ADC data

Channel B

DB0

DB1

DB2

DB8

DB9

DB10

CMOS Interface Power Dissipation

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Figure 60. Parallel CMOS Outputs

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on everyoutput pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clockcycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determinedby the average number of output bits switching, which is a function of the sampling frequency and the nature ofthe analog input signal.

Digital current due to CMOS output switching = C

L

× DRVDD × (N × F

AVG

),

where C

L

= load capacitance, N × F

AVG

= average number of output bits switching.

Figure 38 shows the current with various load capacitances across sampling frequencies at 2 MHz analog inputfrequency.

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l TEXAS INSTRUMENTS

Output Data Format

BOARD DESIGN CONSIDERATIONS

MIGRATION FROM ADS62C15 TO ADS62C17

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

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Two output data formats are supported – 2s complement and offset binary. They can be selected using the serialinterface register bit < DATA FORMAT> or controlling the DFS pin in parallel configuration mode.

In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positiveoverdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format.For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2scomplement output format.

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections ofthe board are cleanly partitioned. See the EVM User Guide (SLAU237A) for details on layout and grounding.

Supply Decoupling

As ADS62C17 already includes internal decoupling, minimal external decoupling can be used without loss inperformance. Note that decoupling capacitors can help filter external power supply noise, so the optimumnumber of capacitors would depend on the actual application. The decoupling capacitors should be placed veryclose to the converter supply pins.

Exposed PadIn addition to providing a path for heat dissipation, the pad is also electrically connected to digital groundinternally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electricalperformance. For detailed information, see application notes QFN Layout Guidelines (SLOA122 ) and QFN/SON.

PCB Attachment (SLUA271 ).

While migrating from the C15 to C17, note the following differences between the two devices.

ADS62C15 ADS62C17

Pinout

Pin 22 is AGND Pin 22 is NC

Pin 64 is DRGND Pin 64 is SDOUT (Serial readout pin)

Supply

AVDD is 3.3V No change

DRVDD is 1.8V to 3.3V (for CMOS interface) and is DRVDD is 1.8V (for both CMOS and LVDS3.3V (for LVDS interface) interfaces)

Serial Interface

Protocol: 8 bit register address & 8 bit register data No change in protocol

Serial register map is completely different

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l TEXAS INSTRUMENTS

DEFINITION OF SPECIFICATIONS

10 S

N

P

SNR = 10Log P

(3)

10 S

N D

P

SINAD = 10Log P + P

(4)

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB withrespect to the low frequency value.

Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time atwhich the sampling occurs. This delay will be different across channels. The maximum variation is specified asaperture delay variation (channel-channel).

Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remainsat a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as apercentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametrictesting is performed at this sampling rate unless otherwise noted.

Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit linedetermined by a least squares curve fit of that transfer function, measured in units of LSBs.

Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gainerror is given as a percentage of the ideal input full-scale range. Gain error has two components: error due toreference inaccuracy and error due to the channel. Both these errors are specified independently as E

GREF

andE

GCHAN

.

To a first order approximation, the total gain error will be E

TOTAL

~ E

GREF

+ E

GCHAN

.

For example, if E

TOTAL

= ± 0.5%, the full-scale input varies from (1-0.5/100) x FS

ideal

to (1 + 0.5/100) x FS

ideal

.

Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual averageidle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.

Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies thechange per degree Celsius of the parameter from T

MIN

to T

MAX

. It is calculated by dividing the maximum deviationof the parameter across the T

MIN

to T

MAX

range by the difference T

MAX

– T

MIN

.

Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),excluding the power at DC and the first nine harmonics.

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter ’ sfull-scale range.

Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P

S

) to the powerof all the other spectral components including noise (P

N

) and distortion (P

D

), but excluding dc.

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter'sfull-scale range.

Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to thetheoretical limit based on quantization noise.

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l TEXAS INSTRUMENTS AVSUP AVCM

SINAD 1.76

ENOB =

6.02

-

(5)

10 S

N

P

THD = 10Log P

(6)

(ExpressedindBc)

DVSUP

DVOUT

10

PSRR=20Log

(7)

(ExpressedindBc)

DVCM

DVOUT

10

CMRR=20Log

(8)

ADS62C17

SLAS631A – APRIL 2009 – REVISED JULY 2009 .............................................................................................................................................................

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Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P

S

) to the power of thefirst nine harmonics (PD).

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest otherspectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given inunits of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB tofull scale) when the power of the fundamental is extrapolated to the converter ’ s full-scale range.

DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to achange in analog supply voltage. The DC PSRR is typically given in units of mV/V.

AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in thesupply voltage by the ADC. If ΔV

SUP

is the change in supply voltage and ΔVout is the resultant change of theADC output code (referred to the input), then

Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after anoverload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive andnegative overload. The deviation of the first few samples after the overload (from their expected values) is noted.

Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog inputcommon-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔV

OUTis the resultant change of the ADC output code (referred to the input), then

Cross-Talk (only for multi-channel ADC) – This is a measure of the internal coupling of a signal from adjacentchannel into the channel of interest. It is specified separately for coupling from the immediate neighboringchannel (near-channel) and for coupling from channel across the package (far-channel). It is usually measuredby applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channelinput. It is typically expressed in dBc.

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l TEXAS INSTRUMENTS

ADS62C17

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............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Revision History

Changes from Original (April 2009) to Revision A .......................................................................................................... Page

•Added missing Value ............................................................................................................................................................. 9•Added paragraph - This disables any further writes into the registers, EXCEPT the register at address 0. Note thatthe < SERIAL READOUT > bit is also located in register 0. The device can exit readout mode by writing < SERIALREADOUT > to 0. Also, only the ......................................................................................................................................... 15•Changed To - To exit the serial readout mode, reset register bit < SERIAL READOUT > =0, which enables writes intoall registers of the device. .................................................................................................................................................... 15•Changed Normalized Corner Frequencies changed to fix error with respect to the mapping between the SNRBoostcoefficient value and normalized corner frequency (f/fs). ................................................................................................... 48•Changed values for Normalized Corner Frequency1, 2, and center frequency .................................................................. 49

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I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADS62C17IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62C17

ADS62C17IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62C17

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS62C17IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Sep-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS62C17IRGCR VQFN RGC 64 2000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Sep-2021

Pack Materials-Page 2

www.ti.com

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

VQFN - 1 mm max heightRGC 64

PLASTIC QUAD FLATPACK - NO LEAD

9 x 9, 0.5 mm pitch

4224597/A

: a ﬁL CCCCCCCECCCCCC UUUUUUU ﬂﬂﬂﬂﬂﬂﬂﬂ UUUUUUU ﬂﬂﬂﬂﬂﬂﬂﬂ 64 DDDDDDDHDDDDDD} W 1‘ , L|L

www.ti.com

PACKAGE OUTLINE

C

9.15

8.85

9.15

8.85

1.0

0.8

0.05

0.00

2X 7.5

60X

0.5

2X 7.5

64X 0.5

0.3

64X 0.30

0.18

7.4 0.1

(0.2) TYP

VQFN - 1 mm max heightRGC0064H

PLASTIC QUAD FLATPACK - NO LEAD

4219011/A 05/2018

0.08 C

0.1 C A B

0.05

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMM

EXPOSED

THERMAL PAD

SYMM

1

16

17 32

33

48

49

64

65

SCALE 1.500

A

B

gmﬁimimﬁﬂﬁmw “““ , oi? H! O O O % A O O‘nﬁ “U M %‘ P O O O % % M o o o DU 0 o m wﬁw DU ﬂﬁmﬁm ““““ L

www.ti.com

EXAMPLE BOARD LAYOUT

60X (0.5)

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

(1.16) TYP

(3.45) TYP

(1.16) TYP

(3.45) TYP

64X (0.6)

64X (0.24)

(8.8)

( 7.4)

( 0.2) TYP

VIA

VQFN - 1 mm max heightRGC0064H

PLASTIC QUAD FLATPACK - NO LEAD

4219011/A 05/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SEE SOLDER MASK

DETAIL

1

16

17 32

33

48

49

64

65

METAL EDGE

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS

Q LﬂBaﬁmewgmmgb 7%,, Lt

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EXAMPLE STENCIL DESIGN

64X (0.6)

64X (0.24)

60X (0.5)

(8.8)

36X ( 0.96)

(R0.05) TYP

(0.58)

(1.16) TYP

(0.58)

(1.16)

TYP

VQFN - 1 mm max heightRGC0064H

PLASTIC QUAD FLATPACK - NO LEAD

4219011/A 05/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

1

16

17 32

33

48

49

64

65

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ADS62C17 Datasheet by Texas Instruments

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