DS90LV804 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS EN
EN
OUT0+
OUT0-
IN0-
IN0+
OUT1+
OUT1-
IN1-
IN1+
OUT2+
OUT2-
IN2-
IN2+
OUT3+
OUT3-
IN3-
IN3+
DS90LV804
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater
Check for Samples: DS90LV804
In order to maximize signal integrity, the DS90LV804
1FEATURES features both an internal input and output (source)
23• 800 Mbps Data Rate per Channel termination to eliminate these extra components from
• Low Output Skew and Jitter the board, and to also place the terminations as close
as possible to receiver inputs and driver output. This
• LVDS/CML/LVPECL Compatible Input, LVDS is especially significant when driving longer cables.
Output
The DS90LV804, available in the WQFN (Leadless
• On-Chip 100ΩInput and Output Termination Leadframe Package) package, minimizes the
• 12 kV ESD Protection on LVDS Outputs footprint, and improves system performance.
• Single 3.3V Supply An output enable pin is provided, which allows the
• Very Low Power Consumption user to place the LVDS outputs and internal biasing
• Industrial -40 to +85°C Temperature Range generators in a TRI-STATE®, low power mode.
• Small WQFN Package Footprint The differential inputs interface to LVDS, and Bus
LVDS signals such as those on TI's 10-, 16-, and 18-
DESCRIPTION bit Bus LVDS SerDes, as well as CML and LVPECL.
The DS90LV804 is a four channel 800 Mbps LVDS The differential inputs are internally terminated with a
buffer/repeater. In many large systems, signals are 100Ωresistor to improve performance and minimize
distributed across cables and signal integrity is highly board space. This function is especially useful for
dependent on the data rate, cable type, length, and boosting signals over lossy cables or point-to-point
the termination scheme. backplane configurations.
Block and Connection Diagrams
Figure 1. DS90LV804 Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2TRI-STATE is a registered trademark of National Semiconductor Corporation.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
*9 TEXAS INSTRUMENTS ozo ozo nzo
8 7 6 5 4 3 2 1
17 18 19 20 21 22 23 24
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
DAP
(GND)
OUT0+
OUT0-
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
IN0+
IN0-
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
EN
VDD
VDD
GND
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
N/C
N/C
DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
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DS90LV804 WQFN Pinout
(Top View)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VDD)−0.3V to +4.0V
CMOS Input Voltage (EN) −0.3V to (VDD+0.3V)
LVDS Input Voltage(2) −0.3V to (VDD+0.3V)
LVDS Output Voltage −0.3V to (VDD+0.3V)
LVDS Output Short Circuit Current +90 mA
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Solder, 4sec) 260°C
Max Pkg Power Capacity @ 25°C 4.16W
θJA 29.5°C/W
Thermal Resistance θJC 3.5°C/W
Package Derating above +25°C 33.3mW/°C
HBM, 1.5kΩ, 100pF 12 kV
ESD Last Passing Voltage (LVDS output pins) EIAJ, 0Ω, 200pF 250V
Charged Device Model 1000V
HBM, 1.5kΩ, 100pF 8 kV
ESD Last Passing Voltage (All other pins) EIAJ, 0Ω, 200pF 250V
Charged Device Model 1000V
(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of products outside of recommended operation conditions.
(2) VID max < 2.4V
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Recommended Operating Conditions
Supply Voltage (VCC) 3.15V to 3.45V
Input Voltage (VI)(1) 0V to VDD
Output Voltage (VO) 0V to VDD
Operating Temperature (TA) Industrial −40°C to +85°C
(1) VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ(1) Max Units
LVTTL DC SPECIFICATIONS (EN)
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA
IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA
CIN1 Input Capacitance Any Digital Input Pin to VSS 3.5 pF
VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.8 V
LVDS INPUT DC SPECIFICATIONS (INn±)
VTH VCM = 0.8V to 3.4V,
Differential Input High Threshold(2) 0 100 mV
VDD = 3.45V
VTL VCM = 0.8V to 3.4V,
Differential Input Low Threshold(2) −100 0 mV
VDD = 3.45V
VID Differential Input Voltage VCM = 0.8V to 3.4V, VDD = 3.45V 100 2400 mV
VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 0.05 3.40 V
CIN2 Input Capacitance IN+ or IN−to VSS 3.5 pF
IIN VIN = 3.45V, VDD = VDDMAX −10 +10 µA
Input Current VIN = 0V, VDD = VDDMAX −10 +10 µA
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
VOD Differential Output Voltage(2) 250 500 600 mV
ΔVOD Change in VOD between −35 35 mV
Complementary States RL= 100Ωexternal resistor between OUT+ and
OUT−
VOS Offset Voltage(3) 1.05 1.18 1.475 V
ΔVOS Change in VOS between −35 35 mV
Complementary States
IOS Output Short Circuit Current OUT+ or OUT−Short to GND −60 −90 mA
COUT2 Output Capacitance OUT+ or OUT−to GND when TRI-STATE 5.5 pF
SUPPLY CURRENT (Static)
ICC All inputs and outputs enabled and active,
Total Supply Current terminated with external differential load of 100Ω117 140 mA
between OUT+ and OUT-.
ICCZ TRI-STATE Supply Current EN = 0V 2.7 6 mA
(1) Typical parameters are measured at VDD = 3.3V, TA= 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
(3) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
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FPGA or ASIC
LVDS I/O
Cable or Backplane
FPGA or ASIC
LVDS I/O
DS90LV804
DS90LV804
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ(1) Max Units
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT Differential Low to High Transition 210 300 ps
Time Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of VOD(4)
tHLT Differential High to Low Transition 210 300 ps
Time
tPLHD Differential Low to High 2.0 3.2 ns
Propagation Delay Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% VOD between input to output.
tPHLD Differential High to Low 2.0 3.2 ns
Propagation Delay
tSKD1 Pulse Skew |tPLHD–tPHLD|(4) 25 80 ps
tSKCC Difference in propagation delay (tPLHD or tPHLD)
Output Channel to Channel Skew 50 125 ps
among all output channels(4)
tSKP Part to Part Skew Common edge, parts at same temp and VCC(4) 1.1 ns
tJIT RJ - Alternating 1 and 0 at 400 MHz(6) 1.1 1.5 psrms
Jitter(5) DJ - K28.5 Pattern, 800 Mbps(7) 15 35 psp-p
TJ - PRBS 223-1 Pattern, 800 Mbps(8) 30 55 psp-p
tON Time from EN to OUT± change from TRI-STATE to
LVDS Output Enable Time 300 ns
active.
tOFF Time from EN to OUT± change from active to TRI-
LVDS Output Disable Time 12 ns
STATE.
(4) Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 400 MHz, tr= tf= 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5
pattern at 800 Mbps, tr= tf= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 800 Mbps, tr= tf= 50ps (20% to 80%).
Typical Application
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! TEXAS INSTRUMENTS Receiver Dun OUT-
OUT+
OUT-
DS90LV804
Receiver
IN+
IN-
100: Differential T-Line
100:
LVDS
Driver
DS90LV804
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
APPLICATION INFORMATION
INTERNAL TERMINATIONS
The DS90LV804 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the
device. The LVDS outputs also contain an integrated 100Ωohm termination resistor, this resistor is used to
reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the
inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external
component count resulting in space savings.
OUTPUT CHARACTERISTICS
The output characteristics of the DS90LV804 have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop signaling.
TRI-STATE MODE
The EN input activates a hardware TRI-STATE mode. When the TRI-STATE mode is active (EN=L), all input and
output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in TRI-STATE
mode. When exiting TRI-STATE mode, there is a delay associated with turning on bandgap references and
input/output buffer circuits as indicated in the LVDS Output Switching Characteristics
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and
the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be
in the 5kΩto 15kΩrange to minimize loading and waveform distortion to the driver. The common-mode bias
point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information.
INPUT INTERFACING
The DS90LV804 accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the DS90LV804 can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML).
Figure 2,Figure 3, and Figure 4 illustrate typical DC-coupled interface to common differential drivers. Note that
the DS90LV804 inputs are internally terminated with a 100Ωresistor.
Figure 2. Typical LVDS Driver DC-Coupled Interface to DS90LV804 Input
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l TEXAS INSTRUMENTS Hecewer Receiver OUT- ‘50-2509 LVPECL or
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
100:
100: Differential T-Line
Differential
Receiver
DS90LV804
Driver
100:
OUT+
OUT-
150-250:
100: Differential T-Line
LVDS
Receiver
IN+
IN-
100:
LVPECL
Driver
150-250:
OUT+
OUT-
50:50:
VCC
CML3.3V or CML2.5V
Driver
100: Differential T-Line
DS90LV804
Receiver
IN+
IN-
100:
DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
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Figure 3. Typical CML Driver DC-Coupled Interface to DS90LV804 Input
Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS90LV804 Input
OUTPUT INTERFACING
The DS90LV804 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to
most common differential receivers. Figure 5 illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
Figure 5. Typical DS90LV804 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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PIN DESCRIPTIONS
Pin WQFN Pin I/O, Type Description
Name Number
DIFFERENTIAL INPUTS
IN0+ 9 I, LVDS Channel 0 inverting and non-inverting differential inputs.
IN0−10
IN1+ 11 I, LVDS Channel 1 inverting and non-inverting differential inputs.
IN1−12
IN2+ 13 I, LVDS Channel 2 inverting and non-inverting differential inputs.
IN2−14
IN3+ 15 I, LVDS Channel 3 inverting and non-inverting differential inputs.
IN3−16
DIFFERENTIAL OUTPUTS
OUT0+ 32 O, LVDS Channel 0 inverting and non-inverting differential outputs(1)
OUT0−31
OUT1+ 30 O, LVDS Channel 1 inverting and non-inverting differential outputs(1)
OUT1−29
OUT2+ 28 O, LVDS Channel 2 inverting and non-inverting differential outputs(1)
OUT2−27
OUT3+ 26 O, LVDS Channel 3 inverting and non-inverting differential outputs(1)
OUT3- 25
DIGITAL CONTROL INTERFACE
EN 8 I, LVTTL Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-
STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL level input.
POWER
VDD 3, 4, 6, 7, 19, 20, 21, 22 I, Power VDD = 3.3V, ±5%
GND 1, 2, 5, 17, 18(2) I, Power Ground reference for LVDS and CMOS circuitry. For the WQFN package, the DAP is
used as the primary GND connection to the device. The DAP is the exposed metal
contact at the bottom of the WQFN-32 package. It should be connected to the ground
plane with at least 4 vias for optimal AC and thermal performance. The pin numbers
listed should also be tied to ground for proper biasing.
N/C 23, 24 No Connect
(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV804 device have
been optimized for point-to-point backplane and cable applications.
(2) Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to grounding
actual pins on the package as listed.
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l TEXAS INSTRUMENTS 350 lack
POWER SUPPLY CURRENT (mA)
350
0
BIT DATA RATE (Gbps)
50
100
150
200
250
300
PRBS-23
Clock
0 0.25 0.5 0.75 1.0
DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
A. Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA=
+25°C, VID = 0.5V, VCM = 1.2V Figure 6. Power Supply Current vs Bit Data Rate
PACKAGING INFORMATION
The Leadless Leadframe Package (WQFN) is a leadframe based chip scale package (CSP) that may enhance
chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The
small size and very low profile make this package ideal for high density PCBs used in small-scale electronic
applications such as cellular phones, pagers, and handheld PDAs. The WQFN package is offered in the no
Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the
edge of the package. This feature offers a visible solder fillet after board mounting.
The WQFN has the following advantages:
• Low thermal resistance
• Reduced electrical parasitics
• Improved board space efficiency
• Reduced package height
• Reduced package mass
For more details about WQFN packaging technology, refer to applications note AN-1187, "Leadless Leadframe
Package".
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision K (April 2013) to Revision L Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90LV804TSQ WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS90LV804TSQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS90LV804TSQX/NOPB WQFN RTV 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Apr-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV804TSQ WQFN RTV 32 1000 208.0 191.0 35.0
DS90LV804TSQ/NOPB WQFN RTV 32 1000 208.0 191.0 35.0
DS90LV804TSQX/NOPB WQFN RTV 32 4500 356.0 356.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Apr-2022
Pack Materials-Page 2
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PACKAGE OUTLINE
C
5.15
4.85
5.15
4.85
0.8
0.7
0.05
0.00
2X 3.5
28X 0.5
2X 3.5
32X 0.5
0.3
32X 0.30
0.18
3.1 0.1
(0.1) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
0.08 C
0.1 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PIN 1 INDEX AREA
SEATING PLANE
PIN 1 ID
SYMM
EXPOSED
THERMAL PAD
SYMM
1
8
916
17
24
25
32
33
SCALE 2.500
A
B
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EXAMPLE BOARD LAYOUT
28X (0.5)
(1.3)
(1.3)
(R0.05) TYP
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
32X (0.6)
32X (0.24)
(4.8)
(4.8)
(3.1)
(3.1)
( 0.2) TYP
VIA
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SYMM
SYMM
SEE SOLDER MASK
DETAIL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
1
8
916
17
24
25
32
33
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
$61819 ‘ i A T” w i i i 86%
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EXAMPLE STENCIL DESIGN
32X (0.6)
32X (0.24)
28X (0.5)
(4.8)
(4.8)
(0.775) TYP
(0.775) TYP
4X (1.35)
4X (1.35)
(R0.05) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SYMM
SYMM
1
8
916
17
24
25
32
33
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