NB6L14S Datasheet by onsemi

The NBéL14S is a member of xhc ECLinPS MAXW family of high VOLTAGE (130 mV/dN) 'EF'F'EEW‘ ‘ m §WDF€M1V L ON Semiconductor“3 Q . w : Work Week . : Pb-Free Package 'Far additional marking inlarmafion, reler m Appncauon Note ANDsoozn. — 00 -° D? \L 01 IN ”1 UT VT 50 (2 w \L 02 >-c DI EN D n {LV'I'I’L/SMDS) _ __ 03 REFAC _c D? 0 See dmanleda
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 2
1Publication Order Number:
NB6L14S/D
NB6L14S
2.5 V 1:4 AnyLevel]
Differential Input to LVDS
Fanout Buffer/Translator
The NB6L14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevel differential input signals: LVPECL, CML, LVDS, or
HSCL. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6L14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6L14S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
The NB6L14S is the 2.5 V version of the NB6N14S and is offered in
a small 3 mm x 3 mm 16−QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
The NB6L14S is a member of the ECLinPS MAX™ family of high
performance products.
Features
•Maximum Input Clock Frequency > 2.0 GHz
•Maximum Input Data Rate > 2.5 Gb/s
•1 ps Maximum of RMS Clock Jitter
•Typically 10 ps of Data Dependent Jitter
•380 ps Typical Propagation Delay
•120 ps Typical Rise and Fall Times
•Single Power Supply; VCC = 2.5 $ 5%
•VREF_AC Reference Output
•These are Pb−Free Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
VOLTAGE (130 mV/div)
Device DDJ = 10 ps
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
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See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
16
NB6L
14S
ALYW G
G
1
1
Q3
Q3
Figure 1. Logic Diagram
Q2
Q2
Q1
Q1
Q0
Q0
EN DQ
(LVTTL/CMOS)
VREFAC
50
W
50
W
IN
VT
IN
(Note: Microdot may be in either location)
9 1:: p |_ l' |_ l' K 1 I _| L_| L_| LJ 0 F‘l F'I F'I F'I lml El E1 L» r‘lr‘lr‘lr‘l llllllll D5 \ntemad 100 :2 Center-tapped Termmanon Pm Ior IN and W In the dwlf on IN/W
NB6L14S
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Figure 3. NB6L14S Pinout, 16−pin QFN (Top View)
Q3 Q3 VCC EN
GND
IN
VT
VREFAC
IN
Q1
Q1
Q2
Q2
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB6L14S
Exposed Pad (EP)
Q0 Q0 VCC
IN IN EN Q
01 10
10 11
x x 0 0 (Note 1)
1. On next transition of the input signal (IN).
Table 1. TRUTH TABLE
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q2 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 Q3 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6 Q3 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7 VCC −Positive Supply Voltage.
8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 26. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9 IN LVPECL, CML, LVDS Inverted Differential Input
10 VREFAC LVPECL Output The VREFAC reference output can only be used to rebias capacitor−coupled
differential or single−ended input signals. For the capacitor−coupled IN and/or
INb inputs, VREFAC should be connected to the VT pin and bypassed to ground
with a 0.01 mF capacitor.
11 VTLVPECL Output Internal 100 W Center−tapped Termination Pin for IN and IN
12 IN LVPECL, CML, LVDS Non−inverted Differential Input. (Note 2)
13 GND −Negative Supply Voltage.
14 VCC −Positive Supply Voltage.
15 Q0 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16 Q0 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
−EP −The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to self−oscillation.
0mm 5mm 0mm 0 Lme-to-Lme (0100 Lme-to-End (Q or U QorU QtOU
NB6L14S
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Table 3. ATTRIBUTES
Characteristics Value
Moisture Sensitivity (Note 3) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200 V
Transistor Count 745
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 3.8 V
VIN Positive Input GND = 0 V VIN ≤ VCC 3.8 V
IIN Input Current Through RT (50 W Resistor) Static
Surge
35
70
mA
mA
IOSC Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Q or Q
Q to Q to GND
Continuous
Continuous
12
24
mA
IREF_AC VREF_AC Sink/Source Current "0.5 mA
TAOperating Temperature Range QFN−16 −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 4) QFN−16 4.0 °C/W
Tsol Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB6L14S
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Table 5. DC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current (Note 9) 65 100 mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 17, 18, 22, and 24)
Vth Input Threshold Reference Voltage Range (Note 8) GND +100 VCC − 100 mV
VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV
VIL Single−ended Input LOW Voltage GND Vth − 100 mV
VREFAC Reference Output Voltage (Note 11) VCC − 1.600 VCC − 1.425 VCC − 1.300 V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10, 12, NO TAG, NO TAG, 23, and 25)
VIHD Differential Input HIGH Voltage 100 VCC mV
VILD Differential Input LOW Voltage GND VIHD − 100 mV
VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV
VID Differential Input Voltage (VIHD − VILD) 100 VCC mV
RTIN Internal Input Termination Resistor 40 50 60 W
LVDS OUTPUTS (Note 5)
VOD Differential Output Voltage 250 450 mV
DVOD Change in Magnitude of VOD for Complementary Output States
(Note 10)
0 1 25 mV
VOS Offset Voltage (Figure 21) 1125 1375 mV
DVOS Change in Magnitude of VOS for Complementary Output States
(Note 10)
0 1 25 mV
VOH Output HIGH Voltage (Note 6) 1425 1600 mV
VOL Output LOW Voltage (Note 7) 900 1075 mV
LVTTL/LVCMOS INPUT, EN
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage GND 0.8 V
IIH Input HIGH Current −150 150 mA
IIL Input LOW Current −150 150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 20.
6. VOHmax = VOSmax + ½ VODmax.
7. VOLmax = VOSmin − ½ VODmax.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. Input termination pins open at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
10.Parameter guaranteed by design verification not tested in production.
11. VREFAC used to rebias capacitor−coupled inputs only (see Figures 17 and 18).
EN to lN/W Q‘U Measured by lorcmg vapmm mm 50% duty cy edge rates 150 p5 (mm—50%). See Figure 20, \npm voltage ewmg Is a Single-ended measurement oper HMS .mer win 50% Duty Cyc‘e dock slow a 750 MHz. Demrmrmsnc jrlter with mpm NR2 dala at PRES 2 —1 and K255. Skew rs measured between outpum under rdennoa\ transmon @ 250 MHz. The worsl case sandman belween Qo/lm and Qw/o‘flrorn either Do/DU or DHDT
NB6L14S
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Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 12)
Symbol Characteristic
−40°C to +85°C
Unit
Min Typ Max
finMax Maximum Input Clock Frequency 2.0 GHz
VOUTPP Output Voltage Amplitude (@ VINPPmin)f
in ≤ 1.0 GHz
(Figure 4) fin= 1.5 GHz
fin= 2.0 GHz
220
200
170
350
300
270
mV
fDATA Maximum Operating Data Rate 2.5 Gb/s
tPLH,
tPHL
Differential Input to Differential Output, IN to Q
Propagation Delay @ 100 MHz
300 450 600 ps
ts
th
Setup Time EN to IN/IN
Hold Time
300
500
20
20
tSKEW Within Device Skew (Note 17)
Device−to−Device Skew (Note 16)
5
30
20
200
ps
tJITTER RMS Random Clock Jitter (Note 14) fin = 2.0 GHz
Deterministic Jitter (Note 15) fDATA v 2.488 Gb/s
0.5
5.0
0.8
20
ps
VINPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
100 VCC−GND mV
tr
tf
Output Rise/Fall Times @ 250 MHz Q, Q
(20% − 80%)
70 150 225 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input
edge rates 150 ps (20%−80%). See Figure 20.
13.Input voltage swing is a single−ended measurement operating in differential mode.
14.RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15.Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
16.Skew is measured between outputs under identical transition @ 250 MHz.
17.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
OUTPUT VOLTAGE AMPLITUDE (mV)
0
50
100
150
200
250
300
350
400
0.5 1 1.5 2 2.5 30
4mm (mun: kaxywk WW“ m 4mm “w w {VHJX A ‘” V‘2,\r’4—\
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Figure 5. Typical Phase Noise Plot at
fcarrier = 311.04 MHz
Figure 6. Typical Phase Noise Plot at
fcarrier = 622.08 MHz
Figure 7. Typical Phase Noise Plot at
fcarrier = 1 GHz
Figure 8. Typical Phase Noise Plot at
fcarrier = 1.5 GHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the NB6L14S device
at frequencies 311.04 MHz, 622.08 MHz, 1 GHz and
1.5 GHz respectively at an operating voltage of 2.5 V in
room temperature. The RMS Phase Jitter contributed by the
device (integrated between 12 kHz and 20 MHz; as shown
in the shaded region of the plot) at each of the frequencies
is 65 fs, 29 fs, 24 fs and 20 fs respectively. The input source
used for the phase noise measurements is Agilent E8663B.
_____j ___T I. | | | | | | | | '— | | LVPECL | VT : V00 ' 30 V | LVPECL | | | Dnver ' Dnver | ‘— J_|m | L__ ___J L___ __4 L__ ___J iL___ __4 VEE/GND GND VEE/GND Figure 10. LVPECL Interface Figure 11. LVPECL V—Termin GND GND Figure 12. LVDS Interface Figure 1a. CML lnlerfac hflp://onsemi.com 7
NB6L14S
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TIME (58 ps/div)
Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask
(VINPP = 100 mV; Input Signal DDJ = 14 ps)
VOLTAGE (63.23 mV/div)
Device DDJ = 10 ps
VCC = 3.3 V or 2.5 V
LVPECL
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
NB6L14S
VCC = 2.5 V
Figure 10. LVPECL Interface
VT = VCC − 2.0 V
VEE / GND GND
VCC = 3.3 V or 2.5 V
LVPECL
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
NB6L14S
VCC = 2.5 V
Figure 11. LVPECL Y−Termination Interface
VT
VEE / GND GNDGND
VCC
0.1 mF
19 W
Figure 12. LVDS Interface
LVDS
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VT = OPEN
GND GND
NB6L14S
VCC = 3.3 V or 2.5 V VCC = 2.5 V
Figure 13. CML Interface
CML
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VT = VCC
GND GND
NB6L14S
VCC = 2.5 V VCC = 2.5 V
r___I ——-I I——— -I | | | | I I— | I | | | LVCMOS | VT : OPEN . | I Dnver I I | I | | | | I I I W I L__—(L___J L__l__4 GND efiD GND Figure 15. LVCMOS lnterfa r ' ‘ o:>—I ‘ | I— | I I | DIfferemIaI I I I DlIver I I | I I I I— 4:509 I L I.— Figure 16. LVTI'L lnterfac r -I I I— 20:509 | | | SIngIe-Ended | | DrIvel | | | | | | | L__ ___J a hllp://onsemi.com a
NB6L14S
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Figure 14. HSTL Interface
HSTL
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VT = GND
GND GND
NB6L14S
VCC = 3.3 V or 2.5 V VCC = 2.5 V
GND
VCC = 2.5 V
GND
LVCMOS
Driver
50 W*
Zo = 50 W
50 W*
NB6L14S
Figure 15. LVCMOS Interface
IN
VT = OPEN
IN
GND
VCC = 2.5 V
2.5 kW
VCC
Differential
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VCC = 2.5 V
VT = VREFAC*
VCC
Single−Ended
Driver
IN
50 W
Zo = 50 W
50 W
IN
GND GND
GND GND
VT = VREFAC*
NB6L14S
NB6L14S
VCC = 2.5 V
GNDGND
LVTTL
Driver
50 W*
Zo = 50 W
50 W*
NB6L14S
Figure 16. LVTTL Interface
IN
VT = OPEN
IN
*VREFAC bypassed to ground with a 0.1 mF capacitor.
VCC = 2.5 V VCC = 2.5 V
GND
1.5 kW
Figure 17. Capacitor−Coupled Differential
Interface (VT Connected to VREF_AC)
Figure 18. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.1 mF capacitor.
—————————— __________ —————————— __________
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Figure 19. AC Reference Measurement
IN
IN
Q
Q
tPHL
tPLH
VINPP = VIH(D) − VIL(D)
VOUTPP = VOH(Q) − VOL(Q)
Figure 20. Typical LVDS Termination for Output Driver and Device Evaluation
Driver
Device Oscilloscope
QD
Q D
LVDS
100 W
Zo = 50 W
Zo = 50 W
HI Z Probe
HI Z Probe
VOL
QN
VOH
QN
VOS VOD
Figure 21. LVDS Output
Figure 22. Differential Input Driven
Single−Ended
IN
Figure 23. Differential Inputs Driven
Differentially
IN
Vth
Vth
IN
IN
VIH
VIL
VIHmax
VILmax
VIHmin
VILmin
VCC
Vthmax
Vthmin
GND
Vth
Figure 24. Vth Diagram
IN
IN
VILD(MAX)
VIHD(MAX)
VIHD
VILD
VIHD(MIN)
VILD(MIN)
VCMR
GND
Figure 25. VCMR Diagram
VID = VIHD − VILD
VCC
VCMRmax
VCMRmin
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IN
IN
VCC/2
tS
VCC/2
tH
tpd
EN
Q
Q
Figure 26. EN Timing Diagram
Figure 27. Tape and Reel Pin 1 Quadrant Orientation
ORDERING INFORMATION
Device Package Shipping†
NB6L14SMNG QFN−16, 3 X 3 mm
(Pb−Free)
123 Units / Rail
NB6L14SMNTXG QFN−16, 3 X 3 mm
(Pb−Free)
3000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 27)
NB6L14SMNTWG QFN−16, 3 X 3 mm
(Pb−Free)
3000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 27)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE E
16X
SEATING
PLANE
L
D
E
0.10 C
A
A1
e
D2
E2
b
1
4
8
9
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
A
0.10 CTOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.05 C
0.05 C
(A3)
C
NOTE 4
16X
0.10 C
0.05 C
A B
NOTE 3
K
16X
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 1.65 1.85
E3.00 BSC
E2 1.65 1.85
e0.50 BSC
K
L0.30 0.50
0.18 TYP
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL A
DETAIL B
L1 0.00 0.15
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
2X
0.50
PITCH
1.84 3.30
1
DIMENSIONS: MILLIMETERS
0.58
16X
2X
0.30
16X
OUTLINE
PACKAGE
2X
2X
0.10 C A B
e/2
SOLDERING FOOTPRINT*
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
NB6L14S/D
AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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