74AHC(T)240 Datasheet by Nexperia USA Inc.

1. General description
The 74AHC240 and 74AHCT240 are 8-bit inverting buffer/line drivers with 3-state outputs.
These devices can be used as two 4-bit buffers or one 8-bit buffer. They feature two
output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on
nOE causes the outputs to assume a high-impedance OFF-state. Inputs are over voltage
tolerant. This feature allows the use of these devices as translators in mixed voltage
environments.
2. Features and benefits
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than VCC
For 74AHC240 only: operates with CMOS input levels
For 74AHCT240 only: operates with TTL input levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101D exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Rev. 4 — 25 September 2013 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC240D 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74AHCT240D
74AHC240PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74AHCT240PW
74AHC240BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74AHCT240BQ
7 CCCCCCCC W H U @ 33333333 7E jjjjjjjjjj O TEEEEEEEEE
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 2 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol
mgu779
1A3
1A2
1A1
1A0
2
4
6
8
1
1Y0
1Y1
18
16
14
12
1Y2
1Y3
1OE
2A3
2A2
2A1
2A0
17
15
13
11
19
2Y0
2Y1
3
5
7
9
2Y2
2Y3
2OE
12
14
2
4
6
8
18
16
1EN
mgu778
3
5
11
13
15
17
9
7
19 EN
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SO20 and TSSOP20 Fig 4. Pin configuration DHVQFN20
74AHC240
74AHCT240
1OE V
CC
1A0 2OE
2Y0 1Y0
1A1 2A0
2Y1 1Y1
1A2 2A1
2Y2 1Y2
1A3 2A2
2Y3 1Y3
GND 2A3
001aal192
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aal193
74AHC240
74AHCT240
GND(1)
Transparent top view
1Y3
1A3
2Y3
2A2
2Y2 1Y2
1A2 2A1
2Y1 1Y1
1A1 2A0
2Y0 1Y0
1A0 2OE
GND
2A3
1OE
VCC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
la,
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 3 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 package: above 70 C the value of Ptot derates linearly with 8.0 mW/K.
For TSSOP20 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 package: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
1OE 1 output enable input (active LOW)
2OE 19 output enable input (active LOW)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input
2A0, 2A1, 2A2, 2A3 17, 15, 13, 11 data input
1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12 data output
2Y0, 2Y1, 2Y2, 2Y3 3, 5, 7, 9 data output
GND 10 ground (0 V)
VCC 20 power supply
Table 3. Function table[1]
Control Input Output
nOE nAn nYn
LLH
LHL
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V [1] 20 - mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - 75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[2] - 500 mW
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 4 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74AHC240
VCC supply voltage 2.0 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 3.3 V 0.3 V - - 100 ns/V
VCC = 5 V 0.5V --20ns/V
74AHCT240
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 5 V 0.5V --20ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC240
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO= 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO= 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO= 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO= 8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 5 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
IIinput leakage
current VI=5.5VorGND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 A
IOZ OFF-state
output current VI =V
IH or VIL;
VO=V
CC or GND;
VCC =5.5V
--0.25 - 2.5 - 10.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --4.0- 40 - 80A
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4- - - - -pF
74AHCT240
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A 4.4 4.5 - 4.4 - 4.4 - V
IO= 8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI=5.5VorGND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 A
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND per input
pin; other inputs at
VCC or GND; IO=0 A;
VCC =5.5V
--0.25 - 2.5 - 10.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --4.0- 40 - 80A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other pins at VCC or GND;
IO=0 A; V
CC = 4.5 V to 5.5 V
--1.35- 1.5 - 1.5mA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Figure 7 W” i Figure 5 7 Figure 6 7 Figure 6 7
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 6 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
74AHC240
tpd propagation delay nAn to nYn; see Figure 5 [2]
VCC = 3.0 V to 3.6 V; CL= 15 pF - 3.9 7.5 1.0 8.6 10.8 ns
VCC = 3.0 V to 3.6 V; CL= 50 pF - 5.8 11.0 1.0 12.5 15.6 ns
VCC = 4.5 V to 5.5 V; CL= 15 pF - 2.8 4.8 1.0 5.7 7.1 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 4.2 7.3 1.0 8.5 10.6 ns
ten enable time nOE to nYn; see Figure 6 [2]
VCC = 3.0 V to 3.6 V; CL= 15 pF - 4.4 10.0 1.0 12.0 19.4 ns
VCC = 3.0 V to 3.6 V; CL= 50 pF - 5.8 13.5 1.0 15.5 19.4 ns
VCC = 4.5 V to 5.5 V; CL= 15 pF - 3.1 6.5 1.0 7.7 12.5 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 4.1 8.5 1.0 10.0 12.5 ns
tdis disable time nOE to nYn; see Figure 6 [2]
VCC = 3.0 V to 3.6 V; CL= 15 pF - 5.3 9.0 1.0 10.0 18.1 ns
VCC = 3.0 V to 3.6 V; CL= 50 pF - 8.9 13.0 1.0 14.5 18.1 ns
VCC = 4.5 V to 5.5 V; CL= 15 pF - 3.9 5.8 1.0 6.5 8.1 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 6.2 8.7 1.0 9.5 11.8 ns
CPD power dissipation
capacitance VI= GND to VCC; CL=50pF;
fi=1MHz
[3] -9 -- - -pF
Figure 7 Figure 5 Figure 6 Figure 6 W” i
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 7 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fi N + (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
74AHCT240
tpd propagation delay nAn to nYn; see Figure 5 [2]
VCC = 4.5 V to 5.5 V; CL= 15 pF - 3.0 5.8 1.0 6.8 8.5 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 4.4 8.4 1.0 9.5 11.9 ns
ten enable time nOE to nYn; see Figure 6 [2]
VCC = 4.5 V to 5.5 V; CL= 15 pF - 3.4 7.5 1.0 9.0 14.4 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 4.5 9.5 1.0 11.5 14.4 ns
tdis disable time nOE to nYn; see Figure 6 [2]
VCC = 4.5 V to 5.5 V; CL= 15 pF - 3.9 6.1 1.0 6.7 8.3 ns
VCC = 4.5 V to 5.5 V; CL= 50 pF - 6.2 8.7 1.0 9.2 11.5 ns
CPD power dissipation
capacitance VI= GND to VCC; CL=50pF;
fi=1MHz
[3] -9 -- - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay input (nAn) to output (nYn)
nAn input
nYn output
tPHL tPLH
GND
VI
VMVM
VMVM
VOH
VOL
90 %
10 % 10 %
90 %
tTHL tTLH mgu781
* L |1' r H = Q:
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 8 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Enable and disable times
001aae014
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
nYn output
LOW-to-OFF
OFF-to-LOW
nYn output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Type Input Output
VMVMVXVY
74AHC240 0.5VCC 0.5VCC VOL + 0.3 V VOH 0.3 V
74AHCT240 1.5 V 0.5VCC VOL + 0.3 V VOH 0.3 V
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 9 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC240 VCC 3.0 ns 15 pF, 50 pF 1 kopen GND VCC
74AHCT240 3.0 V 3.0 ns 15 pF, 50 pF 1 kopen GND VCC
:‘fi Emmy #g :HHHHHHHHH E©
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 10 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
12. Package outline
Fig 8. Package outline SOT163-1 (SO20)
H H HHDHLH H HH- E© W
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 11 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Fig 9. Package outline SOT360-1 (TSSOP20)
€ ,, ,,,,,,, 4 ,,,,,,,, , L ‘ + i D L * D ‘ +‘ F7: 8 \ \ WW P fiwwuupuum T 3 ‘ E4 15 ****** §”**:;E / mnmmMnnm \
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 12 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Fig 10. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
C
B
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 13 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charge Device Model
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT240 v.4 20130925 Product data sheet - 74AHC_AHCT240 v.3
Modifications: •Figure 5 and 6 have been made visible (errata).
74AHC_AHCT240 v.3 20111108 Product data sheet - 74AHC_AHCT240 v.2
Modifications: •Legal pages updated.
74AHC_AHCT240 v.2 20101126 Product data sheet - 74AHC_AHCT240 v.1
74AHC_AHCT240 v.1 20100111 Product data sheet - -
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 14 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
15. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com salesaddresses®nx9£0m
74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 25 September 2013 15 of 16
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AHC240; 74AHCT240
Octal buffer/line driver; inverting; 3-state
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 September 2013
Document identifier: 74AHC_AHCT240
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16