Datenblatt für NTGS4111P, NVGS4111P von onsemi

MOSFET ON Semiconductor@
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 4
1Publication Order Number:
NTGS4111P/D
NTGS4111P, NVGS4111P
MOSFET – Power, Single,
P-Channel, TSOP-6
-30 V, -4.7 A
Features
•Leading −30 V Trench Process for Low RDS(on)
•Low Profile Package Suitable for Portable Applications
•Surface Mount TSOP−6 Package Saves Board Space
•Improved Efficiency for Battery Applications
•NV Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•Pb−Free Package is Available
Applications
•Battery Management and Switching
•Load Switching
•Battery Protection
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS −30 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain Cur-
rent (Note 1)
Steady
State
TA = 25°CID−3.7 A
TA = 85°C−2.7
t ≤5 s TA = 25°C−4.7
Power Dissipation
(Note 1)
Steady
State
TA = 25°C PD1.25 W
t ≤5 s 2.0
Continuous Drain Cur-
rent (Note 2)
Steady
State
TA = 25°CID−2.6 A
TA = 85°C−1.9
Power Dissipation
(Note 2)
TA = 25°C PD0.63 W
Pulsed Drain Current tp = 10 msIDM −15 A
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS−1.7 A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
THERMAL RESISTANCE RATINGS
Rating Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1) RqJA 100 °C/W
Junction−to−Ambient – t ≤5 s (Note 1) RqJA 62.5
Junction−to−Ambient – Steady State (Note 2) RqJA 200
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
3
4
1256
P−Channel
http://onsemi.com
TSOP−6
CASE 318G
STYLE 1
MARKING DIAGRAM &
PIN ASSIGNMENT
1XX M G
G
XX = Specific Device Code
M = Date Code*
G = Pb−Free Package
Source
4
Drain
6
Drain
5
3
Gate
1
Drain
2
Drain
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
−30 V
68 mW @ −4.5 V
38 mW @ −10 V
RDS(on) TYP
−4.7 A
ID MAX
V(BR)DSS
See detailed ordering and shipping information ion page 6 of
this data sheet.
ORDERING INFORMATION
NTGS4111P, NVGS4111P
http://onsemi.com
2
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.006 in sq).
NTGS4111P, NVGS4111P
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−30 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ−17 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = −24 V
TJ = 25°C−1.0 mA
TJ = 125°C−100
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−1.0 −3.0 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ5.0 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = −10 V, ID = −3.7 A 38 60 mW
VGS = −4.5 V, ID = −2.7 A 68 110
Forward Transconductance gFS VDS = −10 V, ID = −3.7 A 6.0 S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1.0 MHz,
VDS = −15 V
750 pF
Output Capacitance COSS 140
Reverse Transfer Capacitance CRSS 105
Total Gate Charge QG(TOT)
VGS = −10 V, VDD = −15 V,
ID = −3.7 A
15.25 32 nC
Threshold Gate Charge QG(TH) 0.8
Gate−to−Source Charge QGS 2.6
Gate−to−Drain Charge QGD 3.4
SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4)
Turn−On Delay Time td(ON)
VGS = −10 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
9.0 17 ns
Rise Time tr9.0 18
Turn−Off Delay Time td(OFF) 38 85
Fall Time tf22 45
SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4)
Turn−On Delay Time td(ON)
VGS = −4.5 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
11 20 ns
Rise Time tr15 28
Turn−Off Delay Time td(OFF) 28 56
Fall Time tf22 50
DRAIN − SOURCE DIODE CHARACTERISTICS
Characteristic Symbol Test Condition Min Typ Max Unit
Forward Diode Voltage VDS VGS = 0 V,
IS = −1.0 A
TJ = 25°C−0.76 −1.2 V
TJ = 125°C−0.60
Reverse Recovery Time tRR
VGS = 0 V
dIS/dt = 100 A/ms, IS = −1.0 A
17 40 ns
Charge Time ta9.0
Discharge Time tb8.0
Reverse Recovery Charge QRR 8.0 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
‘ ‘ ID: .3,7A V55: .mv
NTGS4111P, NVGS4111P
http://onsemi.com
4
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−8 V
100°C
0
12
9
1.20.8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
3
0
0.4
Figure 1. On−Region Characteristics
1
10
2.523
8
7
1
1.5
0
4.5
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
15
1000
100
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−IDSS, LEAKAGE CURRENT (nA)
−ID, DRAIN CURRENT (AMPS)
210
0.1
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−VGS, GATE VOLTAGE (VOLTS)
−50 0−25 25
1.0
0.5
50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
100000
5
TJ = −55°C
VGS = 0 V
75 150
ID = −3.7 A
VGS = −10 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.5
−3 V
25 30
−3.2 V
−3.4 V
−4.5 V
0.2
1.6 2
10000
468
0
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
2.0
0.05
−ID, DRAIN CURRENT (AMPS)
0.1
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −4.5 V
4.0
6
9
10
3.0
TJ = 25°C
VGS = −10 V
TJ = 100°C
TJ = 150°C
3.5 4
2
3
4
5
6
VDS ≥ −10 V
9357
TJ = 25°C
ID = −3.7 A
20
11
8
2
5
10
7
1
4
3.22.82.4 3.6 4
−3.6 V
−3.8 V
−4 V
−4.2 V
−10V
−6 V
−5 V
−5.5 V
5
11
12
V55 : -20 V SINGLE PULSE : 25:0 —— — RDSM LIMIT — THERMAL LIMIT
NTGS4111P, NVGS4111P
http://onsemi.com
5
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
VDS = 0 V VGS = 0 V
010 10
1400
600
400
200
0
30
−GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
0
8
2
0
Qg, TOTAL GATE CHARGE (nC)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Coss
Ciss
Crss
ID = −3.7 A
TJ = 25°C
1000
128
4
6
QGS
5
800
12
−VGS −VDS
15 4
0.9
1
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
−IS, SOURCE CURRENT (AMPS)
TJ = 25°C
1.00.40.3
10
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
Figure 10. Diode Forward Voltage vs. Current
5
1200
216
QT
0.5 0.80.6
0.1
0.7
0.1 1 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.01
100
−ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
VGS = −20 V
SINGLE PULSE
TC = 25°C
1 ms
100 ms
dc
0.1
1
10 ms
1300
500
300
100
900
700
1100
20 25
Ciss
Crss
10
0
20
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
6101411395371115
QGD
VGS
VDS
1.1
VGS = 0 V
TJ = −55°C
TJ = 150°C
TJ = 100°C
0.0001
1
1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03
0.1
D = 0.5
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
Figure 11. FET Thermal Response
0.2
0.1
0.05
0.02
0.01
Single Pulse
t, TIME (s)
0.01
0.001
1E−06 1E−05 1E−041E−07
NTGS4111P, NVGS4111P
http://onsemi.com
6
Table 1. ORDERING INFORMATION
Part Number
Marking
(XX) Package Shipping†
NTGS4111PT1 TG SC−88 3000 / Tape & Reel
NTGS4111PT1G TG SC−88
(Pb−Free)
3000 / Tape & Reel
NVGS4111PT1G VTG SC−88
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
0N Semiwndudw" Q‘flflé‘ i A alcfl' [Us 353 M; T T r/ 025 BSC STVLE I STVLE 2 SIVLE a PTNT DRAW PTNT EMTTTER2 PTNT ENABLE 2 DRAW 2 eAsET 2 we a GATE 3 COLLECTORT 5 REOOST o SOURCE 4 EMTTTERT 4 V1 5 DRAW 5 BASEZ 5 an s DRAW 5 COLLECTORZ a VmA STVLE 7 STVLE a SIVLE 9 PTNT COLLECIOR PTNT Vbus PTNT LOWVOLTAGEGA 2 COLLECIOR 2 mu 2 DRAWN a BASE 3 mm 5 SOURCE o NTG 4 D(nu|)v 4 DRAWN 5 COLLECIOR 5 DTeuTT 5 DRAWN s EMITTER 5 GND 5 HTGH vouAGEGA STVLE Ta STVLE T4 SIVLE T5 PTNT GATET PTNT ANODE PTNT ANODE 2 SOURCEZ 2 SOURCE 2 SOURCE a GATE2 a GATE 5 GATE o DRATNz 4 cAmoDETDRATN 4 DRAWN 5 souRcET 5 cAmoDETDRATN 5 we 6 DRATNT 5 cAmoDETDRATN a CATHODE RECOMMENDED SOLDERING;OO:RINT‘ TD D D G Ll u I: u LI memj 4 e “For addTIIonal TnTonaTTon on our Pn—FTee sTTaTegy and soldenng aeTaTls, please aowmoaa me ON SemTconducmr Sonenng and Mounting Techniques Relevance Manuals SOLDERRM/D ON SeeTeeeeeeTeT and J "seemees eT SeeTeeeeeeTeT eeeeeeems Teeesees. Lu: ees ON SemeeeeeeTeT eT .Ts seeseeees e The Wee sees eeeTe. eTeeT eewesT ON SeeTeeeeeeTeT esew Tee "gm Te meke eeeeees lehuul We. neTee Te eey emeees neee ON Semeeeeeee eeees ee wenem. TeeTeseeTeTee eT eeeTeeTee Teeeeme Tee seTTeTsTTnY eT Te e.eeeeTs TeT any eeeTeeTeT weese eees ON SemeeeeeeTeT essme eey T.eTeTT.TY eTeee eeTeT The eeeTeeTTen e. eT any meeeeTeT em. and seeeTTeeTTy eeeTeTes enY see eTT T.eTe.T.TY eeTeeeewTseeT TeTTeTTen speeeT eeeseeeeeTeT e. eeTeesTeT eemeees ON SeeTTmeeeeTeT eees ne. ewe any Tes eeeeT TTs eeTeeT .Tems The
TSOP−6
CASE 318G−02
ISSUE V
DATE 12 JUN 2012
SCALE 2:1
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
23
456
D
1
e
b
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
XXX MG
G
XXX = Specific Device Code
A =Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
GENERIC
MARKING DIAGRAM*
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
1
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
XXXAYWG
G
1
STANDARDIC
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
DIM
A
MIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
−
0°10°
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
L
C
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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TSOP−6
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1
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