Datenblatt für NTHD4102P von onsemi

MOSFET Optimized for Battery and Land Management Applications in Portable Equipment such as MP3 Players, Cell Phones, and PDAs U Charge Control in Battery Chargers U Buck and Boost Converters MAXIMUM RATINGS (TJ : 25cc unless otnerwrse notedt 0N Semiconductor® Stresses exceedlng Maxlmum Ralrngs may damage the devlce. Maxlmum Ratrngs are stress ratings only. Funetrenal operatron above the Recommended ooeratrng Condltlons Is not rmotied, Extended exposure to stresses above the Recommended Operalrng Condltlons may attect deyrce relraoitity. t Surface mounted on FR4 hoard usmg t rn so pad Slze (Cu area : t.t27 In so It oz] lncludlng traces) n Semlcunduclur Cnmvunenl: measures LLC 20H May, 2019 — Rev. 5 Parameter Symbol Value Unlt Drain—m-Somce Voltage V555 —20 v Gate-Io—Source Voltage vGS 15.0 v Contrnuous Drarn TA : 25°C ID —2 9 A PIN C t N I 1 SI (1 Stat ""9" ( ° 9 ) ea y 6 TA : 55°C 41 CONNECTIO (S105 TA:25°C —41 Dr 0 Power nrssroatron Steady State PD t.t w mm 1) TA : 25°C D t S 10 S 2.1 I Pulsed Drarn tP : to us tDM 45 A D2 Current D Operatrng Junction and Storage Temperature T J, —55 to °C 2 TSTG ‘50 Souroe Cunem (Body Drede) t5 4 t A Lead Temperature Ior Soldering TL 250 cc Purposes (1/8“ trem ease Ior to s) THERMAL RESISTANCE RATINGS Parameter Symbol Max Unlt Juncllon —to—Amoienl, Steady State (Note It tta “C/W lunetron—te—Amnienl, (5 ms (Note It R‘W‘ so Pubhcation Oldel Num NTH D410
© Semiconductor Components Industries, LLC, 2011
May, 2019 − Rev. 6
1Publication Order Number:
NTHD4102P/D
NTHD4102P
MOSFET – Dual, P-Channel,
ChipFET
-20 V, -4.1 A
Features
•Offers an Ultra Low RDS(ON) Solution in the ChipFET Package
•Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
•Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
•Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
•Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
•Pb−Free Package is Available
Applications
•Optimized for Battery and Load Management Applications in
Portable Equipment such as MP3 Players, Cell Phones, and PDAs
•Charge Control in Battery Chargers
•Buck and Boost Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −20 V
Gate−to−Source Voltage VGS "8.0 V
Continuous Drain
Current (Note 1) Steady State
TA = 25°CID−2.9 A
TA = 85°C−2.1
t ≤10 s TA = 25°C−4.1
Power Dissipation
(Note 1)
Steady State
TA = 25°C
PD1.1 W
t ≤10 s 2.1
Pulsed Drain
Current
tp =10 msIDM −16 A
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS−1.1 A
Lead Temperature for Soldering
Purposes (1/8” from case for 10 s)
TL260 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient, Steady State (Note 1)
RqJA
113 °C/W
Junction−to−Ambient, t ≤10s (Note 1) 60
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces)
MARKING
DIAGRAM
1
2
3
4
S1
G1
S2
G2
D1
D1
D2
D2
PIN
CONNECTIONS
8
7
6
5
5
6
7
81
2
3
4
C7 M
G
C7 = Specific Device Code
M = Month Code
G= Pb−Free Package
P−Channel MOSFET
Device Package Shipping†
ORDERING INFORMATION
NTHD4102PT1 ChipFET
S1
G1
D1
P−Channel MOSFET
S2
G2
D2
V(BR)DSS RDS(ON) TYP ID MAX
−20 V
64 mW @ −4.5 V
−4.1 A
85 mW @ −2.5 V
120 mW @ −1.8 V
NTHD4102PT1G ChipFET
(Pb−Free) 3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
ChipFET
CASE 1206A
STYLE 2
http://onsemi.com
NTHD4102P
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(Br)DSS VGS = 0 V, ID = −250 mA−20 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(Br)DSS/TJ−15 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V
VDS = −16 V
TJ = 25°C−1.0 mA
TJ = 85°C−5.0
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "8.0 V "100 nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−0.45 −1.5 V
Gate Threshold Temperature Coefficient VGS(TH)/TJ2.7 mV/°C
Drain−to−Source On Resistance RDS(ON) VGS = −4.5 V, ID = −2.9 A 64 80 mW
VGS = −2.5 V, ID = −2.2 A 85 110
VDS = −1.8 V, ID = −1.0 A 120 170
Forward Transconductance gFS VDS = −10 V, ID = −2.9 A 7.0 S
CHARGES, CAPACITANCES, AND GATE RESISTANCE
Input Capacitance CISS VGS = 0 V, f = 1.0 MHz,
VDS = −16 V
750 pF
Output Capacitance COSS 100
Reverse Transfer Capacitance CRSS 45
Total Gate Charge QG(TOT)
VGS = −4.5 V, VDS = −16 V,
ID = −2.6 A
7.6 8.6 nC
Gate−to−Source Charge QGS 1.3
Gate−to−Drain Charge QGD 2.6
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(ON)
VGS = −4.5 V, VDD = −16 V,
ID = −2.6 A, RG = 2.0 W
5.5 10 ns
Rise Time tr12 25
Turn−Off Delay Time td(OFF) 32 40
Fall Time tf23 35
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, IS = −1.1 A −0.8 −1.2 V
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 1.0 A
20 40 ns
Charge Time ta 15
Discharge Time tb 5
Reverse Recovery Charge QRR 0.01 mC
2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
TJ: 100x:
NTHD4102P
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TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
125°C
0
10
5
8
632
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
6
2
0
1
Figure 1. On−Region Characteristics
0 1.512
6
4
2
0.5
0
2.5
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.04
6
0.08
0
Figure 3. On−Resistance vs. Drain Current and
Gate Voltage
−ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Drain−to−Source Leakage Current
vs. Voltage
TJ = 25°C
0.2
23
TJ = −55°C
TJ = 25°C
VGS = −4.5 V
4
25°C
−1.4 V
−1.6 V
−2.4 V
−1.8 V
78
0.12
VGS = −10 V to −2.8 V
38
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10000
0.1
−IDSS, LEAKAGE (nA)
VGS = −4.5 V
1000
1
100
VGS = −2.5 V
46
4
8
0.16
5
TJ = 100°C
TJ = 125°C
2
9
7
5
1
3
4
9
5
3
1
7
−50 0−25 25
1.3
1.1
0.9
0.7
0.5
50 12510075 150
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.5
VGS = 0 V
3 3.5
0.02
0.06
0.18
0.1
0.14
4
57
vGS : .a v SINGLE PULSE : 25°C — Rnsmm LIM‘T
NTHD4102P
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4
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
010
4
600
400
200
08
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
032
4
1
0
Qg, TOTAL GATE CHARGE (nC)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Coss
Ciss
Crss
ID = −2.7 A
TJ = 25°C
1000
65
2
3
Q2
Q1
101
10
1
100
RG, GATE RESISTANCE (OHMS)
t, TIME (ns)
VDD = −10 V
ID = −1.0 A
VGS = −4.5 V
1000
800
5
td(off)
td(on)
tf
tr
−VGS −VDS
6418
0.9
0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
−IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
1.20.50.4
1
5
Figure 6. Capacitance Variation
Figure 7. Gate−to−Source and Drain−to−Source
Voltage vs. Total Gate Charge
Figure 8. Resistive Switching Time Variation
vs. Gate Resistance
Figure 9. Diode Forward Voltage vs. Current
Figure 10. Maximum Rated Forward Biased
Safe Operating Area
0.1 1 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.01
100
−ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
VGS = −8 V
SINGLE PULSE
TC = 25°C
1 ms
100 ms
dc
10 ms
2
700
500
300
100
900
7
QT
100
0.6 0.80.7
0.1
1
12 14 16 18 20
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
3
4
1.0 1.1
10 ms
DIM MOM a 4* A ‘ as mm a u 30 u m2 2 u ‘5 u was n 3 Us a ‘20 z ‘ 55 u was a 55 as .125 Esc el 55 as uzz Esc L uza U35 042 mm x mm mm AWE: ‘80 x ‘90 x 200 mm \ ums‘ 007s "WWI (32 on Semicanduanrand J a nanypmflumj harem some
NTHD4102P
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5
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE K
Basic
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b0.25 0.30 0.35 0.010
c0.10 0.15 0.20 0.004
D2.95 3.05 3.10 0.116
E1.55 1.65 1.70 0.061
e0.65 BSC
e1 0.55 BSC
L0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
HE
5°NOM
q5°NOM
HE
q
RESET
0.457
0.018
2.032
0.08
0.65
0.025
PITCH
0.66
0.026 ǒmm
inchesǓ
2.362
0.093
1
8X
8X
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NTHD4102P/D
ChipFET is a trademark of Vishay Siliconix.
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