Datenblatt für TPS92510 von Texas Instruments

i TEXAS Q INSTRUMENTS 9
VIN
TPS92510
PDIM
EN
COMP
PH
RT/CLK
VSENSE
TSENSE BOOT
GND
UDG-11042
Pad
T
TPS92510
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1.5-A Constant-Current Buck Converter for High-Brightness LEDs
with Integrated LED Thermal Foldback
Check for Samples: TPS92510
1FEATURES DESCRIPTION
2• 3.5-V to 60-V Input Voltage Range The TPS92510 is a 60-V, 1.5-A peak current-mode
• Integrated 200-mΩHigh-Side MOSFET step-down converter with an integrated high-side
• 200 mV Internal Voltage Reference MOSFET. It is specifically designed for driving high-
brightness LEDs with a constant current. The tight-
• ±3% LED Current Accuracy tolerance, 200-mV internal reference voltage reduces
• 100 kHz to 2.5 MHz Switching Frequency power dissipation in the current-sense resistor. A
Range dedicated pulse width modulation input pin allows
• Dedicated PWM Dimming Input linear control of the light output.
• LED Thermal Foldback The TPS92510 integrates a thermal foldback feature
• Adjustable UVLO that reduces the average output current to ensure
that the sensed LED temperature never exceeds a
• Overcurrent Protection specific value, improving the reliability of the overall
• Over-Temperature Protection system. An integrated frequency synchronization
• MSOP-10 (DGQ) PowerPAD™ Package feature allows a reduction of unwanted beat-
frequencies in multi-string applications and simplifies
APPLICATIONS EMI filtering. The adjustable input voltage UVLO
feature accommodates the various deep discharge
• Street Lighting levels of multiple battery types.
• Emergency Lighting The TPS92510 includes cycle-by-cycle overcurrent
• General Illumination protection, and thermal shutdown protection. It is
• Industrial and Commercial Lighting available in a 10-pin MSOP PowerPAD™ package.
• MR16 LED Bulbs
SIMPLIFIED APPLICATION
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
TPS92510
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE DEVICE
TJPACKAGE PINS OUTPUT SUPPLY MINIMUM QUANTITY NUMBER
Tube 80 TPS92510DGQ
PowerPAD Plastic
–40°C to 150°C 10
Small Outline (MSOP) Tape and Reel 2500 TPS92510DGQR
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted).
VALUE UNIT
MIN MAX
VIN –0.3 65
PDIM, EN –0.3 6
Input voltage BOOT 73 V
VSENSE, TSENSE, COMP –0.3 3
RT/CLK –0.3 3.6
BOOT-PH 8
Output voltage PH –0.6 65 V
PH, 10-ns Transient –2 65
Voltage Difference PAD to GND ±200 mV
EN 100 μA
BOOT 100 mA
VSENSE 10 μA
Source current Current
PH A
Limit
RT/CLK 100 μA
Current
VIN A
Limit
Sink current
COMP, VSENSE, EN 100 μA
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 V
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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THERMAL INFORMATION
TPS92510
THERMAL METRIC(1) MSOP UNITS
10 PINS
θJA Junction-to-ambient thermal resistance(2) 66.7
θJCtop Junction-to-case (top) thermal resistance(3) 45.8
θJB Junction-to-board thermal resistance(4) 37.5 °C/W
ψJT Junction-to-top characterization parameter(5) 1.8
ψJB Junction-to-board characterization parameter(6) 37.1
θJCbot Junction-to-case (bottom) thermal resistance(7) 15.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PWM dimming input frequency 120 1000 Hz
PWM dimming minimum on-time 10 µs
VVIN Input voltage 3.5 60 V
tON(min) High-side MOSFET on-time 350 ns
IL(pk-pk) Peak-to-peak inductor current 150 mA
TJOperating junction temperature –40 125 °C
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ELECTRICAL CHARACTERISTICS
–40°C ≤TJ≤125°C, VVIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VVIN Input voltage 3.5 60 V
VUVLO Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
IVINSD Shutdown supply current VEN = 0 V, TA=25°C, 3.5 V ≤VVIN ≤60 V 1.3 4 μA
IVIN Non-switching supply current VVSENSE = 210 mV, TA=25°C 305 400
ENABLE AND UVLO (EN PIN)
VEN Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.10 1.22 1.34 V
VREF threshold +50 mV –3.8
Input current μA
VREF threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
3.5 ≤VVIN ≤60 V, TJ= 25°C 194 200 206
VREF Voltage reference mV
3.5 ≤VVIN ≤60 V, -40°C ≤TJ≤125°C 190 210
HIGH-SIDE MOSFET
VVIN = 3.5 V, (VBOOT– VPH) = 3 V 300
RDS(on) On-resistance mΩ
VVIN = 12 V, (VBOOT– VPH) = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
gM(ea) Error amplifier transconductance gain –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μA/V
Error amplifier dc gain VVSENSE = 0.2 V 10 kV/V
Error amplifier bandwidth 2.7 MHz
Error amplifier source/sink VCOMP = 1 V, 100 mV overdrive ±27 μA
COMP to switch current transconductance 10.5 A/V
CURRENT LIMIT
Current limit threshold TJ= 25°C 2.5 4.0 A
THERMAL SHUTDOWN
TSD Thermal shutdown 150 °C
Thermal shutdown hysteresis 20 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RRT = 200 kΩ450 581 720 kHz
Switching frequency range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
Phase loop (PLL) lock-in time fSW = 500 kHz 100 μs
PWM DIMMING (PDIM)
VIH High-level input voltage 1.35 1.55 V
VIL Low-level input voltage 0.75 0.90 V
THERMAL FOLDBACK PROTECTION (TSENSE)
PWM ramp valley voltage 0 100 250 mV
PWM ramp peak voltage 1.75 1.95 2.15 V
PWM frequency 3.5 6.0 9.0 kHz
Current source 70 95 125 μA
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1
65
10
2
3
74
8
9
RT/CLK
BOOT
PDIM
EN
VIN
TSENSE
PH
VSENSE
COMP
GND
TPS92510
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DEVICE INFORMATION
TPS92510
MSOP-10
(Top View)
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 O minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 8 O components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2-V to disable. Float to enable. Adjust the input
EN 3 I undervoltage lockout with two resistors.
GND 9 – Ground
PWM dimming input pin. The duty cycle of the PWM signal linearly controls the average current output of the
PDIM 4 I converter.
PH 10 O The source of the internal high-side MOSFET.
PowerPAD Pad – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to program the switching frequency. If the pin is pulled above the PLL upper
RT/CLK 5 I threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin becomes a high impedance clock input to the internal PLL. If the clocking edges stop,
the internal amplifier is re-enabled and the mode returns to the resistor-programmed function.
Temperature fold-back pin. An NTC thermistor connected from this pin to ground provides a thermal
TSENSE 6 I feedback to decrease the average LED current as the sensed LED temperature increases. It is
recommended to bypass this pin with a capacitor with a value of 0.01 µF (or larger) to GND.
VIN 2 I Input supply voltage, 3.5 V to 60 V.
VSENSE 7 I Inverting node of the transconductance (gM) error amplifier.
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l TEXAS INSTRUMENTS I [1 f, , [1 \E D 3: 5D x
UDG-11043
EN
TSENSE
VSENSE
PDIM
COMP
RT/CLK
PH
3
8
7
4
6
1.25 V
0.9 µA
2.9 µA
200 mV
Enable
Comparator
Current
Sense
1.35 V
+
+
1 µA
+
Error Amplifier
5.9 kHz
+
100 µA
PDIM
Comparator
Temperature
Comparator
Thermal
Shutdown
VIN
UVLO
Shutdown Logic
S
Slope
Compensation
Oscillator
with PLL
Logic
and
PWM
Latch
+
R R
Q
SR
R
BOOT
UVLO
5
PowerPAD
BOOT
Charge
10
9 GND
VIN2
BOOT1
2 V
0 V
COMP S/H
EA
Clamp
TPS92510
TPS92510
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FUNCTIONAL BLOCK DIAGRAM
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0
500
2000
2500
0 25 50 200
Timing and External Clock (RT/CLK ) Resistance (kW)
Switching Frequency (kHz)
75 100 125 150 175
1000
1500
VIN = 12 V
TJ=25°C
High Frequency Range
0
100
400
500
200 400 1200
Timing and External Clock (RT/CLK) Resistance (kW)
Switching Frequency (kHz)
600 800 1000
200
300
VIN = 12 V
TJ=25°C
Low Frequency Range
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Switch Current Limit (A)
VIN = 12 V
G000
560
565
570
575
580
585
590
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Switching Frequency (kHz)
VIN = 12 V
RRT = 200 kΩ
G000
0
100
200
300
400
500
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Static D−to−S On−Resistance (mΩ)
BOOT–PH = 3 V
BOOT–PH = 6 V
VIN = 12 V
G000
190
192
194
196
198
200
202
204
206
208
210
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Voltage Reference (mV)
VIN = 12 V
G000
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TYPICAL CHARACTERISTICS
Figure 1. On-Resistance vs. Junction Temperature Figure 2. Reference Voltage vs. Junction Temperature
Figure 3. Switch Current vs. Junction Temperature Figure 4. Switching Frequency vs. Junction Temperature
Figure 5. Switching Frequency vs. RT/CLK Resistance Figure 6. Switching Frequency vs. RT/CLK Resistance
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−1.10
−1.08
−1.06
−1.04
−1.02
−1.00
−0.98
−0.96
−0.94
−0.92
−0.90
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enable Current (µA)
VIN = 12 V
VEN_THRESHOLD –50 mV
G000
−4.20
−4.15
−4.10
−4.05
−4.00
−3.95
−3.90
−3.85
−3.80
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enable Current (µA)
VIN = 12 V
VEN_THRESHOLD +50 mV
G000
0 10 60
Input Voltage (V)
20 30 40 50
0
0.5
1.5
2.0
Quiescent Current (mA)
1.0
TJ=25°C
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Shutdown Quiescent Current (µA)
VIN = 12 V
G000
200
250
300
350
400
450
500
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Error Amplifier Transconductance (µA/V)
VIN = 12 V
G000
1.10
1.15
1.20
1.25
1.30
1.35
1.40
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enable Threshold (V)
VIN = 12 V
G000
TPS92510
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TYPICAL CHARACTERISTICS (continued)
Figure 7. Error Amplifier Transconductance vs. Junction Figure 8. Enable Voltage vs. Junction Temperature
Temperature
Figure 9. Shutdown Quiescent Current vs. Junction Figure 10. Shutdown Quiescent Current vs. Input Voltage
Temperature
Figure 11. Enable Current vs. Junction Temperature Figure 12. Enable Current vs. Junction Temperature
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l TEXAS INSTRUMENTS N \/ V V V/\/\/\/VV\ ‘v/V/V Time Time
1.90
1.95
2.00
2.05
2.10
2.15
2.20
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
BOOT−PH UVLO (V)
G000
2.50
2.51
2.52
2.53
2.54
2.55
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Input Voltage UVLO (V)
G000
300
302
304
306
308
310
312
314
316
318
320
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Input Supply Current (µA)
VIN = 12 V
VVSENSE = 210 mV
G000
200
210
220
230
240
250
260
270
280
290
300
310
320
330
0 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Input Supply Current (µA)
TJ = 25°C
VVSENSE = 210 mV
G000
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TYPICAL CHARACTERISTICS (continued)
Figure 13. Input Supply Current vs. Junction Temperature Figure 14. Input Supply Current vs. Input Voltage
Figure 15. BOOT-PH UVLO vs. Junction Temperature Figure 16. Input Voltage UVLO vs. Junction Temperature
Figure 17. PDIM Rising Figure 18. PDIM Falling
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TPS92510
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TYPICAL CHARACTERISTICS (continued)
Figure 19. Enable Rising Figure 20. Enable Falling
Figure 21. TSENSE and High-Side MOSFET
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( )
( )
DELAY
0.7 V R1 32 A
t C1
32 A
- ´ m
= ´ m
TPS92510
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OVERVIEW
The TPS92510 is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. To
improve performance during line and load transients the device implements a constant frequency, peak-current
mode control which reduces output capacitance and simplifies external frequency compensation design. The
wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the
output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The
device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch
turn on to a falling edge of an external system clock.
The TPS92510 has a default start up voltage of approximately 2.5 V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device
operates. The operating current is 138 μA when not switching and under no load. When the device is disabled,
the supply current is 1.3 μA.
The integrated 200 mΩhigh-side MOSFET allows for high efficiency power supply designs capable of delivering
1.5 A of continuous current to a load. The TPS92510 reduces the external component count by integrating the
boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the
BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET
off when the boot voltage falls below a preset threshold. The TPS92510 can operate at high duty cycles because
of the boot UVLO.
DETAILED DESCRIPTION
Start-Up
The VIN and EN UVLO conditions must be satisfied before the TPS92510 is allowed to switch. When the EN pin
is held low the device enters a low-power shutdown mode, and some internal circuits are deactivated to conserve
power. When EN returns high these circuits are enabled, which results in a delay of approximately 50 µs (typical)
before switching starts. During start-up the TPS92510 operates in a minimum pulse width mode, which is an
open-loop control. At the start of each switching cycle the internal oscillator initiates a SET pulse. The high-side
MOSFET turns on with a minimum pulse width of 300 ns (typical), independent of the COMP voltage. The device
does not pulse skip. While operating in minimum pulse width mode the LED bypass capacitor is being charged,
causing an in-rush current. Also, the COMP voltage begins to rise as the error amplifier output current charges
the compensation network. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured
to be out of saturation and to have sufficient gain to regulate the loop. The TPS92510 then transitions from
minimum pulse width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop
control of the system. The gain of the error amplifier quickly increases the duty cycle, which causes the output
voltage to increase. Once the output voltage approaches the forward voltage of the LED string the LED current
quickly begins to increase until it reaches regulation.
There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error
amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the
compensation components to 0.7 V. This delay can be approximated as shown in Equation 1 .
where
• C1 is the integrator capacitor from COMP to GND
• R1 is the resistor in series with the integrator capacitor (1)
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( )
( )
HYS EN ESD HYS ESD START
HYS EN
V V I1 R I R V
R1
I V
´ - ´ - ´ ´
=´
( )
OUT
IN
SW ON min
V
V
f t
=´
( )
IN SW
ON min
PEAK
SENSE
OUT
V t f
I
LR
C
´ ´
=
+
TPS92510
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DETAILED DESCRIPTION (continued)
The peak in-rush current can be calculated to a first approximation using Equation 2.
where
• tON(min) is the minimum on-time and can be between 200 ns and 300 ns (2)
Minimum Pulse Width Limitations
The TPS92510 is designed to output a minimum pulse width during each switching cycle of 280 ns (typical). The
control loop cannot regulate the system to an on-time less than this amount, and it does not skip pulses. When
attempting to operate below the minimum on-time the system loses regulation and the LED current increases.
This puts a practical limitation on the system operating conditions, as shown in Equation 3.
where
• VOUT equals the forward voltage of the LED string plus the reference voltage (3)
The system can avoid this operating condition by limiting the maximum input voltage as shown in Equation 3 . If
the input voltage cannot be limited due to application, then the switching frequency can be lowered, or the output
voltage increased. This region of operation typically occurs with high input voltages, high operating frequencies,
and low output voltages (one LED).
Enable and Adjusting Undervoltage Lockout
The TPS92510 is enabled when the VIN pin voltage is above 2.5 V and when the EN pin voltage is above 1.25
V. The VIN pin voltage threshold has no hysteresis. Figure 22 shows how to use the EN pin to adjust the input
voltage UVLO to a higher threshold and increase the input voltage hysteresis. The EN pin has an internal pull-up
current source, I1, of 0.9 µA that provides a default ON state when the EN pin is floating. Once the EN pin
voltage exceeds 1.25 V, an additional 2.9 µA of hysteresis, IHYS, is added. This additional current provides some
input voltage hysteresis. Use Equation 4 to set the external hysteresis for the input voltage. Use Equation 5 to
set the input start voltage. When the EN pin is held low the internal regulators are shut down and the device
enters a low-power mode. In addition, the error amplifier output discharges the COMP voltage through a diode
path to GND.
Figure 22. Adjustable Undervoltage Lockout (UVLO)
(4)
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( ) ( )
1
1.0888
RT
206033
SW
R k
f kHz
æ ö
ç ÷
è ø
W
æ ö
ç ÷
=ç ÷
è ø
( ) ( ) ( )
1.0888
RT
SW
206033
R k
f kHz
W =
ESD
R 10k= W
HYS START STOP
V V V= -
( )
( )
( )
( ) ( ) ( )
EN ESD HYS
STOP EN HYS ESD
R1 V R I1 I
R2
V V I1 I R1 R
´ - ´ +
=- + + ´ +
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DETAILED DESCRIPTION (continued)
(5)
(6)
(7)
Fixed Frequency PWM Control
The TPS92510 uses an adjustable, fixed-frequency, peak current mode control. Each switching cycle an internal
oscillator initiates the turn-on of the MOSFET. The LED current flows through the sense resistor and develops
the feedback voltage on the VSENSE pin. The error amplifier output (COMP pin) is compared to the high-side
MOSFET current. When the MOSFET current reaches the level set by the COMP pin voltage the MOSFET is
turned off.
Slope Compensation
The TPS92510 adds a compensating ramp to the MOSFET current signal. The slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS92510 is adjustable over a wide range from approximately 100 kHz to 2500
kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor
to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use
Equation 8 or the curves in Figure 5 or Figure 6. To reduce the solution size one typically sets the switching
frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum
controllable on time should be considered. The minimum controllable on time limits the maximum operating input
voltage.
XXX
(8)
(9)
Synchronization to an External System Clock (RT/CLK)
The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square
wave to the RT/CLK pin through the circuit network as shown in Figure 23. The square wave amplitude must
transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and
an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of
the PH is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit default
frequency is set by connecting the resistor from the RT/CLK pin to ground should the synchronization signal turn
off. It is recommended to use a frequency set resistor connected as shown in Figure 23 through a 50-Ωresistor
to ground.
The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac
couple the synchronization signal through a 470-pF ceramic capacitor to RT/CLK pin and a 4-kΩseries resistor.
The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in
applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK
threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is
removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then increases or
decreases the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS TeK mm mun/Isl: blx Acqs [ T l um: um Chl 2.00V w |0.0V mm 500m Chl \ soomv L 4 zuumA w
IL
EXT
PH
UDG-11052
RT/CLK
TPS92510
5
RRT Phase-Lock
Loop (PLL)
50 W
4 kW
470 pF
External
Clock
Source
TPS92510
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
www.ti.com
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor then sets the switching frequency. It is not
recommended that a system transition from PLL mode to resistor mode repeatedly during operation. When the
PLL loses the external clock input the default 150-kHz switching frequency creates long on-times, which result in
higher inductor ripple currents. This can lead to inductor saturation if the system is not designed to operate at this
frequency. Figure 24, shows the device synchronized to an external system clock in continuous conduction mode
(CCM).
Figure 23. Synchronizing to a System Clock Figure 24. Plot of Synchronizing in CCM
Error Amplifier
The TPS92510 error amplifier is a transconductance amplifier. It compares the VSENSE voltage to the internal
0.2-V voltage reference. The transconductance (gm) of the error amplifier is 310 μA/V. The frequency
compensation components are connected from the COMP pin to ground.
Voltage Reference and Output Current
The internal voltage reference is accurate to ± 5% over temperature. The LED current is programmed with a
sense resistor from the VSENSE pin to GND. It is recommended to use a 1% tolerance resistor, or better.
PWM Dimming
The TPS92510 incorporates a PWM dimming input pin, which directly controls the enable/disable state of the
internal gate driver. When PDIM is low, the gate driver is disabled. The PDIM pin has a 1-µA pull-up current
source, which creates a default ON state when the PDIM pin is floating. When PDIM goes low and the gate
driver shuts off, and the LED current quickly reduces to zero.
The TPS92510 uses a sample-and-hold switch on the error amplifier output. During the PDIM off-time the COMP
voltage remains unchanged. Also, the error amplifier output is internally clamped low. These techniques help the
system recover to its regulation duty cycle quickly.
Duty Cycle and Bootstrap Voltage (BOOT)
The TPS92510 requires a small 0.1-µF ceramic capacitor between the BOOT and PH pins to provide the gate
drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET turns
off, and the freewheeling diode conducts. A ceramic capacitor with an X7R or X5R dielectric and a minimum
voltage rating of 10 V is recommended.
14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5
TSENSE Voltage (V)
Normalized LED Current (%)
G000
TPS92510
www.ti.com
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
The TPS92510 is designed to operate up to 100% duty cycle as long as the BOOT to PH voltage is greater than
2.1V. If the BOOT capacitor voltage drops below 2.1 V, then the BOOT UVLO circuit turns off the MOSFET,
which allows the BOOT capacitor to be refreshed. The current required from the BOOT capacitor to keep the
MOSFET on is quite low. Therefore, many switching cycles occur before the BOOT capacitor is refreshed. In this
way, the effective duty cycle of the converter is quite high.
Attention must be taken in maximum duty cycle applications which experience extended time periods with little or
no load current. When the voltage across the BOOT capacitor falls below the 2.1 V UVLO threshold, the high-
side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1 V. The output capacitor then decays until the difference between the input voltage and
output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output current is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
Overcurrent Protection
An overcurrent fault condition is unlikely. It can be the result of a shorted sense resistor, or a direct short from
VOUT to GND. In either case, the voltage at the VSENSE pin is zero, and this causes the COMP pin voltage to
rise. When VCOMP reaches approximately 2.2 V it is internally clamped, and functions as a MOSFET current limit.
The TPS92510 limits the MOSFET current to 4 A (typical). If the shorted condition persists the TPS92510
junction temperature increases. If it increases above 150°C, the thermal shutdown protection is activated.
LED Thermal Foldback Protection
The TPS92510 implements a thermal foldback protection to limit the LED temperature in case of a system
failure, such as an incorrectly programmed LED current, a poor thermal design or increasing thermal impedance
over time. A 100-µA current source generates a voltage across an NTC resistor that is located near the LED
load. When the NTC voltage drops below 2 V at the TSENSE pin (due to excessive LED temperature) the device
begins to modulate the converter at a frequency of 5.9 kHz. The more the NTC voltage drops, the longer the off-
time of the converter. Therefore, the delivered output power is reduced until the NTC cools, the TSENSE voltage
(VTSENSE) increases, and the system no longer requires reduced output power. The thermal foldback protection
slowly reduces the output power, as a function of the thermal time constant. Thermal foldback protection is
intended for protection only. It is not intended to be used as a regulation feature. During thermal foldback the
error amplifier output is internally clamped low, and the COMP sample-and-hold switch is open, preserving the
COMP pin voltage.
Figure 25 shows the thermal foldback linearity.
Figure 25. Thermal Foldback Linearity
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS fl TVS 4 %
2
4
3
8
10
VIN
TPS92510
PDIM
EN
COMP
PH
5
7
RT/CLK
VSENSE
6
TSENSE
1
BOOT
9
GND
UDG-11108
Pad
TVS
RESD
TPS92510
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
www.ti.com
Over-Temperature Fault Protection
When the TPS92510 junction temperature reaches 150ºC, the driver immediately disables the high-side
MOSFET. The COMP sample-and-hold switch closes, and the COMP pin internally clamps low until the junction
temperature drops by approximately 20ºC. At this time, the COMP clamp is removed and the driver attempts to
regulate.
APPLICATION INFORMATION
Open LED Fault Protection
An open circuit can be the result of an open LED or an open wire connection. In either case, the voltage at the
VSENSE pin becomes zero, and this causes the COMP pin voltage to rise, commanding wide duty cycles. The
output voltage eventually rises to the input voltage. This is a safe operating mode, provided that the output
capacitors are rated for the input voltage potential.
As shown in Figure 26, a transient voltage suppressor (TVS) device from VOUT to GND, or a diode from VOUT to
the VIN pin can be used to clamp the L-C resonant output voltage ringing caused by the inductor and the output
capacitor at the moment the LED string opens, particularly at high-input voltage and high-output voltage
operating conditions. The TVS should have a voltage rating greater than the maximum output voltage, so that it
does not conduct under normal operation. Either of these devices can be used to limit the output voltage to safe
levels during an open LED fault.
If the current sense resistor also opens, current attempts to flow into the ESD structure of the VSENSE pin. To
prevent damage to the device, a series resistor (RESD) on the VSENSE pin can be used to limit this current. The
VSENSE pin has an internal, 8-V clamp, and the continuous current should be limited to a maximum of 20 mA.
Figure 26. Output Voltage Clamp
An external overvoltage protection circuit consisting of VZand RZshown in Figure 27, can be applied to the
VSENSE pin to regulate the output voltage to less than the input voltage potential.
16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS 0 EE EX XX XX
UDG-11110
COUT
RESR
RSENSE
LBUCK
DI
LLIMIT
2
short
VIN
10
PH
2
4
3
8
10
VIN
TPS92510
PDIM
EN
COMP
PH
5
7
RT/CLK
VSENSE
6
TSENSE
1
BOOT
9
GND
UDG-11109
Pad
RZ
VZ
RESD
TPS92510
www.ti.com
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
Figure 27. Output Voltage Limiter
Shorted LED(s) Fault Protection
Some LEDs fail to a shorted state. It is unlikely that multiple LEDs fail short simultaneously. If a bypass capacitor
is in parallel with the LED string it is charged to the LED string forward voltage. When one or more LEDs
instantaneously short, the bypass capacitor senses a voltage transient from the initial LED string voltage to
something less, depending on the number of LEDs that are now shorted. The voltage change across the
capacitor causes the capacitor to discharge some energy in the form of a transient current through the LED
string. This current flows from the bypass capacitor through the LED string, but not through the current sense
resistor. Therefore, the TPS92510 does not sense the fault event, and does not respond to it. The peak transient
current is a function of the change in forward voltage due to the shorted LED(s), and the dynamic resistance of
the LED string at the moment the short occurs. This current can be substantial, and may require a protection
circuit as shown in Figure 28, unless the LEDs can survive the transient current. After the LED has shorted the
error amplifier continues to regulate the programmed LED current at the new, lower output voltage.
Figure 28. LED Current Limiter Due to a Shorted LED
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS
3
SW
M
IN OUT SW
117 10 L f
f
V V 3 f L
´ ´ ´
=
- + ´ ´
( ) ( )
( ) ( ) ( ) ( )
6
M SENSE
C2O 6
M M V OUT
167 10 f R Gi s
G s
1 17 10 f Gi s He s f G Gi s Z s
-
-
´ ´ ´ ´
=
+ ´ ´ ´ ´ - ´ ´ ´
F
LIMIT
DYNAMIC ESR
OUT
V
I
L
R R
C
D
D =
+ +
TPS92510
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
www.ti.com
Equation 10 shows how to reduce the peak transient current (ΔI) by adding a series inductance (LLIMIT).
Typically, the bypass capacitor (COUT) is used to reduce the high-frequency ripple current through the LED.
Adding inductance into this path is counter productive. Alternatively, the buck inductance, or switching frequency
can be increased to achieve a lower LED ripple current. In this way, the output capacitor can be reduced in
value, which allows LLIMIT to be smaller. The end result of low LED ripple current can still be achieved. Reducing
the output capacitor (COUT) does not reduce the magnitude of the transient current, but it does reduce the settling
time.
(10)
Open Current Sense Resistor Fault Protection
An open current sense resistor is unlikely, but may be caused by a failing resistor, an open solder joint, or an
open PCB trace. As the current sense resistor opens, the output voltage quickly rises due to the energy stored in
the inductor, similar to an open LED fault. Therefore, it is necessary to clamp the output voltage, either with a
TVS to GND or a diode from VOUT to VIN. It is also necessary to use a current limiting resistor on the VSENSE
pin. Otherwise, the output voltage spike causes the VSENSE voltage to break down its internal ESD structure.
The ESD device should be limited to 20 mA. In this condition, the converter attempts to regulate the output
current through the ESD structure, which results in a very low regulated current. Typically, the output voltage
overcharges and holds the VSENSE voltage high within a few switching cycles. The device stops switching, and
there is a long off-time between consecutive start-up attempts. The consecutive attempts result in lower peak
current through the ESD structure than the initial event.
Shorted Output Fault
A shorted output fault is considered rare, because the system does not require any single component from VOUT
to GND. Therefore, a single component failure cannot cause this fault condition. If this failure mode were to occur
it would most likely be due to a mechanical short, or a foreign object. In the unlikely event of this failure mode,
the TPS92510 responds in the following way.
With the output voltage shorted directly to ground the COMP voltage saturates high, because the feedback
voltage is zero. The controller would naturally command wide duty cycle PH pulses. However, as soon as the
gate driver turns on, very quickly an overcurrent event is detected and the PH pulse is truncated. This results in
minimum on-time pulses at the PH node. Depending upon the impedance of the short, large currents can build
up in the inductor, which naturally raises the junction temperature of the TPS92510. The over-temperature
protection feature protects the device.
Control-to-Output Transfer Function
The TPS92510 converter uses peak current mode control in order to regulate the average LED current. Slope
compensation is utilized internally to eliminate sub-harmonic oscillations over a wide range of operating duty
cycles. To properly compensate the closed-loop system the control to output gain characteristics must be
calculated. The control to output transfer function is shown in Equation 11.
where
• RSENSE is the LED current sense resistance (11)
where
• L is the output inductance
• fSW is the switching frequency in Hz (12)
18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS \ / CO
( ) DC
M ea
CO
g G
C1 2 f
´
=´ p ´
( )
( )
IN M SENSE
DC
IN M DCR SENSE LED M IN V SENSE LED
167 V f R
G
17 V f 1000000 R R R f V G R R
´ ´ ´
=´ ´ + ´ + + - ´ ´ ´ +
OUT F
V V n 0.2 V= ´ +
LED ESR
OUT
OUT SENSE
LED ESR
OUT
1
R R
s C
Z R
1
R R
s C
æ ö
´ +
ç ÷
´
è ø
= +
æ ö
+ + ç ÷
´
è ø
OUT
V3
IN SW
V
G
117.2 10 L V f
=
´ ´ ´ ´
( ) ( )
2
2
SW SW
s s
He s 1
2 f f
= + +
- ´ p ´
( ) IN
ESR LED
OUT
DCR SENSE
ESR LED
OUT
V
Gi s
1
R R
s C
s L R R
1
R R
s C
=æ ö
+ ´
ç ÷
´
è ø
´ + + + æ ö
+ +
ç ÷
´
è ø
TPS92510
www.ti.com
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
where
• RDCR is the DC resistance of the output inductor
• COUT is the output capacitance.
• RESR is the equivalent series resistance of the output capacitor
• RLED is the dynamic resistance of the entire LED string and is dependent upon the LED current (ILED) (13)
(14)
(15)
(16)
where
• VFis the forward voltage of an individual LED
• n is the number of LEDs in the string (17)
The control-to-output transfer function can be understood best by plotting it using a computer aided mathematics
program such as Mathcad. The resulting plot shows that the control to output DC gain is typically very low, which
can also be computed with Equation 18.
(18)
Compensating the Loop
The control-to-output transfer function is compensated by the error amplifier in order to accomplish the following
functions.
• more DC gain is required for better current regulation
• more bandwidth is desired for better PWM dimming and transient performance
• adequate phase margin is needed for system stability
The TPS92510 utilizes peak current mode control, which effectively reduces the power stage’s second order pole
to a first order pole. A single pole power stage can be compensated easily with a single capacitor from COMP to
GND, which forms a dominate pole. This compensation topology is referred to as Type I and is shown in
Figure 29. In most applications, a Type I compensation network can be used when a low cross-over frequency
(typically less than 10 kHz) is desired. Equation 19 calculates the required capacitance from the COMP pin to
GND in order to achieve a desired cross-over frequency (fCO), knowing the DC gain of the power stage (GDC).
Type I Compensation
(19)
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS 9W s x C1 CO
C1
C2
10
=
CO
1
R1
2 K f C1
=
p ´ ´ ´
( ) DC
M ea
CO
g G
C1 2 f
´
=´ p ´
COUT
RESR
RSENSE
VREF
C1
COMP VSENSE
VOUT
RLED
UDG-11210
gM
+
COUT
RESR
RSENSE
VREF
C1
C2
R1
COMP VSENSE
VOUT
RLED
UDG-11211
gM
+
( )
( )
( ) ( )
EA M ea 2
1 s R1 C1
G g
s C1 C2 s R1 C1 C2
+ ´ ´
=
´ + + ´ ´ ´
( )
M ea
EA
g
Gs C1
=´
CL C2O EA
G G G= ´
TPS92510
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
www.ti.com
The compensated loop gain is equal to the control to output transfer function multiplied by the error amplifier
transfer function as shown in Equation 20.
(20)
(21)
The transconductance gain of the error amplifier (gM(ea)) is 310 µA/V.
Type II Compensation
When using PWM dimming, it is beneficial to extend the loop bandwidth beyond 10 kHz. In this case, a Type II
compensation topology can be used. The gain of the error amplifier changes as shown in Equation 22.
(22)
Figure 29. Type I Compensation Figure 30. Type II Compensation
Knowing the desired cross-over frequency (fCO) and the power stage DC dain (GDC), the error amplifier can be
easily compensated with a Type II network. Equation 23 through Equation 25 show some simple approximations
for the compensation values. Capacitor C1 has the biggest influence on the cross-over frequency and low-
frequency gain. Resistor R1 creates a zero in the error amplifier transfer function, which improves the phase
margin particularly near the cross-over frequency. Capacitor C2 creates a high-frequency pole to reduce gain
beyond the cross-over frequency.
(23)
where
• K is a multiplier of the desired cross-over frequency (24)
(25)
For reference, the error amplifier zero frequency and high-frequency pole equations are shown in Equation 26
through Equation 27.
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TPS92510
TEXAS INSTRUMENTS 2 R1 C1
EA(pole)
1 1
fC1 C2 2 R1 C2
2 R1 C1 C2
= @
´p ´ ´
æ ö
p ´ ´ ç ÷
+
è ø
EA(zero)
1
f2 R1 C1
=
p ´ ´
TPS92510
www.ti.com
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
(26)
(27)
The compensation equations above are given as a guideline. It is strongly recommended to verify the closed loop
response for adequate gain and phase margin by directly measuring the circuit. The value of C1 is inversely
proportional to the closed loop bandwidth of the system: as C1 decreases, the loop bandwidth increases. If the
measured loop gain is too high, increase the value of C1 and recalculate R1 and C2. For a Type II compensation
network a good cross-over frequency target is between 10 kHz and 50 kHz, but should not exceed one-fifth (1/5)
of the switching frequency (fSW).
When calculating the value of R1 the K multiplier must be chosen. Typically, this value is between 1.5 and 4. A
good starting value for K is 2 or 3. This places the error amplifier zero frequency two or three times higher than
the desired cross-over frequency. When measuring the loop response, if additional phase margin is needed the
K value can be reduced, resulting in a larger R1 value. Alternatively, as the K multiplier increases beyond 4 the
value of R1 becomes so small that its benefit to phase margin becomes insignificant, and the error amplifier
performance begins to approach a Type I network.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS92510
l TEXAS INSTRUMENTS
TPS92510
SLUSAE4A –JANUARY 2012–REVISED AUGUST 2012
www.ti.com
Changes from Original (JANUARY 2012) to Revision A Page
• Changed corrected y-axis label on Figure 8 ......................................................................................................................... 8
• Changed corrected test condition on Figure 14 .................................................................................................................... 9
22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TPS92510
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS92510DGQ ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 92510
TPS92510DGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 92510
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS92510DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS92510DGQR HVSSOP DGQ 10 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
HVSSOP - 1.1 mm max height
TM
PowerPADDGQ 10
PLASTIC SMALL OUTLINE
3 x 3, 0.5 mm pitch
4224775/A
MECHANICAL DATA POWS’DAD‘V F ASTC SMN cm NF WES- n nu nnean dimewsors are n mflhmeiers 5. Ma drawing is suaject :a mange w‘wam whee. C hay c'vrcnsm s :0 nut mu‘ucu mo‘d flash my pmlrusm'v nut (u cxccu: 0.15 D TMs package ‘5 deswgned (c be so‘devec ta a - vmu‘ pad an Lne bouvd ?e'e' (o Techmcu‘ finer, Puwevpmi Ther'rcHy Enhanced Package, Texas \rstmmenis .wte'umre Nu smooz far \Mormahon regardirg reco'r‘rrerded board \uyout. 'ms document is avaname at wwwncam , See the uddwtmnu‘ «we n he Procud Data 92 a far aetans 'egc'cmq «he expose: (herma‘ pad ieamras c'vd fl'mensmns FcHs within JEDEC worm vuriahun EH PowerPAD is a trademavk MTexas \nsuuments. J5 TEXAS INSTRUMENTS wwwxi .com
THERMAL PAD MECHANICAL DATA DGQ (SiPDsoiciO) PowerPADTM PLASTiC SMALL OUTLiNE THERMAL lNFORMATlON This PowerPAprackage incorporates an exposed thermal pad that is designed to be attached to a printed circuit board (PCB), The thermal pad must be soldered directly to the PCB. After soldering. the PCB can be used as a heatsink. In addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively. can be attached to a special heatsink structure designed into the PCB‘ This design optimiIes the heat transfer from the integrated circuit (lC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerFAD Thermally Enhanced Package, Texas Instruments Literature No. SLMAOOZ and Application Brief. PowerPAD Made Easy, Texas instruments Literature Nod SLMAOO4‘ Both documents are available at www.ti.cam. The exposed thermal pad dimensions for this package are shown in the following illustration 10 6 L48 i A if i 7 Vi Exposed Thermal Pad 2,i8 i,48 Top View Exposed Thermal Pad Dimensions 420532474/H 12/14 NOTE: A. All linear dimensions are in millimeters FowerPAD is a trademark at Texas instruments fl} TEXAS INSTRUMENTS www.ti .com
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