Datenblatt für ICS853S014AGILF(T) von Renesas Electronics Corporation

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‘DIDT. DATA SHEET ﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂ uuuuuuuuuu

DATA SHEET

Low Skew, 1-to-5, Differential-to-2.5V, 3.3V

LVPECL/ECL Fanout Buffer ICS853S014I

General Description

The ICS853S014I is a low skew, high performance 1-to-5, 2.5V/3.3V

Differential-to-LVPECL/ECL Fanout Buffer. The ICS853S014I has

two selectable clock inputs.

Guaranteed output and part-to-part skew characteristics make the

ICS853S014I ideal for those applications demanding well defined

performance and repeatability.

Features

•Five differential LVPECL/ECL outputs

•Two selectable differential LVPECL clock inputs

•PCLKx, nPCLKx pairs can accept the following

differential input levels: LVPECL, LVDS, CML, SSTL

•Maximum output frequency: 2GHz

•Output skew: 55ps (maximum)

•Part-to-part skew: 100ps (maximum)

•Propagation delay: 500ps (maximum)

•Additive phase jitter, RMS: 0.10ps (maximum)

•LVPECL mode operating voltage supply range:

VCC = 2.375V to 3.8V, VEE = 0V

•ECL mode operating voltage supply range:

VCC = 0V, VEE = -3.8V to -2.375V

•-40°C to 85°C ambient operating temperature

•Lead-free (RoHS 6) packaging

ICS853S014I

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm package body

G Package

Top View

Pin Assignment

Block Diagram

nQ0

nQ1

nEN

CLK_SEL

PCLK0

nPCLK0

CLK

Pulldown

Pullup/Pulldown

Pulldown

VBB

nQ2

nQ3

PCLK1

nPCLK1

Pulldown

Pullup/Pulldown

nQ4

nQ3

nQ2

nQ1

nQ0

nQ4

VCC

nEN

VCC

nPCLK1

PCLK1

VBB

nPCLK0

PCLK0

CLK_SEL

VEE

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Pin Description and Pin Characteristic Table

Table 1. Pin Descriptions

NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels.

3, 4 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels.

5, 6 Q2, nQ2 Output Differential output pair. LVPECL/ECL interface levels.

7, 8 Q3, nQ3 Output Differential output pair. LVPECL/ECL interface levels.

9, 10 Q4, nQ4 Output Differential output pair. LVPECL/ECL interface levels.

11 VEE Power Negative supply pin.

12 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects

PCLK0, nPCLK0 inputs. Single-ended LVPECL interface levels.

13 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.

14 nPCLK0 Input Pullup/

Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating.

15 VBB Output Bias voltage.

16 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.

17 nPCLK1 Input Pullup/

Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating.

18, 20 VCC Power Positive supply pins.

19 nEN Input Pulldown

Synchronizing clock enable. When LOW, clock outputs follow clock input. When

HIGH, Qx outputs are forced low, nQx outputs are forced high.

Single-ended LVPECL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

RPULLDOWN Input Pulldown Resistor 37 k

RVCC/2 Pullup/Pulldown Resistors 37 k

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as described in Table 3B.

Figure 1. nEN Timing Diagram

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section. Wiring the Differential Input to Accept Single-ended Levels.

Inputs Outputs

nEN CLK_SEL Selected Source Q0:Q4 nQ0:nQ4

1 0 PCLK0, nPCLK0 Disabled; Low Disabled; High

1 1 PCLK1, nPCLK1 Disabled; Low Disabled; High

0 0 PCLK0, nPCLK0 Enabled Enabled

0 1 PCLK1, nPCLK1 Enabled Enabled

Inputs Outputs

Input to Output Mode PolarityPCLK0 or PCLK1 nPCLK0 or nPCLK1 Q0:Q4 nQ0:nQ4

0 1 LOW HIGH Differential to Differential Non-Inverting

1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

←

→t

/2V

nEN

nPCLK[0:1]

PCLK[0:1]

nQ[0:4]

Q[0:4]

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C

Item Rating

Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V)

Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V)

Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V

Inputs, VI (ECL mode) 0.5V to VEE – 0.5V

Outputs, IO

Continuous Current

Surge Current

50mA

100mA

VBB Sink//Source, IBB ± 0.5mA

Operating Temperature Range, TA-40C to +85C

Package Thermal Impedance, JA 92.1C/W (0 mps)

Storage Temperature, TSTG -65C to 150C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Positive Supply Voltage 2.375 3.3 3.8 V

IEE Power Supply Current 68 mA

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C

NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50 to VCC – 2V.

NOTE 2: Single-ended input operation is limited. VCC  3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as VIH for the differential inputs.

NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.

Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C

NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50 to VCC – 2V.

NOTE 2: Common mode voltage is defined as VIH for the differential inputs.

NOTE 3: The VCMR and VPP levels should be such that input low voltage never goes below VEE.

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

VOH Output High Voltage; NOTE 1 2.175 2.275 2.50 2.225 2.295 2.495 2.22 2.295 2.485 V

VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V

VIH Input High Voltage (CLK_SEL, nEN) 2.075 2.36 2.075 2.36 2.075 2.36 V

VIL Input Low Voltage (CLK_SEL, nEN) 1.43 1.765 1.43 1.765 1.43 1.765 V

VBB

Output Voltage Reference;

NOTE 2 1.72 1.98 1.72 1.98 1.72 1.98 V

VCMR

Input High Voltage Common Mode

Range; NOTE 3 1.2 3.3 1.2 3.3 1.2 3.3 V

VPP

Peak-to-Peak Input Voltage;

NOTE 4 150 800 1200 150 800 1200 150 800 1200 mV

IIH

Input

High Current

PCLK0, PCLK1

nPCLK0, nPCLK1 150 150 150 µA

IIL

Input

Low Current

PCLK0, PCLK1 -10 -10 -10 µA

nPCLK0, nPCLK1 -150 -150 -150 µA

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

VOH Output High Voltage; NOTE 1 1.375 1.475 1.70 1.425 1.495 1.69 1.42 1.495 1.685 V

VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.86 0.64 0.735 0.85 V

VIH Input High Voltage (CLK_SEL, nEN) 1.275 1.56 1.275 1.56 1.275 1.56 V

VIL Input Low Voltage (CLK_SEL, nEN) 0.63 0.965 0.63 0.965 0.63 0.965 V

VCMR

Input High Voltage Common Mode

Range; NOTE 2 1.2 2.5 1.2 2.5 1.2 2.5 V

VPP

Peak-to-Peak Input Voltage;

NOTE 3 150 800 1200 150 800 1200 150 800 1200 mV

IIH

Input

High Current

PCLK0, PCLK1

nPCLK0, nPCLK1 150 150 150 µA

IIL

Input

Low Current

PCLK0, PCLK1 -10 -10 -10 µA

nPCLK0, nPCLK1 -150 -150 -150 µA

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C

NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50 to VCC – 2V.

NOTE 2: Single-ended input operation is limited. VCC  3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as VIH for the differential inputs.

NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.80 -1.075 -1.005 -0.805 -1.08 -1.005 -0.815 V

VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V

VIH Input High Voltage (CLK_SEL, nEN) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V

VIL Input Low Voltage (CLK_SEL, nEN) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V

VBB

Output Voltage Reference;

NOTE 2 -1.58 -1.32 -1.58 -1.32 -1.58 -1.32 V

VCMR

Input High Voltage Common

Mode Range; NOTE 3 VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V

VPP

Peak-to-Peak Input Voltage;

NOTE 4 150 800 1200 150 800 1200 150 800 1200 mV

IIH

Input

High Current

PCLK0, PCLK1

nPCLK0,

nPCLK1

150 150 150 µA

IIL

Input

Low Current

PCLK0, PCLK1 -10 -10 -10 µA

nPCLK0,

nPCLK1 -150 -150 -150 µA

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

AC Electrical Characteristics

Table 5. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C

NOTE: All parameters are measured at f  1GHz, unless otherwise noted.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

fMAX Output Frequency 2 2 2 GHz

tPD Propagation Delay; NOTE 1 250 425 300 450 350 500 ps

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section (ƒ = 156.25MHz,

12kHz - 20MHz)

0.06 0.10 0.07 0.10 0.08 0.10 ps

tsk(o) Output Skew; NOTE 2, 4 55 55 55 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 100 100 ps

tR / tF

Output

Rise/Fall Time 20% to 80% 70 220 80 220 90 220 ps

tSClock Enable Setup Time 100 50 100 50 100 50 ps

tHClock Enable Hold Time 200 140 200 140 200 140 ps

_ m _ — 400 \ — -110 \\ — -120 — .130 \ EL1 — .140 \h EL2— §=- mm... '- *V 7 450 10Hz 10on 1kHz 10kHz 100kHz 1MHz 30MHz

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "IFR2042 10kHz – 5.4GHz Low Noise Signal

Generator used as external input to an Agilent 8133A 3GHz Pulse

Generator".

Additive Phase Jitter @ 156.25MHz

12kHz to 20MHz = 0.07ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

_L>i_, 121.:

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information

LVPECL Output Load Test Circuit

Part-to-Part Skew

Output Rise/Fall Time

Differential Input Level

Output Skew

Propagation Delay

SCOPE

nQx

VEE

VCC

-1.8V to -0.375V

tsk(pp)

Part 1

Part 2

nQx

nQy

20%

80% 80%

20%

SWING

nQ0:nQ4

Q0:Q4

VEE

CMR

Cross Points

nPCLKx

PCLKx

tsk(o)

nQx

nQy

tPD

nQ0:nQ4

Q0:Q4

nPCLKx

PCLKx

VCC R0 Driver RS Ro+Rs=Zo vq: vg; R3 100 R1 1K Zn = 50 Ohm , V1 R4 100 R2 C1 1K O’VUF VCC + Receiver

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage V1= VCC/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V1in the center of the input voltage swing. For

example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2

value should be adjusted to set V1 at 1.25V. The values below are for

when both the single ended swing and VCC are at the same voltage.

This configuration requires that the sum of the output impedance of

the driver (Ro) and the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the input will

attenuate the signal in half. This can be done in one of two ways.

First, R3 and R4 in parallel should equal the transmission line

impedance. For most 50 applications, R3 and R4 can be 100. The

values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however VIL cannot be less

than -0.3V and VIH cannot be more than VCC + 0.3V. Though some

of the recommended components might not be used, the pads should

be placed in the layout. They can be utilized for debugging purposes.

The datasheet specifications are characterized and guaranteed by

using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

LVPECL Clock Input Interface

The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other

differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 3A to 3F show interface examples

for the PCLK/nPCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm the

driver termination requirements.

Figure 3A. PCLK/nPCLK Input Driven by an

Open Collector CML Driver

Figure 3C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 3E. PCLK/nPCLK Input Driven by an SSTL Driver

Figure 3B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 3D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

Figure 3F. PCLK/nPCLK Input Driven by a

3.3V LVDS Driver

LVPE

125Ω

84Ω

3.3V

Zo = 50Ω

PCLK

nPCLK

3.3V

LVPECL LVPECL

Input

PCLK

nPCLK

LVPECL

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

Zo = 50Ω

100Ω

CML Built-In Pullup

50Ω

100Ω - 200Ω

PCLK

VBB

nPCLK

3.3V LVPECL

3.3V

Zo = 50Ω

3.3V

LVPECL

Input

PCLK

nPCLK

VBB

3.3V

LVPECL

Input

3.3V

Zo = 50Ω

100Ω

LVDS

0.1µF

33v LVPECL "‘9‘“ R1 son ‘ — ‘Z EVOH‘VOLVch’gPJ ” Fm R2 son vCC , 2v RTT

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Recommendations for Unused Output Pins

Inputs:

PCLK/nPCLK Inputs

For applications not requiring the use of a differential input, both the

PCLK and nPCLK pins can be left floating. Though not required, but

for additional protection, a 1k resistor can be tied from PCLK to

ground.

LVCMOS Control Pins

All control pins have internal pulldown resistors; additional resistance

is not required but can be added for additional protection. A 1k

resistor can be used.

Outputs:

LVPECL Outputs

All unused LVPECL output pairs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 4A and 4B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination

84

3.3V

125

Zo = 50

LVPECL Input

3.3V

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Termination for 2.5V LVPECL Outputs

Figure 5A and Figure 5B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating 50

to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground

level. The R3 in Figure 5B can be eliminated and the termination is

shown in Figure 5C.

Figure 5A. 2.5V LVPECL Driver Termination Example

Figure 5C. 2.5V LVPECL Driver Termination Example

Figure 5B. 2.5V LVPECL Driver Termination Example

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

250Ω

62.5Ω

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

18Ω

–

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Schematic Example

This application note provides general design guide using

ICS853S014I LVPECL buffer. Figure 6 shows a schematic example

of the ICS853S014I LVPECL clock buffer. In this example, the input

is driven by an LVPECL driver. CLK_SEL is set at logic high to select

PCLK1, nPCLK1 input.

Figure 6. ICS853S014I Example LVPECL Clock Output Buffer Schematic

Zo = 50

R10

0. 1u

Zo = 50

0. 1u

0.1u

LVPECL Driv er

0. 1u

Zo = 50

R12 1K

IC S8 5301 4

1011

nQ0

nQ1

nQ2

nQ3

nQ4VEE

CLK_SEL

PCLK0

nPCLK0

VBB

PCLK1

VCC

nEN

VCC

nPCLK1

R11

3.3V

Zo = 50

3. 3V

Zo = 50

3. 3V

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS853S014I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853S014I is the sum of the core power plus the power dissipated due to the load.

The following is the power dissipation for VCC = 3.8V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 68mA = 258.4mW

• Power (outputs)MAX = 30.94mW/Loaded Output pair

If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW

Total Power_MAX (3.8V, with all outputs switching) = 258.4mW + 154.7mW = 413.1mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = JA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.413W * 92.1°C/W = 123°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection

JA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 92.1°C/W 86.5°C/W 83.0°C/W

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

T3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 7.

Figure 7. LVPECL Driver Circuit and Termination

To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V

(VCC_MAX – VOH_MAX) = 0.935V

• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V

(VCC_MAX – VOL_MAX) = 1.67V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.935V)/50] * 0.935V = 19.92mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.67V)/50] * 1.67V = 11.02mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW

VOUT

VCC

VCC - 2V

50Ω

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Reliability Information

Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP

Transistor Count

The transistor count for ICS853S014I is: 407

Pin compatible with ICS853014

Package Outline and Package Dimensions

Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

JA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 92.1°C/W 86.5°C/W 83.0°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N20

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D6.40 6.60

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

0° 8°

aaa 0.10

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Ordering Information

Table 9. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

853S014AGILF ICS53S014AIL “Lead-Free” 20 Lead TSSOP Tube -40C to 85C

853S014AGILFT ICS53S014AIL “Lead-Free” 20 Lead TSSOP Tape & Reel -40C to 85C

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Revision History Sheet

Rev Table Page Description of Change Date

B T5 7 AC Characteristics Table - added Additive Phase Jitter max. spec. 9/1/10

CT6B

T7B

T8B

Added 20 Lead VFQFN proposed pin assignment.

Absolute Maximum Ratings - added 32 Lead VFQN Package Thermal Impedance.

Added VFQFN EPad Thermal Release section.

Added proposed 20 Lead VFQFN Thermal Resistance table.

Added proposed 20 Lead VFQFN theta ja table.

Added proposed 20 Lead VFQFN Package Outline and Dimensions.

Ordering Information Table added proposed 20 Lead VFQFN ordering information.

10/29/10

Deleted all “Proposed” VFQFN Package References throughout the datasheet.

Updated Application Note, Wiring the Differential Input Levels to Accept

Single-ended Levels.

Deleted Application Note, VFQFN EPAD Thermal Release Path.

Ordering Information Table - deleted tape & reel count; deleted VFQFN package

information.

5/23/13

‘DID'IZ www.|DT.com

ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

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