Datenblatt für 74LVC1G332-Q100 von Nexperia USA Inc.

Table 1. Ordering information nexpefla
74LVC1G332-Q100
3-input OR gate
Rev. 3 — 21 August 2018 Product data sheet
1. General description
The 74LVC1G332-Q100 provides one 3-input OR function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature
range
Name Description Version
74LVC1G332GW-Q100 -40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC1G332GV-Q100 -40 °C to +125 °C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC1G332-Q100 Table 2. Marking o: gamma 0013mm 1701534935 14LVC16332—Q100 E0 j E jog C j assmmz Table 3. Pin description
Nexperia 74LVC1G332-Q100
3-input OR gate
4. Marking
Table 2. Marking
Type number Marking code[1]
74LVC1G332GW-Q100 YG
74LVC1G332GV-Q100 YG
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
001aad933
B
AY
1
3
4
C
6
Fig. 1. Logic symbol
001aad934
4
1
3
6
1
Fig. 2. IEC logic symbol
001aad935
B
C
AY
Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
74LVC1G332-Q100
A C
GND
B Y
aaa-012462
1
2
3
6
VCC
5
4
Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74)
6.2. Pin description
Table 3. Pin description
Symbol Pin Description
A 1 data input
GND 2 ground (0 V)
B 3 data input
Y 4 data output
VCC 5 supply voltage
C 6 data input
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 2 / 11
74LVC1G332-Q100 Table 6. Recommended operating conditions
Nexperia 74LVC1G332-Q100
3-input OR gate
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input Output
ABCY
H X X H
X H X H
X X H H
LLLL
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +6.5 V
IIK input clamping current VI < 0 V -50 - mA
VIinput voltage [1] -0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
Active mode [1] -0.5 VCC + 0.5 VVOoutput voltage
Power-down mode; VCC = 0 V [1] -0.5 +6.5 V
IOoutput current VO = 0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 250 mW
Tstg storage temperature -65 +150 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
Active mode 0 - VCC VVOoutput voltage
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature -40 - +125 °C
VCC = 1.65 V to 2.7 V - - 20 ns/VΔt/ΔV input transition rise and fall rate
VCC = 2.7 V to 5.5 V - - 10 ns/V
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 3 / 11
74LVC1G332-Q100
Nexperia 74LVC1G332-Q100
3-input OR gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ[1] Max Min Max
Unit
VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC - V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V
VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V
VI = VIH or VIL
IO = -100 μA;
VCC = 1.65 V to 5.5 V
VCC - 0.1 - - VCC - 0.1 - V
IO = -4 mA; VCC = 1.65 V 1.2 - - 0.95 - V
IO = -8 mA; VCC = 2.3 V 1.9 - - 1.7 - V
IO = -12 mA; VCC = 2.7 V 2.2 - - 1.9 - V
IO = -24 mA; VCC = 3.0 V 2.3 - - 2.0 - V
VOH HIGH-level output
voltage
IO = -32 mA; VCC = 4.5 V 3.8 - - 3.4 - V
VI = VIH or VIL
IO = 100 μA;
VCC = 1.65 V to 5.5 V
- - 0.1 - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.3 - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V
VOL LOW-level output
voltage
IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V
IIinput leakage
current
VCC = 0 V to 5.5 V;
VI = 5.5 V or GND
- ±0.1 ±1 - ±1 μA
IOFF power-off leakage
current
VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±2 - ±2 μA
ICC supply current VCC = 1.65 V to 5.5 V;
VI = VCC or GND; IO = 0 A
- 0.1 4 - 4 μA
ΔICC additional supply
current
per pin; VCC = 2.3 V to 5.5 V;
VI = VCC - 0.6 V; IO = 0 A
- 5 500 - 500 μA
CIinput capacitance VCC = 3.3 V; VI = GND to VCC - 3 - - - pF
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 4 / 11
74LVC1G332-Q100 gamma Table 9 Table 9. Measurement points
Nexperia 74LVC1G332-Q100
3-input OR gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6.
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ[1] Max Min Max
Unit
A, B and C to Y; see Fig. 5 [2]
VCC = 1.65 V to 1.95 V 1.5 4.7 17.2 1.5 21.5 ns
VCC = 2.3 V to 2.7 V 1.0 3.0 6.2 1.0 7.8 ns
VCC = 2.7 V 1.0 3.0 6.0 1.0 7.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.6 4.8 1.0 6.2 ns
tpd propagation delay
VCC = 4.5 V to 5.5 V 1.0 1.9 3.5 1.0 4.4 ns
CPD power dissipation
capacitance
VI = GND to VCC; VCC = 3.3 V [3] - 12 - - - pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC
2 x fi x N + ∑(CL x VCC
2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL x VCC
2 x fo) = sum of outputs.
11.1. Waveforms and test circuit
001aad936
A, B, C input
Y output
tPLH
tPHL
GND
VI
VM
VM
VOH
VOL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 5. The input A, B and C to output Y propagation delays
Table 9. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5VCC 0.5VCC
2.3 V to 2.7 V 0.5VCC 0.5VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5VCC 0.5VCC
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 5 / 11
74LVC1G332-Q100 VE m mm» mam Table 10 Table 10. Test data
Nexperia 74LVC1G332-Q100
3-input OR gate
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance; should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 6. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr = tfCLRLtPLH, tPHL
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 6 / 11
74LVC1G332-Q100 Plastic surface-mounted package; 6 leads SOT363
Nexperia 74LVC1G332-Q100
3-input OR gate
12. Package outline
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
w BM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
1 32
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpc D Ee1HELpQ ywv
mm 0.1 0.30
0.20
2.2
1.8
0.25
0.10
1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
Fig. 7. Package outline SOT363 (SC-88)
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 7 / 11
74LVC1G332-Q100 Plastic surface-mounted package (TSOPB); 6 leads SOT457
Nexperia 74LVC1G332-Q100
3-input OR gate
Fig. 8. Package outline SOT457 (SC-74)
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 8 / 11
74LVC1G332-Q100 Table 11. Abbreviations Table 12. Revision history Table 7
Nexperia 74LVC1G332-Q100
3-input OR gate
13. Abbreviations
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G332_Q100 v.3 20180821 Product data sheet - 74LVC1G332_Q100 v.2
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74LVC1G332_Q100 v.2 20161209 Product data sheet - 74LVC1G332_Q100 v.1
Modifications: Table 7: The maximum limits for leakage current and supply current have changed.
74LVC1G332_Q100 v.1 20140526 Product data sheet - -
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 9 / 11
same In a deswgn on new sheet’ .5 exp‘amed in status of dewoem described 2 «ms documenl was publish es. The latest produd slam hugs waw nexg mm 74LVC1G332-Q100 sale 7 Max us of comma non ha me genera‘ ierms and continuous or m g llwww nexger cam/gm ellerms
Nexperia 74LVC1G332-Q100
3-input OR gate
15. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 10 / 11
74LVC1G332-Q100
Nexperia 74LVC1G332-Q100
3-input OR gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking.......................................................................... 2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description............................................................. 2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 5
12. Package outline.......................................................... 7
13. Abbreviations.............................................................. 9
14. Revision history..........................................................9
15. Legal information......................................................10
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 21 August 2018
74LVC1G332_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 3 — 21 August 2018 11 / 11