Datenblatt für TRF37A73 von Texas Instruments

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TRF37A73
SLASE39 –MAY 2014
TRF37A73 1-6000 MHz RF Gain Block
1 Features 3 Description
The TRF37A73 is packaged in a 2.00mm x 2.00mm
1• 1 MHz – 6000 MHz WSON with a power down pin feature making it ideal
• Gain: 12 dB for applications where space and low power modes
• Noise Figure: 4.5 dB are critical.
• Output P1dB: 14.5 dBm at 2000 MHz The TRF37A73 is designed for ease of use. For
• Output IP3: 28.5 dBm at 2000 MHz maximum flexibility, this family of parts uses a
common 3.3 V supply and consumes 55 mA. In
• Power Down Mode addition, this family was designed with an active bias
• Single Supply: 3.3 V circuit that provides a stable and predictable bias
• Stabilized Performance Over Temperature current over process, temperature and voltage
variations. For gain and linearity budgets the device
• Unconditionally Stable was designed to provide a flat gain response and
• Robust ESD: >1 kV HBM; >1 kV CDM excellent OIP3 out to 6000 MHz. For space
constrained applications, this family is internally
2 Applications matched to 50 Ω, which simplifies ease of use and
• General Purpose RF Gain Block minimizes needed PCB area.
• Consumer Device Information(1)
• Industrial PART NUMBER PACKAGE BODY SIZE (NOM)
• Utility Meters TRF37A73 WSON (32) 2.00mm x 2.00mm
• Low-cost Radios (1) For all available packages, see the orderable addendum at
• Cellular Base Station the end of the datasheet.
• Wireless Infrastructure Simplified Schematic
• RF Backhaul
• Radar
• Electronic Warfare
• Software-defined Radio
• Test and Measurement
• Point-to-Point/Multipoint Microwave
• Software Defined Radios
• RF Repeaters
• Distributed Antenna Systems
• LO and PA Driver Amplifier
• Wireless Data, Satellite, DBS, CATV
• IF Amplifier
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLASE39 –MAY 2014
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Table of Contents
7.2 Functional Block Diagram......................................... 8
1 Features.................................................................. 17.3 Feature Description................................................... 8
2 Applications ........................................................... 17.4 Device Functional Modes.......................................... 8
3 Description ............................................................. 18 Applications and Implementation ........................ 9
4 Revision History..................................................... 28.1 Application Information.............................................. 9
5 Pin Configuration and Functions......................... 38.2 Typical Application ................................................... 9
6 Specifications......................................................... 49 Power Supply Recommendations...................... 10
6.1 Absolute Maximum Ratings ...................................... 410 Layout................................................................... 11
6.2 Handling Ratings....................................................... 410.1 Layout Guidelines ................................................. 11
6.3 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 11
6.4 Thermal Information.................................................. 411 Device and Documentation Support ................. 12
6.5 Electrical Characteristics........................................... 511.1 Trademarks........................................................... 12
6.6 Timing Requirements................................................ 511.2 Electrostatic Discharge Caution............................ 12
6.7 Typical Characteristics.............................................. 611.3 Glossary................................................................ 12
7 Detailed Description.............................................. 812 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................... 8Information ........................................................... 12
4 Revision History
DATE REVISION NOTES
May 2014 * Initial release.
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1
2
3
4
VCC
NC
NC
RFIN
8
7
6
5
NC
PWDN
RFOUT
NC
Input
Match
Output
Match
TRF37A73
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SLASE39 –MAY 2014
5 Pin Configuration and Functions
DSG PACKAGE
(TOP VIEW)
Pin Functions
PIN DESCRIPTION
NAME NO.
VCC 1 DC Bias.
RFIN 2 RF input. Connect to an RF source through a DC-blocking capacitor. Internally matched to 50 Ω.
NC 3, 4, 6, 8 No electrical connection. Connect pad to GND for board level reliability integrity.
When high the device is in power down state. When LOW or NC the device is in active state. Internal pulldown
PWDN 5 resistor to GND.
RF Output and DC Bias (VCC). Connect to DC supply through an RF choke inductor. Connect to output load
RFOUT 7 through a DC-blocking capacitor. Internally matched to 50 Ω.
GND PowerPAD™ RF and DC GND. Connect to PCB ground plane.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Input voltage –0.3 3.6 V
Input Power 10 dBm
Operating virtual junction temperature range –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN MAX UNIT
TSTG Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC –1 1 kV
JS-001, all pins(1)
VESD Electrostatic discharge Charged device model (CDM), per JEDEC –1 1 kV
specification JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply Voltage, VCC 3 3.3 3.45 V
Operating junction temperature, TJ–40 125 °C
6.4 Thermal Information
DSG
THERMAL METRIC(1) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 79.3
RθJCtop Junction-to-case (top) thermal resistance 110
RθJB Junction-to-board thermal resistance 49 °C/W
ψJT Junction-to-top characterization parameter 6
ψJB Junction-to-board characterization parameter 49.4
RθJCbot Junction-to-case (bottom) thermal resistance 19.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
VCC = 3V3, TA= 25°C, PWDN = Low, LOUT = 100 nH, C1 = C2 = 1000 pF, ZS= ZL= 50 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC PARAMETERS
Total supply current 55 65 mA
ICC Power down current PWDN = High 125 µA
Pdiss Power dissipation 0.182 W
RF FREQUENCY RANGE
Frequency range 1 6000 MHz
fRF = 400 MHz 12.5 dB
fRF = 2000 MHz 12 dB
fRF = 3000 MHz 11.5 dB
G Small signal gain fRF = 4000 MHz 11.5 dB
fRF = 5000 MHz 11 dB
fRF = 6000 MHz 10.5 dB
OP1dB Output 1dB compression point At 2000 MHz 14.5 dBm
OIP3 Output 3rd order intercept point At 2000 MHz, 2-tone 10 MHz apart 28.5 dBm
NF Noise figure At 2000 MHz 4.5 dB
R(LI) Input return loss At 2000 MHz 16 dB
R(LO) Output return loss At 2000 MHz 15 dB
PWDN PIN
VIH High level input level 2 V
VIL Low level input level 0.8 V
IIH High level input current 30 µA
IIL Low level input current 1 µA
6.6 Timing Requirements
MIN TYP MAX UNIT
PWDN PIN
tON Turn-on Time 50% TTL to 90% POUT 0.6 µs
tOFF Turn-off Time 50% TTL to 10% POUT 1.4 µs
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15
17
19
21
23
25
27
29
31
33
35
0 1000 2000 3000 4000 5000 6000
OIP3 (dBm)
Frequency (MHz)
3.45V
3.3V
3.15V
3.0V
15
17
19
21
23
25
27
29
31
33
35
0 1000 2000 3000 4000 5000 6000
OIP3 (dBm)
Frequency (MHz)
±40C
25°C
85°C
7
8
9
10
11
12
13
14
15
16
17
0 1000 2000 3000 4000 5000 6000
OP1dB (dBm)
Frequency (MHz)
3.45V
3.3V
3.15V
3.0V
7
8
9
10
11
12
13
14
15
16
17
0 1000 2000 3000 4000 5000 6000
OP1dB (dBm)
Frequency (MHz)
±40C
25°C
85°C
7
8
9
10
11
12
13
14
15
16
17
0 1000 2000 3000 4000 5000 6000
Gain (dB)
Frequency (MHz)
3.45V
3.3V
3.15V
3.0V
7
8
9
10
11
12
13
14
15
16
17
0 1000 2000 3000 4000 5000 6000
Gain (dB)
Frequency (MHz)
±40C
25°C
85°C
TRF37A73
SLASE39 –MAY 2014
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6.7 Typical Characteristics
VCC curves Temp = 25°C Pin = –10 dBm Temp curves VCC = 3.3 V Pin = –10 dBm
Figure 1. Gain vs Frequency Figure 2. Gain vs Frequency
VCC curves Temp = 25°C Temp curves VCC = 3.3 V
Figure 3. OP1dB vs Frequency Figure 4. OP1dB vs Frequency
VCC curves Temp = 25°C Pin = –10 dBm/tone Temp curves VCC = 3.3 V Pin = –10 dBm/tone
Figure 5. OIP3 vs Frequency Figure 6. OIP3 vs Frequency
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l TEXAS INSTRUMENTS mm m 000MHz m a ODOGHZ)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10
20
20
-20
10
-10
5.0
-5.0
4.0
-4
.0
3.
0
-3
.0
2
.0
-2.0
1
.8
-1.8
1
.6
-1.6
1.4
-1.4
1.2
-1.2
1.0-1.0
0.9
-0.9
0.8
-0.8
0.7
-0.7
0
.6
-0.6
0
.5
-0.5
0
.4
-
0.4
0.3
-
0.3
0.2
-0.2
0.1
-0.1
freq (1.000MHz to 8.000GHz)
S(2,2)
S(1,1)
0
2
4
6
8
10
12
14
16
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1000 2000 3000 4000 5000 6000 7000 8000
S21 (dB)
Sxx (dB)
Frequency (MHz)
S22
S11
S12
S21
C016
45
48
51
54
57
60
0 1000 2000 3000 4000 5000 6000
Icc (mA)
Frequency (MHz)
3.45V
3.3V
3.15V
3.0V
45
48
51
54
57
60
0 1000 2000 3000 4000 5000 6000
Icc (mA)
Frequency (MHz)
±40C
25°C
85°C
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0 1000 2000 3000 4000 5000 6000
NF (dB)
Frequency (MHz)
3.45V
3.3V
3.15V
3.0V
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0 1000 2000 3000 4000 5000 6000
NF (dB
Frequency (MHz)
±40C
25°C
85°C
TRF37A73
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SLASE39 –MAY 2014
Typical Characteristics (continued)
VCC curves Temp = 25°C Temp curves VCC = 3.3 V
Figure 7. NF vs Frequency Figure 8. NF vs Frequency
VCC curves Temp = 25°C Temp curves VCC = 3.3 V
Figure 9. ICC vs Frequency Figure 10. ICC vs Frequency
VCC = 3.3 V Temp = 25°C 1 MHz to 8 GHz VCC = 3.3 V Temp = 25°C 1 MHz to 8 GHz
Data Taken with EVM and Bias T, De-embedded to DUT pin Data Taken with EVM and Bias T, De-embedded to DUT pin
Figure 11. Smith Chart – S11, S22 Figure 12. S22, S11, S12, S21
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Input
Match
Output
Match
Active Bias and
Temperature
Compensation
VCC VCC
Power Down
RF Input RF Output
TRF37A73
SLASE39 –MAY 2014
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7 Detailed Description
7.1 Overview
The device is a 3.3 V general purpose RF gain block. It is a SiGe Darlington amplifier with integrated 50 Ωinput
and output matching. The device contains an active bias circuit to maintain performance over a wide temperature
and voltage range. The included power down function allows the amplifier to shut down saving power when the
amplifier is not needed. Fast shut down and start up enable the amplifier to be used in a host of time division
duplex applications.
7.2 Functional Block Diagram
7.3 Feature Description
The TRF37A73 is a fixed gain RF amplifier. It is internally matched to 50 Ωon both the input and output. It is a
fully cascadable general purpose amplifier. The included active bias circuitry ensures the amplifier performance
is optimized over the full operating temperature and voltage ranges.
7.4 Device Functional Modes
7.4.1 Power Down
The TRF37A73 PWDN pin can be left unconnected for normal operation or a logic-high for disable mode
operation. For applications that use the power down mode, normal 5 V TLL levels are supported.
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l TEXAS INSTRUMENTS }—. FOut
1
2
3
4
VCC
RFIN
8
7
6
5
RFOUT
C5
C2
C1
DC Blocking
Capacitor DC Blocking
Capacitor
RF Choke
Inductor
DC Bypass
Capacitor
RF Bypass
Capacitors
RF In RF Out
VCC
C3
C4
L1
PWDN
TRF37A73
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SLASE39 –MAY 2014
8 Applications and Implementation
8.1 Application Information
The TRF37A73 is a wideband, high performance, general purpose RF amplifier. To maximize its performance,
good RF layout and grounding techniques should be employed.
8.2 Typical Application
The TRF37A73 device is typically placed in a system as illustrated in Figure 13.
Figure 13. Typical Application Schematic for TRF37A73
8.2.1 Design Requirements
Table 1. Design Parameters
PARAMETERS EXAMPLE VALUES
Input power range < 3 dBm
Output power < 18 dBm
Operating frequency range 1 — 6000 MHz
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0
2
4
6
8
10
12
14
16
18
20
22
0
2
4
6
8
10
12
14
16
18
20
22
0 1000 2000 3000 4000 5000 6000
NF (dB)
OP1dB (dBm)
Frequency (MHz)
OP1dB
NF
C017
TRF37A73
SLASE39 –MAY 2014
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8.2.2 Detailed Design Procedure
The TRF37A73 is a simple to use internally matched and cascadable RF amplifier. Following the recommended
RF layout with good quality RF components and local DC bypass capacitors will ensure optimal performance is
achieved. TI provides various support materials including S-Parameter and ADS models to allow the design to be
optimized to the user's particular performance needs.
8.2.3 Application Curve
Figure 14. OP1dB and NF vs Frequency
9 Power Supply Recommendations
All supplies may be generated from a common nominal 3.3 V source but should be isolated through decoupling
capacitors placed close to the device. The typical application schematic in Figure 13 is an excellent example.
Select capacitors with self-resonant frequency near the application frequency. When multiple capacitors are used
in parallel to create a broadband decoupling network, place the capacitor with the higher self-resonant frequency
closer to the device. Expensive tantalum capacitors are not needed for optimal performance.
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1
1
2
2
3
3
4
4
VCC
NC
NC
RFIN
8
8
7
7
6
6
5
5
NC
PWDN
RFOUT
NC
DC Blocking
Capacitor DC Blocking
Capacitor
RF Choke
Inductor
DC Bypass
Capacitor
DC Bypass
Capacitor
RF Bypass
Capacitors
RF In RF Out
VCC
Note: Ensure good RF microstrip or stripline traces are
used to connect the external components to the RF input
and output pins
Note: Ensure all components are connected to a common
RF/DC ground plane with plenty of vias
Note: Single DC bypass capacitor
can be used as long as it is close to
the pin 1 and is tied to the common
ground plane
TRF37A73
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SLASE39 –MAY 2014
10 Layout
10.1 Layout Guidelines
Good layout practice helps to enable excellent linearity and isolation performance. An example of good layout is
shown in Figure 15. In the example, only the top signal layer and its adjacent ground reference plane are shown.
• Excellent electrical connection from the PowerPAD™ to the board ground is essential. Use the recommended
footprint, solder the pad to the board, and do not include solder mask under the pad.
• Connect pad ground to device terminal ground on the top board layer.
• Verify that the return DC and RF current path have a low impedance ground plane directly under the package
and RF signal traces into and out of the amplifier.
• Ensure that ground planes on the top and any internal layers are well stitched with vias.
• Do not route RF signal lines over breaks in the reference ground plane.
• Avoid routing clocks and digital control lines near RF signal lines.
• Do not route RF or DC signal lines over noisy power planes. Ground is the best reference, although clean
power planes can serve where necessary.
• Place supply decoupling close to the device.
10.2 Layout Example
Figure 15. Layout
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11 Device and Documentation Support
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TRF37A73IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 A73I
TRF37A73IDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 A73I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
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PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TRF37A73IDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TRF37A73IDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TRF37A73IDSGR WSON DSG 8 3000 182.0 182.0 20.0
TRF37A73IDSGT WSON DSG 8 250 182.0 182.0 20.0
Pack Materials-Page 2
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GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WSON - 0.8 mm max heightDSG 8
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
4224783/A
,Cl, LII, 7|:|
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PACKAGE OUTLINE
C
8X 0.32
0.18
1.6 0.1
2X
1.5
0.9 0.1
6X 0.5
8X 0.4
0.2
0.05
0.00
0.8 MAX
A2.1
1.9 B
2.1
1.9
0.32
0.18
0.4
0.2
(0.2) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
ALTERNATIVE TERMINAL SHAPE
TYPICAL
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.25)
(1.6)
(1.9)
6X (0.5)
(0.9) ( 0.2) VIA
TYP
(0.55)
8X (0.5)
(R0.05) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.25)
8X (0.5)
(0.9)
(0.7)
(1.9)
(0.45)
6X (0.5)
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
45
8
METAL
SYMM 9
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