Datenblatt für AD5676 von Analog Devices Inc.

I: ANALOG DEVICES AD5676 noDAC+" Devices Table L Octal ml
Octal, 16-Bit
nano
DAC+ with SPI Interface
Data Sheet
AD5676
Rev. D Document Feedback
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FEATURES
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
20-lead, TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5676 is a low power, octal, 16-bit buffered voltage
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.62 V to 5.5 V logic.
Table 1. Octal nanoDAC+® Devices
Interface Reference 16-Bit 12-Bit
SPI Internal AD5676R AD5672R
External AD5676 Not applicable
I2C Internal AD5675R AD5671R
External AD5675 Not applicable
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: ±3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
12549-001
INPUT
REGISTER
INPUT
REGISTER
POWER-DOWN
LOGIC
GAIN x1/x2
POWER-ON RESET
DAC
REGISTER STRING
DAC 0
STRING
DAC 7
DAC
REGISTER
AD5676
GAIN GND
RSTSEL
SDO
SDI
LDAC
SYNC
SCLK
RESET
INPUT
REGISTER STRING
DAC 1
DAC
REGISTER
INPUT
REGISTER STRING
DAC 2
DAC
REGISTER
INPUT
REGISTER STRING
DAC 3
DAC
REGISTER
INPUT
REGISTER STRING
DAC 4
DAC
REGISTER
INPUT
REGISTER STRING
DAC 5
DAC
REGISTER
INPUT
REGISTER STRING
DAC 6
DAC
REGISTER
BUFFER
V
REF
V
OUT
0
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
V
OUT
5
V
OUT
6
V
OUT
7
V
DD
V
LOGIC
INTERFACE
LOGIC
Figure 1.
LDAC LDAC (RESE 1‘
AD5676 Data Sheet
Rev. D | Page 2 of 30
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
AC Characteristics ........................................................................ 6
Timing Characteristics ................................................................ 7
Daisy-Chain and Readback Timing Characteristics................ 8
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Digital-to-Analog Converter .................................................... 21
Transfer Function ....................................................................... 21
DAC Architecture ....................................................................... 21
Serial Interface ............................................................................ 22
Standalone Operation ................................................................ 23
Write and Update Commands .................................................. 23
Daisy-Chain Operation ............................................................. 23
Readback Operation .................................................................. 24
Power-Down Operation ............................................................ 24
Load DAC (Hardware LDAC Pin) ........................................... 25
LDAC Mask Register ................................................................. 25
Hardware Reset (RESET) .......................................................... 26
Reset Select Pin (RSTSEL) ........................................................ 26
Software Reset ............................................................................. 26
Amplifier Gain Selection on LFCSP Package ......................... 26
Applications Information .............................................................. 27
Power Supply Recommendations ............................................. 27
Microprocessor Interfacing ....................................................... 27
AD5676 to ADSP-BF531 Interface .......................................... 27
AD5676 to SPORT Interface ..................................................... 27
Layout Guidelines....................................................................... 27
Galvanically Isolated Interface ................................................. 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
5/2018—Rev. C to Rev. D
Change to SYNC to SCLK Falling Edge Parameter, Table 5 ....... 8
4/2018—Rev. B to Rev. C
Changes to Features Section and General Description Section ....... 1
Changes to Specifications Section .................................................. 4
Changes to VLOGIC Parameter, Table 2 ............................................ 5
Deleted Endnote 3, Table 2; Renumbered Sequentially .............. 5
Changes to AC Characteristics Section and Output Noise
Spectral Density (NSD) Parameter, Table 3 .................................. 6
Changes to Timing Characteristics Section, Table 4, and
Figure 2 .............................................................................................. 7
Changes to Daisy-Chain and Readback Timing Characteristics
Section, Table 5, Figure 3, and Figure 4 ......................................... 8
Added Figure 5; Renumbered Sequentially .................................. 9
Deleted ESD Ratings Parameter, Table 6 ..................................... 10
Changes to Thermal Resistance Section ...................................... 10
Change to VLOGIC Pin Description, Table 8 .................................. 11
Change to VLOGIC Pin Description, Table 9 .................................. 12
Changes to Figure 21 ...................................................................... 15
Changes to Table 10 ........................................................................ 22
Deleted Endnote 1, Table 11.......................................................... 22
Changes to Update DAC Register with Contents of Input Register n
Section and Write to and Update DAC Channel n (Independent
of LDAC) Section ........................................................................... 23
Changes to Readback Operation Section and Power-Down
Operation Section........................................................................... 24
Changes to Hardware Reset (RESET) Section ............................ 26
Added Software Reset Section ...................................................... 26
Updated Outline Dimensions ....................................................... 29
10/2015—Rev. A to Rev. B
Added 20-Lead LFCSP ...................................................... Universal
Changes to Features Section, General Description Section,
Table 1, Product Highlights Section, and Figure 1 ....................... 1
Changes to Table 2 ............................................................................. 3
Deleted Figure 5; Renumbered Sequentially ................................. 8
Change to Table 5 .............................................................................. 8
Added Table 6; Renumbered Sequentially ..................................... 8
Change to Table 7 .............................................................................. 9
Added Figure 6 and Table 8 .......................................................... 10
Change to Figure 10 to Figure 12 ................................................. 11
Change to Figure 13 to Figure 18 ................................................. 12
Changes to Figure 19, Figure 20, and Figure 22 ......................... 13
m" 152 uf LDAC m Readba m LDAC
Data Sheet AD5676
Rev. D | Page 3 of 30
Change to Figure 25, Figure 28, and Figure 30 ........................... 14
Change to Figure 31, Figure 34, Figure 35, and Figure 36 ......... 15
Change to Figure 37 and Figure 38 ............................................... 16
Changes to Transfer Function Section and Output Amplifiers
Section .............................................................................................. 19
Change to Table 9 ............................................................................ 20
Changes to Write to and Update DAC Channel n (Independent
of LDAC) Section ............................................................................ 21
Changes to Readback Operation Section ..................................... 22
Changes to LDAC Mask Register Section and Table 14 ............. 23
Changes to Reset Select Pin (RSTSEL) Section ........................... 24
Added Amplifier Gain Selection on LFCSP Section, Table 16,
and Table 17 ..................................................................................... 24
Added Figure 53, Outline Dimensions ......................................... 27
Changes to Ordering Guide ........................................................... 27
2/2015—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 3
Change to RESET Pulse Activation Time Parameter, Table 4 ..... 6
Change to Terminology Section .................................................... 17
Changes to Transfer Function Section and Output Amplifiers
Section .............................................................................................. 19
Changes to Hardware Reset (RESET) Section ............................ 24
Changes to Ordering Guide ........................................................... 27
10/2014—Revision 0: Initial Version
AD5676 Data Sheet
Rev. D | Page 4 of 30
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, resistive load (RL) = 2 kΩ, capacitive load (CL) = 200 pF, all specifications −40°C to +125°C,
unless otherwise noted.
Table 2.
A Grade B Grade
Test Conditions/Comments
Parameter Min Typ Max Min Typ Max Unit
STATIC PERFORMANCE1
Resolution 16 16 Bits
Relative Accuracy (INL)2 ±1.8 ±8 ±1.8 ±3 LSB Gain = 1
±1.7 ±8 ±1.7 ±3 LSB Gain = 2
Differential Nonlinearity
(DNL)2
±0.7 ±1 ±0.7 ±1 LSB Gain = 1
±0.5 ±1 ±0.5 ±1 LSB Gain = 2
Zero Code Error2 0.8 4 0.8 1.6 mV Gain = 1 or gain = 2
Offset Error2 −0.75 ±6 −0.75 ±2 mV Gain = 1
−0.1 ±4 −0.1 ±1.5 mV Gain = 2
Full-Scale Error2 −0.018 ±0.28 −0.018 ±0.14 % of full-
scale range
(FSR)
Gain = 1
−0.013 ±0.14 −0.013 ±0.07 % of FSR Gain = 2
Gain Error2 +0.04 ±0.24 +0.04 ±0.12 % of FSR Gain = 1
−0.02 ±0.12 −0.02 ±0.06 % of FSR Gain = 2
Total Unadjusted Error (TUE) +0.03 ±0.3 +0.03 ±0.18 % of FSR Gain = 1
+0.006 ±0.25 +0.006 ±0.14 % of FSR Gain = 2
Offset Error Drift2 ±1 ±1 µV/°C
DC Power Supply Rejection
Ratio (PSRR)2
0.25 0.25 mV/V DAC code = midscale, VDD = 5 V
± 10%
DC Crosstalk2 ±2 ±2 µV Due to single channel, full-
scale output change
±3 ±3 µV/mA Due to load current change
±2 ±2 µV Due to powering down (per
channel)
OUTPUT CHARACTERISTICS
Output Voltage Range 0 VREF 0 VREF V Gain = 1
0 2 × VREF 0 2 × VREF V Gain = 2
Output Current Drive (IOUT) 15 15 mA
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 1 kΩ
Resistive Load3 1 1 kΩ
Load Regulation 183 183 µV/mA 5 V ± 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
177 177 µV/mA 3 V ± 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current4 40 40 mA
Load Impedance at Rails5 25 25 Ω
Power-Up Time 2.5 2.5 µs Exiting power-down mode,
VDD = 5 V
REFERENCE INPUT
Reference Input Current 398 398 µA VREF = VDD = VLOGIC = 5.5 V, gain = 1
789 789 µA VREF = VDD = VLOGIC = 5.5 V, gain = 2
Reference Input Range 1 VDD 1 VDD V Gain = 1
1 VDD/2 1 VDD/2 V Gain = 2
Reference Input Impedance 14 14 kΩ Gain = 1
7 7 kΩ Gain = 2
Data Sheet AD5676
Rev. D | Page 5 of 30
A Grade B Grade
Test Conditions/Comments
Parameter Min Typ Max Min Typ Max Unit
LOGIC INPUTS
Input Current ±1 ±1 µA Per pin
Input Voltage
Low, VIL 0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VIH 0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
3
3
pF
LOGIC OUTPUTS (SDO)
Output Voltage
Low, VOL 0.4 0.4 V ISINK = 200 μA
High, VOH VLOGIC −
0.4
VLOGIC −
0.4
V ISOURCE = 200 μA
Floating State Output
Capacitance
4 4 pF
POWER REQUIREMENTS
VLOGIC 1.62 5.5 1.62 5.5 V
VLOGIC Supply Current (ILOGIC) 3 3 µA Power-on, −40°C to +105°C
3 3 µA Power-on, −40°C to +125°C
3
µA
Power-down, −40°C to +105°C
3 3 µA Power-down, −40°C to +125°C
VDD 2.7 5.5 2.7 5.5 V Gain = 1
VREF +
1.5
5.5 VREF +
1.5
5.5 V Gain = 2
VDD Supply Current (IDD)
Normal Mode6 1.1 1.26 1.1 1.26 mA −40°C to +85°C
1.1 1.3 1.1 1.3 mA −40°C to +105°C
All Power-Down Modes7 1 1.7 1 1.7 µA Three-state, −40°C to +85°C
1 1.7 1 1.7 µA Power-down to 1 kΩ, −40°C to
+85°C
1
1
2.5
µA
Three-state, −40°C to +105°C
1 2.5 1 2.5 µA Power-down to 1 kΩ, −40°C to
+105°C
1 5.5 1 5.5 µA Three-state, −40°C to +125°C
1 5.5 1 5.5 µA Power-down to 1 kΩ, −40°C to
+125°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 See the Terminology section.
3 Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink
40 mA up to a junction temperature of 125°C.
4 VDD = 5 V. The AD5676 includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature can impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6 Interface inactive. All DACs active. DAC outputs unloaded.
7 All DACs powered down.
Table 3‘
AD5676 Data Sheet
Rev. D | Page 6 of 30
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless
otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
Output Voltage Settling Time1 5 8 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 0.8 V/µs
Digital-to-Analog Glitch Impulse1 1.4 nV-sec 1 LSB change around major carry, gain = 1
Digital Feedthrough1 0.13 nV-sec
Digital Crosstalk1 0.1 nV-sec
Analog Crosstalk1 −0.25 nV-sec Gain = 1
−1.3 nV-sec Gain = 2
DAC-to-DAC Crosstalk1 −2.0 nV-sec
Total Harmonic Distortion (THD)1, 2 −80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Output Noise Spectral Density (NSD)1 80 nV/√Hz DAC code = midscale, bandwidth = 10 kHz, gain = 2
Output Noise
6
µV p-p
0.1 Hz to 10 Hz, gain = 1
Signal-to-Noise Ratio (SNR) 90 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Spurious-Free Dynamic Range (SFDR) 83 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Signal-to-Noise-and-Distortion Ratio (SINAD) 80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 See the Terminology section.
2 Digitally generated sine wave (fOUT) at 1 kHz.
Table 4‘ W 0% W WRising Edge tom W m W 0W W 0% m 0% W an, SYNC
Data Sheet AD5676
Rev. D | Page 7 of 30
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter Symbol Min Max Min Max Unit
SCLK Cycle Time t1 20 20 ns
SCLK High Time t2 8 8 ns
SCLK Low Time t3 10 12 ns
SYNC to SCLK Falling Edge Setup Time t4 15 11 ns
Data Setup Time t5 2 3 ns
Data Hold Time t6 2 2 ns
SCLK Falling Edge to SYNC Rising Edge t7 4 4 ns
Minimum SYNC High Time t8 15 12 ns
SYNC
Rising Edge to
SYNC
Rising Edge (DAC Register Updates)
t
9
870
830
ns
SYNC Falling Edge to SCLK Fall Ignore t10 4 4 ns
LDAC Pulse Width Low t11 8 8 ns
SYNC Rising Edge to LDAC Rising Edge t12 25 25 ns
SYNC Rising Edge to LDAC Falling Edge t13 25 25 ns
LDAC Falling Edge to SYNC Rising Edge t14 840 800 ns
Minimum Pulse Width Low t15 8 10 ns
RESETActivation Time t16 90 90 ns
Power-Up Time1 5.5 5.5 µs
1 Time to exit power-down to normal mode of AD5676 operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded.
t
4
t
3
SCLK
SYNC
SDIN
t
1
t
2
t
5
t
6
t
7
t
14
t
9
t
8
DB23
t
10
t
11
t
12
LDAC
1
LDAC
2
t
13
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
RESET
t
15
t
16
V
OUT
DB0
10485-002
Figure 2. Serial Write Operation
Table 5‘ SVNC SVNC SVNC o SVNC SYNC -IH MWWW_ ‘>ijtxxxx‘>— ’ ¥>CXTX X X M
AD5676 Data Sheet
Rev. D | Page 8 of 30
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD = 2.7 V to
5.5 V.
Table 5.
1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter Symbol Min Max Min Max Unit
SCLK Cycle Time t1 130 110 ns
SCLK High Time t2 33 23 ns
SCLK Low Time t3 12 7 ns
ASYNCEE
A to SCLK Falling Edge t4 80 80 ns
Data Setup Time t5 2 2 ns
Data Hold Time t6 2 2 ns
SCLK Falling Edge to ASYNCEE
A Rising Edge t7 35 10 ns
Minimum ASYNCEE
A High Time t8 55 30 ns
SDO Data Valid from SCLK Rising Edge t9 60 50 ns
ASYNCEE
A Rising Edge to SCLK Falling Edge t10 2 6 ns
ASYNCEE
A Rising Edge to SDO Disable t11 40 35 ns
Circuit and Timing Diagrams
10485-003
200µA I
OL
200µA I
OH
V
OH
(MIN)
TO OUTPUT
PIN C
L
20pF
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t
4
t
1
t
2
t
3
t
5
t
6
t
8
4824
DB23 DB0 DB23 DB0
INPUT WORD FOR DAC NUNDEFINED
INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N
t
7
t
10
t
9
10485-004
Figure 4. Daisy Chain Timing Diagram
i H a” 3; XXX X X: —> m 24 XZiX X 3359?
Data Sheet AD5676
Rev. D | Page 9 of 30
10485-005
SYNC
t
8
t
6
SCLK 24
124
1
t
8
t
4
t
2
t
10
t
7
t
3
t
1
DB23 DB0 DB23 DB0
SDIN
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
t
5
DB23 DB0
SDO
SELECTED REGISTER DATA
CLOCKED OUT
HI-Z
t
9
t
11
Figure 5. Readback Timing Diagram
Table 7‘ Thermal Resistance ESD CAUTION A M ESD (almmsmic discharge] sensilive devize. Chavged dame; and (Mun boards can dwszharge mm: daemon Akhuugh ms pvudun feamve: paxenxed av pvopnexavy pmemon mumy, damage may occuv on dewces summed m hlgh enevgy ESD Therelave, pvopev ESD pmauum mama be xaken m avmd pevfovmance degvadanon or loss of funztlonahty
AD5676 Data Sheet
Rev. D | Page 10 of 30
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
VLOGIC to GND −0.3 V to +7 V
VOUTx to GND −0.3 V to VDD + 0.3 V
VREF to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature 125°C
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 7. Thermal Resistance
Package Type
θ
JA
θ
JB
θ
JC
Ψ
JT
Ψ
JB
Unit
20-Lead TSSOP
(RU-20)1
98.65 44.39 17.58 1.77 43.9 °C/W
20-Lead LFCSP
(CP-20-8)2
82 16.67 32.5 0.43 22 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
ESD CAUTION
SYNC SYNC LDAC LDAC RESET RESET RESET LDAC RESET
Data Sheet AD5676
Rev. D | Page 11 of 30
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
OUT
0
V
DD
V
LOGIC
SDI
SCLK
SYNC
V
OUT
1
V
OUT
3
V
REF
RESET
RSTSEL
LDAC
SDO
V
OUT
6
V
OUT
7
GAIN
V
OUT
5
V
OUT
4
GND
V
OUT
2
TOP VIEW
(Not to Scale)
AD5676
12549-006
Figure 6. 20-Lead TSSOP Pin Configuration
Table 8. 20-Lead TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT1 Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
2 VOUT0 Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
3
V
DD
Power Supply Input. The AD5676 operates from 2.7 V to 5.5 V. Decouple V
DD
with a 10 µF capacitor in parallel with
a 0.1 µF capacitor to GND.
4 VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
5 ASYNCE
A Active Low Control Input. This is the frame synchronization signal for the input data. When ASYNCE
A goes low, data
transfers in on the falling edges of the next 24 clocks.
6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
7 SDI Serial Data Input. The AD5676 has a 24-bit input shift register. Data is clocked into the register on the falling edge
of the serial clock input.
8 GAIN Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC,
all eight DACs output a span of 0 V to 2 × VREF.
9 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
10 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
11 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
12 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
13 GND Ground Reference Point for All Circuitry on the Device.
14 RSTSEL Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all
eight DACs to midscale.
15 ALDACE Load DAC. ALDACE
A operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data. This allows all DAC outputs to update simultaneously.
This pin can also be tied permanently low.
16 SDO Serial Data Output. Use this pin to daisy-chain a number of devices together, or use it for readback. The serial data
transfers on the rising edge of SCLK and is valid on the falling edge.
17 ARESETE Asynchronous Reset Input. The ARESETE
A input is falling edge sensitive. When ARESETE
A is low, all ALDACE
A pulses are
ignored. When ARESETE
A is activated, the input register and the DAC register are updated with zero scale or midscale,
depending on the state of the RSTSEL pin.
18 VREF Reference Input Voltage.
19 VOUT3 Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
20 VOUT2 Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
SYNC SYNC LDAC LDAC RESET nput.The RESET input is falling edge sensiwe When RESET ‘5 low, 3“ LDAC When RESET
AD5676 Data Sheet
Rev. D | Page 12 of 30
12549-100
14
13
12
1
3
4
RESET
15 V
REF
SDO
LDAC
11 GND
V
DD
SYNC
2
V
LOGIC
SCLK
5
SDI
7
V
OUT
6
6V
OUT
7
8V
OUT
5
9V
OUT
4
10NIC
19 V
OUT
1
20 V
OUT
0
18 V
OUT
2
17 V
OUT
3
16 NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE TIED TO GND.
AD5676
TOP VIEW
(Not to Scale)
Figure 7. 20-Lead LFCSP Pin Configuration
Table 9. 20-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1 VDD Power Supply Input. The AD5676 operate from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a
0.1 µF capacitor to GND.
2 VLOGIC Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V.
3 ASYNCE
A Active Low Control Input. This is the frame synchronization signal for the input data. When ASYNCE
A goes low, data
transfers in on the falling edges of the next 24 clocks.
4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
5 SDI Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
6 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
7 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
8 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
9 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
10, 16 NIC Not Internally Connected.
11 GND Ground Reference Point for All Circuitry on the Device.
12 ALDACE Load DAC. ALDACE
A operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data. That allows all DAC outputs to update simultaneously.
This pin can also be tied permanently low.
13 SDO Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
14 ARESETE Asynchronous Reset Input. The ARESETE
A input is falling edge sensitive. When ARESETE
A is low, all ALDACE
A pulses are ignored.
When ARESETE
A is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
15
V
REF
Reference Input Voltage.
17 VOUT3 Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
18 VOUT2 Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
19 VOUT1 Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
20 VOUT0 Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
EPAD Exposed Pad. The exposed pad must be tied to GND.
Data Sheet AD5676
Rev. D | Page 13 of 30
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
010000 20000 30000 40000 50000 60000 70000
12549-007
INL ERROR (LSB)
CODE
Figure 8. INL Error vs. Code
12549-008
DNL ERROR (LSB)
CODE
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
010000 20000 30000 40000 50000 60000 70000
Figure 9. DNL Error vs. Code
12549-009
TOTAL UNADJUSTED ERROR (% OF FSR)
CODE
–0.02
–0.01
0
0.01
0.02
0.03
0.04
010000 20000 30000 40000 50000 60000 70000
Figure 10. TUE vs. Code
12549-010
INL ERROR (LSB)
TEMPERATURE (°C)
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
–40 –20 020 40 60 80 100 120
Figure 11. INL Error vs. Temperature
12549-011
DNL ERROR (LSB)
–10
–8
–6
–4
–2
0
2
4
6
8
10
TEMPERATURE (°C)
–40 –20 020 40 60 80 100 120
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 12. DNL Error vs. Temperature
12549-012
TOTAL UNADJUSTED ERROR (% OF FSR)
TEMPERATURE (°C)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
–40 –20 020 40 60 80 100 120
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 13. TUE vs. Temperature
AD5676 Data Sheet
Rev. D | Page 14 of 30
12549-016
INL ERROR (LSB)
SUPPLY VOLTAGE (V)
–10
–8
–6
–4
–2
0
2
4
6
8
10
2.7 3.2 3.7 4.2 4.7 5.2
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 14. INL Error vs. Supply Voltage
12549-017
DNL ERROR (LSB)
SUPPLY VOLTAGE (V)
–10
–8
–6
–4
–2
0
2
4
6
8
10
2.7 3.2 3.7 4.2 4.7 5.2
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 15. DNL Error vs. Supply Voltage
12549-018
TOTAL UNADJUSTED ERROR (% OF FSR)
SUPPLY VOLTAGE (V)
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
2.7 3.2 3.7 4.2 4.7 5.2
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 16. TUE vs. Supply Voltage
12549-019
ERROR (% OF FSR)
TEMPERATURE (°C)
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
–40 –20 020 40 60 80 100 120
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
FULL-SCALE ERROR
GAIN ERROR
Figure 17. Gain Error and Full-Scale Error vs. Temperature
12549-020
ERROR (% OF FSR)
SUPPLY VOLTAGE (V)
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
2.7 3.2 3.7 4.2 4.7 5.2
FULL-SCALE ERROR
GAIN ERROR
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage
12549-021
ERROR (mV)
TEMPERATURE (°C)
–0.6
–0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
–40 –20 020 40 60 80 100 120
ZERO CODE ERROR
OFFSET ERROR
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 19. Zero Code Error and Offset Error vs. Temperature
fi zzno con: ERROR /_\ mam / \\ \\ \\
Data Sheet AD5676
Rev. D | Page 15 of 30
12549-022
ERROR (mV)
SUPPLY VOLTAGE (V)
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.7 3.2 3.7 4.2 4.7 5.2
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
ZERO CODE ERROR
OFFSET ERROR
Figure 20. Zero Code Error and Offset Error vs. Supply Voltage
12549-023
HITS
I
DD
FULL SCALE (mA)
0
20
40
60
80
100
120
0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 21. IDD Histogram with External Reference
12549-024
V
OUT
(V)
LOAD CURRENT (A)
–1.4
–1.0
–0.6
–0.2
0.2
0.6
1.0
1.4
00.005 0.010 0.015 0.020 0.025 0.030
SINKING –2.7V
SINKING –3V
SINKING –5V
SOURCING –5V
SOURCING –3V
SOURCING –2.7V
Figure 22. Headroom/Footroom (∆VOUT) vs. Load Current
12549-025
V
OUT
(V)
LOAD CURRENT (A)
–2
–1
0
1
2
3
4
5
6
–0.06 –0.04 –0.02 00.02 0.04 0.06
VDD = 5V
TA = 25°C
GAIN = 2
V
REF
= 2.5V
0xFFFF
0xC000
0x8000
0x4000
0x0000
Figure 23. Source and Sink Capability at 5 V
12549-026
V
OUT
(V)
LOAD CURRENT (A)
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–
0.06
–
0.04
–
0.02 00.02 0.04 0.06
VDD = 3V
TA = 25°C
GAIN = 1
V
REF
= 2.5V
0xFFFF
0xC000
0x8000
0x4000
0x0000
Figure 24. Source and Sink Capability at 3 V
12549-027
I
DD
(mA)
CODE
1.0
1.1
1.2
1.3
1.4
1.5
1.6
010000 20000 30000 40000 50000 60000 70000
DEVICE 1
DEVICE 2
DEVICE 3
Figure 25. IDD vs. Code
AD5676 Data Sheet
Rev. D | Page 16 of 30
12549-028
I
DD
(mA)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TEMPERATURE (°C)
–40 –20 020 40 60 80 100 120
FULL SCALE
ZERO CODE
EXTERNAL REFERENCE, FULL SCALE
Figure 26. IDD vs. Temperature
12549-029
I
DD
(mA)
LOGIC INPUT VOLTAGE (V)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.7 3.2 3.7 4.2 4.7 5.2
ZERO CODE
EXTERNAL REFERENCE, FULL SCALE
FULL SCALE
Figure 27. IDD vs. Supply Voltage
12549-030
I
DD
(mA)
LOGIC INPUT VOLTAGE (V)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.7 3.2 3.7 4.2 4.7 5.2
ZERO CODE
EXTERNAL REFERENCE, FULL SCALE
FULL SCALE
Figure 28. IDD vs. Logic Input Voltage
12549-031
V
OUT
(V)
TIME (µs)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
80 100 120 140 160 180 200
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
V
DD
= 5V
GAIN = 1
T
A
= 25°C
V
REF
= 2.5V
1/4 TO 3/4 SCALE
Figure 29. Full-Scale Settling Time
12549-032
V
DD
(V)
TIME (Seconds)
–0.001
0
0.001
0.002
0.003
0.004
0.005
0.006
–1
0
1
2
3
4
5
6
00.002 0.004 0.006 0.008 0.010
V
OUT
(V)
V
DD
(V)
V
OUT
0 (V)
V
OUT
1 (V)
V
OUT
2 (V)
V
OUT
3 (V)
V
OUT
4 (V)
V
OUT
5 (V)
V
OUT
6 (V)
V
OUT
7 (V)
Figure 30. Power-On Reset to 0 V and Midscale
12549-033
V
OUT
(V)
TIME (µs)
0
0.50
1.00
1.50
2.00
2.50
3.00
–5 0510
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
SYNC
MIDSCALE, GAIN = 2
MIDSCALE, GAIN = 1
Figure 31. Exiting Power-Down to Midscale
Msn (NV/m2)
Data Sheet AD5676
Rev. D | Page 17 of 30
12549-034
V
OUT
(V)
TIME (µs)
0.004
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.00415 16 17 18 19 20 21 22
V
DD
= 5V
GAIN = 1
T
A
= 25°C
V
REF
= 2.5V
CODE = 0x7FFF TO 0x8000
ENERGY = 1.209376nV-sec
Figure 32. Digital-to-Analog Glitch Impulse
12549-035
V
OUT
(V)
TIME (µs)
–0.006
–0.005
–0.004
–0.003
–0.002
–0.001
0.001
0
0.002
0.003
0 2 46810 12 14 161820
ATTACK CHANNEL 1
ATTACK CHANNEL2
ATTACK CHANNEL 3
ATTACK CHANNEL 4
ATTACK CHANNEL 5
ATTACK CHANNEL 6
ATTACK CHANNEL7
Figure 33. Analog Crosstalk
12549-036
V
OUT
(V)
TIME (µs)
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
0.010
0.012
0246810 12 14 16 18 20
ATTACK CHANNEL 1
ATTACK CHANNEL 2
ATTACK CHANNEL 3
ATTACK CHANNEL 4
ATTACK CHANNEL 5
ATTACK CHANNEL 6
ATTACK CHANNEL 7
Figure 34. DAC-to-DAC Crosstalk
1
12549-038
CH1 5µV M1.0sec A CH1 401mV
Figure 35. 0.1 Hz to 10 Hz Output Noise
12549-040
NSD (NV/√Hz)
FREQUENCY (Hz)
0
200
400
600
800
1000
1200
10 100 1k 10k 100k 1M
FULL SCALE
MIDSCALE
ZERO SCALE
V
DD
= 5V
T
A
= 25°C
GAIN = 1
V
REF
= 2.5V
Figure 36. Noise Spectral Density (NSD)
12549-037
dBV
FREQUENCY (kHz)
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0246810 12 14 16 18 20
V
DD
= 5V
T
A
= 25°C
V
REF
= 2.5V
Figure 37. THD at 1 kHz
AD5676 Data Sheet
Rev. D | Page 18 of 30
12549-039
TIME (ms)
V
OUT
(V)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20
0nF
0.1nF
1nF
4.7nF
10nF
V
DD
= 5V
GAIN = 1
T
A
= 25°C
V
REF
= 2.5V
Figure 38. Settling Time for Various Capacitive Loads
12549-041
V
OUT
(V)
TIME (µs)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
80 100 120 140 160 180 200
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
V
DD
= 5.5V
GAIN = 1
T
A
= 25°C
V
REF
= 2.5V
1/4 TO 3/4 SCALE
Figure 39. Settling Time, 5.5 V
12549-042
VOUT AT MIDSCALE (V)
VOUT AT ZERO SCALE (V)
TIME (µs)
0
0.1
0.2
0.3
0
1
2
3
–20 020 40 60
RESET
MIDSCALE, GAIN = 1
ZERO SCALE, GAIN = 1
Figure 40. Hardware Reset
12549-043
BANDWIDTH (dB)
FREQUENCY (Hz)
–30
–20
–10
0
1K 10K100K1M 10M
V
DD
= 5V
T
A
= 25°C
EXTERNAL REFERENCE = 2.5V, ±0.1V
p-p
GAIN = 1
V
OUT
= FULL SCALE
Figure 41. Multiplying Bandwidth, External Reference
c (hung a software LDAC umput of: mu u: adds to a :pecified level for a v: m 3/4 mum ']\'
Data Sheet AD5676
Rev. D | Page 19 of 30
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity. The AD5676
is guaranteed monotonic by design.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
is 0 V. The zero code error is always positive because the output
of the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
the change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a ¼ to ¾ full-scale
input change and is measured from the rising edge of ASYNCE
A.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-sec.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. To
measure analog crosstalk, load one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa). Then, execute
a software ALDACE
A and monitor the output of the DAC whose digital
code was not changed. The area of the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update
commands while monitoring the output of the victim channel
that is at midscale. The energy of the glitch is expressed in nV-sec.
AD5676 Data Sheet
Rev. D | Page 20 of 30
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference with full-scale code loaded to the DAC appears on the
output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. THD is measured in
decibels.
Data Sheet AD5676
Rev. D | Page 21 of 30
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5676 is an octal 16-bit, serial input, voltage output DAC.
The device operates from supply voltages of 2.7 V to 5.5 V. Data
is written to the AD5676 in a 24-bit word format via a 3-wire
serial interface. The AD5676 incorporates a power-on reset
circuit to ensure that the DAC output powers up to a known
output state. The device also has a software power-down mode that
reduces the typical current consumption to typically 1 µA.
TRANSFER FUNCTION
The gain of the output amplifier can be set to ×1 or ×2 using the
gain select pin (GAIN) on the TSSOP package or the gain bit on
the LFCSP package. When the GAIN pin is tied to GND, all eight
DAC outputs have a span from 0 V to VREF. When the GAIN pin
is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
When using the LFCSP package, the gain bit in the gain setup
register is used to set the gain of the output amplifier. The gain
bit is 0 by default. When the gain bit is 0 the output span of all
eight DACs is 0 V to VREF. When the gain bit is 1 the output
span of all eight DACs is 0 V to 2 × VREF. The gain bit is ignored
on the TSSOP package.
DAC ARCHITECTURE
The DAC architecture implements a segmented string DAC
with an internal output buffer. Figure 42 shows the internal
block diagram.
INPUT
REGISTER DAC
REGISTER RESISTOR
STRING
REF (+)
V
REF
GND
REF (–)
V
OUT
x
GAIN
(GAIN = 1 OR 2)
12549-044
Figure 42. Single DAC Channel Architecture Block Diagram
Figure 43 shows the simplified segmented resistor string DAC
structure. The code loaded to the DAC register determines the
switch on the string that is connected to the output buffer.
Because each resistance in the string has the same value, R, the
string DAC is guaranteed monotonic.
R
R
R
R
RTO OUTPUT
AMPLIFIER
V
REF
12549-045
Figure 43. Simplified Resistor String Structure
Output Amplifiers
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the gain setting, the offset error,
and the gain error.
The output amplifiers can drive a load of 1 kΩ in parallel with
10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾
scale settling time of 5 µs.
addre
AD5676 Data Sheet
Rev. D | Page 22 of 30
SERIAL INTERFACE
The AD5676 has a 3-wire serial interface (SYNC, SCLK, and
SDI) that is compatible with SPI, QSPI™, and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence. The AD5676 contains
an SDO pin that allows the user to daisy-chain multiple devices
together (see the Daisy-Chain Operation section) or for readback.
Input Shift Register
The input shift register of the AD5676 is 24 bits wide. Data
is loaded MSB first (DB23), and the first four bits are the
command bits, C3 to C0 (see Table 10), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 11), and finally, the
16-bit data-word.
The data-word comprises 16-bit input code, followed by zero, two,
or four don’t care bits. These data bits are transferred to the input
register on the 24 falling edges of SCLK and are updated on the
rising edge of SYNC.
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
Table 10. Command Bit Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 No operation
0 0 0 1 Write to Input Register n (where n = 1 to 8,
depending on the DAC selected from the
address bits in Table 11), dependent on
LDAC
0 0 1 0 Update the DAC register with contents of
Input Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up the DAC
0 1 0 1 Hardware LDAC mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Gain setup register (LFCSP package only)
1 0 0 0 Set up the DCEN register (daisy-chain
enable)
1 0 0 1 Set up the readback register (readback
enable)
1 0 1 0 Update all channels of the input register
simultaneously with the input data
1 0 1 1 Update all channels of the DAC register
and input register simultaneously with
the input data
1 1 0 0 Reserved
… … … …
1 1 1 1 No operation, daisy-chain mode
Table 11. Address Bits and Selected DACs
Address Bits Selected Output DAC
Channel
A3 A2 A1 A0
0 0 0 0 DAC 0
0 0 0 1 DAC 1
0 0 1 0 DAC 2
0 0 1 1 DAC 3
0 1 0 0 DAC 4
0 1 0 1 DAC 5
0 1 1 0 DAC 6
0 1 1 1 DAC 7
ADDRESS BITSCOMMAND BITS
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
12549-046
Figure 44. Input Shift Register Content
Table 12. Daiserhain Enable (DCEN) Register SYNC gt of SC SYNC lug LDAC a valid I i SYNC SYNC betwse SYNC SYNC i addm i LDAC soc LDAC lo the dc n LDAC * i _. LDAC i 4» SCLK pi SY]\ C Write to and Update DAC Channel I! (Independent olLDAC qua] 24 SYNC ‘hs DAC SYN C hm reg] SYNC rsl cluc and hike SYNC
Data Sheet AD5676
Rev. D | Page 23 of 30
STANDALONE OPERATION
The write sequence begins by bringing the SYNC line low. Data
from the SDI line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of the 24 data bits is
clocked in, bring SYNC high. The programmed function is then
executed, that is, an LDAC dependent change in the DAC
register contents and/or a change in the mode of operation
occurs.
If SYNC is taken high at a clock before the 24th clock, it is
considered a valid frame, and invalid data may be loaded to the
DAC. Bring SYNC high for a minimum of 9.65 ns (single
channel, see t8 in Table 4) before the next write sequence so that
a falling edge of SYNC can initiate the next write sequence.
Idle SYNC at the rails between write sequences for even lower
power operation. The SYNC line is kept low for 24 falling edges
of SCLK, and the DAC is updated on the rising edge of SYNC.
When data is transferred into the input register of the addressed
DAC, all DAC registers and outputs update by taking LDAC low
while the SYNC line is high.
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write to the dedicated input
register for each DAC individually. When LDAC is low, the
input register is transparent (if not controlled by the LDAC
mask register).
Update DAC Register with Contents of Input Register n
Command 0010 loads the DAC registers and outputs with the
contents of the selected input registers and updates the DAC
outputs directly. Data Bit D7 to Bit D0 determine which DACs
have data from the input register transferred to the DAC
register. Setting a bit to 1 transfers data from the input register
to the appropriate DAC register.
Write to and Update DAC Channel n (Independent of LDAC)
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. The address bits are used
to select the DAC channel.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can daisy-
chain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command 1000
is reserved for this DCEN function (see Table 10). The daisy-chain
mode is enabled by setting Bit DB0 in the DCEN register. The
default setting is standalone mode, where DB0 = 0. Table 12
shows how the state of the bit corresponds to the mode of
operation of the device.
Table 12. Daisy-Chain Enable (DCEN) Register
DB0 Description
0 Standalone mode (default)
1 DCEN mode
68HC11*
MISO
SDI
SCLK
MOSI
SCK
PC7
PC6 SDO
SCLK
SDO
SCLK
SDO
SDI
SDI
SYNC
SYNC
SYNC
LDAC
LDAC
LDAC
AD5676
AD5676
AD5676
*ADDITIONAL PINS OMITTED FOR CLARITY.
12549-047
Figure 45. Daisy-Chaining the AD5676
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDI input on the next DAC in the chain, a daisy-chain interface is
constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices updated. If SYNC is
taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC.
When the serial transfer to all devices is complete, SYNC goes
high, which latches the input data in each device in the daisy
chain and prevents any further data from being clocked into the
input shift register. The serial clock can be continuous or a gated
clock. If SYNC is held low for the correct number of clock
cycles, a continuous SCLK source is used. In gated clock mode,
use a burst clock containing the exact number of clock cycles,
and take SYNC high after the final clock to latch the data.
Table 13. Modes of Operation Table 14. 2478“ Inpm Shift Regism Cements of PowerDown/PowerrUp Operation
AD5676 Data Sheet
Rev. D | Page 24 of 30
READBACK OPERATION
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is enabled
automatically for the duration of the read operation, after which
it is disabled again. Command 1001 is reserved for the readback
function. This command, in association with the address bits,
A3 to A0, selects the DAC input register to read. Note that,
during readback, only one DAC register can be selected. The
remaining data bits in the write sequence are don’t care bits.
During the next SPI write, the data appearing on the SDO output
contains the data from the previously addressed register.
For example, to read back the DAC register for Channel 0,
implement the following sequence:
1. Write 0x900000 to the AD5676 input register. This
configures the device for read mode with the DAC register
of Channel 0 selected. Note that all data bits, DB15 to DB0,
are don’t care bits.
2. Follow this with a second write, a no operation (NOP)
condition, 0x000000 or 0xF00000 when in daisy-chain
mode. During this write, the data from the register is
clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
When SYNC is high the SDO pin is driven by a weak latch
which holds the last data bit. The SDO pin can be overdriven by
the SDO pin of another device, thus allowing multiple devices
to be read using the same SPI interface.
POWER-DOWN OPERATION
The AD5676 provides two separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 10). These power-down modes are software
programmable by setting 16 bits, Bit DB15 to Bit DB0, in the input
shift register. There are two bits associated with each DAC
channel. Table 13 shows how the state of the two bits corresponds
to the mode of operation of the device.
Table 13. Modes of Operation
Operating Mode PD1 PD0
Normal Operation 0 0
Power-Down Modes
1 kΩ to GND 0 1
Three-State 1 1
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 14 for the
contents of the input shift register during the power-down/
power-up operation.
When both Bit PD1 and Bit PD0 in the input shift register are set to
0, the device works normally with its normal power consumption
of 1.1 mA typically. However, for the two power-down modes,
the supply current falls to 1 µA typically. Not only does the
supply current fall, but the output stage is also internally switched
from the output of the amplifier to a resistor network of known
values. Therefore the DAC channel output impedance is defined
when the channel is powered down. There are two different
power-down options. The output is connected internally to
GND through either a 1 kΩ resistor, or it is left open-circuited
(three-state). The output stage is shown in Figure 46.
RESISTOR
NETWORK
V
OUT
x
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
12549-048
Figure 46. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The DAC register updates
while the device is in power-down mode. The time required to
exit power-down is typically 5 µs for VDD = 5 V.
Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1
[DB23:DB20] DB19 [DB18:DB16]
DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0
[DB15: B14] [DB13: B12] [DB11: B10] [DB9:DB8] [DB7:DB6] [DB5:DB4] [DB3:DB2] [DB1:DB0]
0100 0 XXX [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0]
1 X means don’t care.
fl? fl? sivuc —> channe‘s uEd npur Regme
Data Sheet AD5676
Rev. D | Page 25 of 30
LOAD DAC (HARDWARE LDAC PIN)
The AD5676 DAC has a double buffered interface consisting of
two banks of registers: input registers and DAC registers. The
user can write to any combination of the input registers.
Updates to the DAC register are controlled by the LDAC pin.
SYNC
SCLK
V
OUT
x
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIER
LDAC
SDO
SDI
V
REF
INPUT
REGISTER
16-BIT
DAC
12549-049
Figure 47. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (LDAC Held Low)
LDAC is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of SYNC and
the output begins to change (see Table 16).
Deferred DAC Updating (LDAC is Pulsed Low)
LDAC is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC is taken high. The
update occurs on the falling edge of LDAC.
LDAC MASK REGISTER
Command 0101 is reserved for this hardware LDAC function.
Address bits are ignored. Writing to the DAC using
Command 0101 loads the 8-bit LDAC register (DB7 to DB0).
The default for each channel is 0; that is, the LDAC pin works
normally. Setting the bits to 1 forces this DAC channel to ignore
transitions on the LDAC pin, regardless of the state of the hardware
LDAC pin. This flexibility is useful in applications where the
user wants to select which channels respond to the LDAC pin.
Table 15. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits
(DB7 to DB0) LDAC Pin LDAC Operation
00000000 1 or 0 Determined by the LDAC pin.
11111111 X1 DAC channels update and
override the LDAC pin. DAC
channels see LDAC as 1.
1 X means don’t care.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 15). Setting the LDAC
bits (DB0 to DB7) to 0 for a DAC channel means that the
update for this channel is controlled by the hardware LDAC pin.
Table 16. Write Commands and LDAC Pin Truth Table1
Command Description Hardware LDAC Pin State Input Register Contents DAC Register Contents
0001 Write to Input Register n
(dependent on LDAC)
VLOGIC Data update No change (no update)
GND2 Data update Data update
0010 Update the DAC register
with contents of Input
Register n
VLOGIC No change Updated with input register contents
GND No change Updated with input register contents
0011 Write to and update DAC
Channel n
VLOGIC Data update Data update
GND Data update Data update
1 A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
(blocked) by the LDAC mask register.
2 When LDAC is permanently tied low, the LDAC mask bits are ignored.
(RESET RESE 1‘ m scale 0 is user sslscmble via die RE 111: RESE 1‘ ). W hen 111: RE ams m m: programmed. While the Rb ' LDAC u RESE 1‘
AD5676 Data Sheet
Rev. D | Page 26 of 30
HARDWARE RESET (RESET)
The RESET pin is an active low reset that allows the outputs to
be cleared to either zero scale or midscale. The clear code value
is user selectable via the RESET select pin. It is necessary to keep
the RESET pin low for a minimum time (see Table 4) to complete
the operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. While the RESET pin is low, the outputs cannot be
updated with a new value. Any events on the LDAC or RESET
pins during power-on reset are ignored. If the RESET pin is
pulled low at power-up, the device does not initialize correctly
until the pin is released.
RESET SELECT PIN (RSTSEL)
The AD5676 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the RSTSEL pin
low, the output powers up to zero scale. Note that this is outside
the linear region of the DAC; by connecting the RSTSEL pin
high, VOUTx power up to midscale. The output remains powered
up at this level until a valid write sequence is made to the DAC.
The RSTSEL pin is only available on the TSSOP package. When
the AD5676 LFCSP package is used the outputs power up to 0 V.
SOFTWARE RESET
A software executable reset function is also available, which
resets the DAC to the power-on reset code. Command 0110 is
designated for this software reset function. The address bits
must be set to 0x0 and the data bits set to 0x1234 for the
software reset command to execute.
AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE
The output amplifier gain setting for the LFCSP package is
determined by the state of Bit DB2 in the gain setup register
(see Table 17 and Table 18).
Table 17. Gain Setup Register
Bit Description
DB2 Amplifier gain setting
DB2 = 0; amplifier gain = 1 (default)
DB2 = 1; amplifier gain = 2
Table 18. 24-Bit Input Shift Register Contents for Gain Setup Command
DB23 (MSB) DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 (LSB)
0 1 1 1 Don’t care Gain Reserved; set to 0 Reserved; set to 0
km HIM/l
Data Sheet AD5676
Rev. D | Page 27 of 30
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The AD5676 is typically powered by the following supplies: VDD =
3.3 V and VLOGIC = 1.8 V.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 48. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
12549-057
1.8V: V
LOGIC
3.3V: V
DD
5V INPUT
ADP160
LDO
ADP7118
LDO
Figure 48. Low Noise Power Solution for the AD5676
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5676 is via a serial bus
that uses a standard protocol that is compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire or 4-wire interface consisting of a clock signal,
a data signal, and a synchronization signal. The AD5676 requires a
24-bit data-word with data valid on the rising edge of SYNC.
AD5676 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5676 can easily connect to industry-
standard DSPs and microcontrollers. Figure 49 shows the
AD5676 connected to the Analog Devices, Inc. Blackfin® DSP.
The Blackfin has an integrated SPI port that can connect
directly to the SPI pins of the AD5676.
ADSP-BF531
SYNCSPISELx
SCLKSCK
SDIMOSI
LDACPF9
RESETPF8
AD5676
12549-053
Figure 49. ADSP-BF531 Interface
AD5676 TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 50 shows how a SPORT interface controls the AD5676.
ADSP-BF527
SYNCSPORT_TFS
SCLKSPORT_TSCK
SDISPORT_DTO
LDACGPIO0
RESETGPIO1
AD5676
12549-054
Figure 50. SPORT Interface
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the PCB on which the AD5676 is
mounted so that the AD5676 lies on the analog plane.
The AD5676 must have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. The 0.1 μF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
In systems where many devices are on one board, it is often useful
to provide some heat sinking capability to allow the power to
dissipate easily.
The GND plane on the device can be increased (as shown in
Figure 51) to provide a natural heat sinking effect.
AD5676
GND
PLANE
BOARD
12549-055
Figure 51. Pad Connection to Board
AD5676 Data Sheet
Rev. D | Page 28 of 30
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5676 makes the
device ideal for isolated interfaces because the number of interface
lines is kept to a minimum. Figure 52 shows a 4-channel
isolated interface to the AD5676 using an ADuM1400. For
further information, visit www.analog.com/icoupler.
ENCODE
SERIAL
CLOCK IN
CONTROLLER
ADuM1400
1
SERIAL
DATA OUT
SYNC OUT
LOAD DAC
OUT
DECODE TO
SCLK
TO
SDI
TO
SYNC
TO
LDAC
V
IA
V
OA
ENCODE DECODE
V
IB
V
OB
ENCODE DECODE
V
IC
V
OC
ENCODE DECODE
V
ID
V
OD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
12549-056
Figure 52. Isolated Interface
ORDERING GUIDE L4 * “EH- 1 1 W
Data Sheet AD5676
Rev. D | Page 29 of 30
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARITY
0.10
Figure 53. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-11.
4.10
4.00 SQ
3.90
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.75
2.60 SQ
2.35
1
20
6
10
11
15
16
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-12-2017-C
EXPOSED
PAD
PKG-003502
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 54. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Resolution Temperature Range Accuracy Package Description Package Option
AD5676ARUZ
16 Bits
−40°C to +125°C
±8 LSB INL
20-Lead TSSOP
RU-20
AD5676ARUZ-REEL7
16 Bits
−40°C to +125°C
±8 LSB INL
20-Lead TSSOP
RU-20
AD5676BRUZ 16 Bits −40°C to +125°C ±3 LSB INL 20-Lead TSSOP RU-20
AD5676BRUZ-REEL7 16 Bits −40°C to +125°C ±3 LSB INL 20-Lead TSSOP RU-20
AD5676ACPZ-REEL7 16 Bits −40°C to +125°C ±8 LSB INL 20-Lead LFCSP CP-20-8
AD5676ACPZ-RL 16 Bits −40°C to +125°C ±8 LSB INL 20-Lead LFCSP CP-20-8
AD5676BCPZ-REEL7 16 Bits −40°C to +125°C ±3 LSB INL 20-Lead LFCSP CP-20-8
AD5676BCPZ-RL 16 Bits −40°C to +125°C ±8 LSB INL 20-Lead LFCSP CP-20-8
EVAL-AD5676SDZ Evaluation Board
1 Z = RoHS Compliant Part.
momma Analug Dam, mun vigmx Venn/1d. Tindemivkx ind ANALOG DEVICES www.ana|og.nnm
AD5676 Data Sheet
Rev. D | Page 30 of 30
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12549-0-5/18(D)