Datenblatt für PT7C4337A,AC von Diodes Incorporated

Using external 32.768k1-lz quartz crystal for PT7C4337A Using internal 32.768kHz quartz crystal for PT7C4337AC Supports Izc-Bus's high speed mode (400 kHz) Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD code) Programmable square wave output signal Two Time-of—Day Alarms Oscillator Stop Flag Operating range: 1.8V to 5.5V Timekeeping range 1.2V to 1.8V Totally LeadrFree 8r Fully RoHS Compliant (Notes 1 8r 2) Halogen and Antimony Free. “Green" Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-QlOO/lfll/ZOO, PPAP capable, and manufactured in IATF 16949 certified facilities). please contact us or your local Diodes representative. https:z/www.diodes.com/guality/product-definitionsl Packaging 8-Pin. SOIC (W) 8-Pin, MSOl’ (U) 8-Pin. TSSOP (L) 16min, sow (s) ‘ l mPE/e/CUM‘ PT704337A/4337AC The PT7C4337A/4337AC serial real-time clock is a low-power clock/calendar with two programmable time-of—dav alarms and a programmable square-wave output. Address and data are transferred serially via a 2-wire. bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date. month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the Z4rhour or 12.nour format with AM/PM indicator. The device is fully accessible through the serial interface while VCC is between 1.8V and 5.5V, 12C operation is not guaranteed below 1.8V. Timekeeping operation is maintained with VCC as low as 1.2V. Table 1 shows the basic functions of PT7C4337A/ 4337AC. More details are shown in section: overview of functions. mo
Real-time Clock Module (I2C Bus)
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PT7C4337A/4337AC
Features
Description
Table 1. Basic functions of PT7C4337A/4337AC
Item
Function
PT7C4337A
PT7C4337AC
1
Oscillator
Source
External crystal
Integrated Crystal
Oscillator enable/disable
Oscillator fail detect
2
Time
Time
display
12-hour
24-hour
Century bit
Time count chain enable/disable
3
Interrupt
Alarm interrupt output
2
2
4
Programmable square wave output (Hz)
1, 4.096k, 8.192k, 32.768k
1, 4.096k, 8.192k, 32.768k
5
Communication
2-wire I2C bus
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm
antimony compounds.
ms Dioé‘ei'i’rifiiagfié’é IDPER/CDM‘ P1704337A/4337AC WWI—IN |_||_||_||_| SOIC-8, MSOP-8 And TSSOPVB HHHHHI‘II‘II‘I UUUULILILILI
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Document Number DS43090 Rev 1-2 2 © Diodes Incorporated
PT7C4337A/4337AC
Pin Configuration
X2
INTA
GND
VCC
SQW/INTB
SCL 6
7
8
1
2
3
X1
45
SDA
PT7C4337A
SOIC-8, MSOP-8,
TDFN-8, TSSOP-8
GND
VCC
NC
SDA
SQW/INTB
INTA 14
15
16
1
2
3
SCL
413
NC
PT7C4337AC
SOIC-16
NC
NC
NC
NC
NC
NC 10
11
12
5
6
7
NC
89
NC
Pin Description
4337A
Pin#
4337AC
SOIC
Pin#
Pin
Type
Description
1
/
X1
I
Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected
between them. Or external clock input.
2
/
X2
O
Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected
between them. When 32.768kHz external input, X2 must be float.
6
1
SCL
I
Serial Clock Input. SCL is used to synchronize data movement on the I2C
serial interface.
5
16
SDA
I/O
Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial
interface. The SDA pin is open-drain output and requires an external pull-up
resistor.
3
14
INTA
O
Interrupt Output. When enabled, INTA is asserted low when the time
matches the values set in the alarm registers. This pin is an open-drain output
and requires an external pull up resistor.
7
2
SQW/INTB
O
Square-Wave/Interrupt Output. Programmable square-wave or interrupt
output signal. It is an open-drain output and requires an external pull up
resistor.
8
3
VCC
P
Power. Primary power for PT7C4337A.
4
15
GND
P
Ground.
/
5-13
NC
No Connect. These pins are not connected internally, but must be grounded for
proper operation.
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PT7C4337A/4337AC
Maximum Ratings
Storage Temperature ............................................................ -65℃ to +150℃
Supply Voltage to Ground Potential (VCC to GND) ............... -0.3V to +6.5V
DC Input (All Other Inputs except Vcc & GND) .......................................
-0.3V to (Vcc +0.3V)
DC Output Voltage (SDA, /INTA, /INTB pins) ....................................... -0.3V to +6.5V
DC Output Current (FOUT) ............................................... -0.3V to (Vcc +0.3V)
Power Dissipation ............................................ 320mW(depend on package)
Junction Temperature ..................................................................... 125℃max
Operating Mode
The amount of current consumed by the PT7C4337A is determined, in part, by the I2C interface and oscillator operation. The
following table shows the relationship between the operating mode and the corresponding ICC parameter.
Operating Mode
VCC
Power
I2C Interface Active
1.8V ≤ VCC ≤ 5.5V
ICC Active (ICCA)
I2C Interface Inactive
1.8V ≤ VCC ≤ 5.5V
ICC Standby (ICCS)
I2C Interface Inactive
1.2V ≤ VCC ≤ 1.8V
Timekeeping (ICCTOSC)
I2C Interface Inactive, Oscillator Disabled
1.2V ≤ VCC ≤ 1.8V
Data Retention (ICCTDDR)
Recommended Operating Conditions
Part No.
Sym.
Description
Min
Type
Max
Unit
PT7C4337A
PT7C4337AC
VCC
VCC supply voltage
1.8
3.3
5.5
V
VCCT
1.2
-
1.8
VOSC
Oscillator start up voltage
1.2
-
5.5
VIH
Input high level
SCL, SDA
0.7VCC
-
VCC+0.3
INTA, SQW/INTB
-
-
5.5
VIL
Input low level
-0.3
-
0.3VCC
TA
Operating temperature
-40
-
85
ºC
DC Electrical Characteristics
Unless otherwise specified, VCC = 1.8~5.5V, TA = -40 °C to +85 °C
Sym.
Item
Pin
Condition
Min
Typ
Max
Unit
VCC
Supply voltage
VCC
Full operation
1.8
-
5.5
V
VCCT
Timekeeping (Note 5)
1.2
-
1.8
VOSC
Oscillator voltage
VCC
1.2
-
5.5
V
VIL1
Low-level input voltage
SCL
-0.3
-
0.3VCC
V
VIH1
High-level input voltage
SCL
0.7VCC
-
VCC+0.3
VIL2
Low-level input voltage
X1
-
0.53
-
V
VIH2
High-level input voltage
X1
-
0.53
-
IOL
Low-level output current
SDA, /INTA, /INTB
VOL = 0.4V
3
-
-
mA
IIL
Input leakage current
SCL
-1
-
1
A
IOZ
Output current when OFF
SDA, /INTA, /INTB
-1
-
1
A
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
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PT7C4337A/4337AC
DC Electrical Characteristics
Sym.
Item
Pin
Condition
Min
Typ
Max
Unit
Unless otherwise specified, VCC = 1.3~1.8V, TA = -40 °C to +85 °C
ICCTOSC
Timekeeping current
VCC
Note 2, 4, 5
-
450
800
nA
ICCTDDR
Data retention current
VCC
Note 2,4,5,6
-
-
160
Unless otherwise specified, VCC = 1.8~3.6V, TA = -40 °C to +85 °C
ICCA
Active supply current
VCC
Note 1, 5
-
-
100
A
ICCS
Standby current
VCC
Note 2, 3, 5
-
0.6
1.0
Unless otherwise specified, VCC = 3.6~5.5V, TA = -40 °C to +85 °C
ICCA
Active supply current
VCC
Note 1, 5
-
-
150
A
ICCS
Standby current
VCC
Note 2, 3, 5
-
1.0
1.8
Note:
1. SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
2. Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC.
3. SQW enabled.
4. Specified with the SQW function disabled by setting INTCN = 1.
5. Using recommended crystal on X1 and X2.
6. Crystal oscillator is disabled.
Frequency Characteristics
PT4337AC
Sym.
Description
Condition
Rating
Unit
f / f
Frequency tolerance
TA = +25°C
VDD = 3.3 V
Stability AC: 0 ± 30
10 -6
f / V
Frequency voltage
characteristics
TA = +25°C
VDD = 2 V to 5 V
± 2 Max.
10 -6 / V
Top
Frequency temperature
characteristics
TA = -10°C to +70°C,
VDD = 3.3 V; +25°C reference
+10 / -120
10 -6
tSTA
Oscillation start up time
TA = +25°C
VDD = 3.3 V
3 Max.
s
fa
Aging
TA = +25°C
VDD=3.0 V; first year
± 5 Max.
10 -6 / year
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PT7C4337A/4337AC
Recommended Layout for Crystal (Only for PT7C4337A)
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
Typ
Unit
Build-in capacitors
X1 to GND
CG
12
pF
X2 to GND
CD
12
pF
Recommended External capacitors for
crystal CL=12.5pF
X1 to GND
C1
12
pF
X2 to GND
C2
12
pF
Recommended External capacitors for
crystal CL=6pF
X1 to GND
C1
0
pF
X2 to GND
C2
0
pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768KHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Nominal Frequency
fO
-
32.768
-
kHz
Series Resistance
ESR
-
-
70
k
Load Capacitance
CL
-
6/12.5
-
pF
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
ms mosairi’nitfigtjgiss IDPEMCDM‘ P1704337A/4337AC HM [C m. [C ‘SU 3T0 A a 44m 4?
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PT7C4337A/4337AC
AC Electrical Characteristics
Sym
Description
Value
Unit
VHM
Rising and falling threshold voltage high
0.8 VCC
V
VHL
Rising and falling threshold voltage low
0.2 VCC
V
Over the operating range
Symbol
Item
Min.
Typ.
Max.
Unit
fSCL
SCL clock frequency
-
-
400
kHz
tSU;STA
START condition set-up time
0.6
-
-
s
tHD;STA
START condition hold time
0.6
-
-
s
tSU;DAT
Data set-up time (RTC read/write)
200
-
-
ns
tHD;DAT1
Data hold time (RTC write)
35
-
-
ns
tHD;DAT2
Data hold time (RTC read)
0
-
-
s
tSU;STO
STOP condition setup time
0.6
-
-
s
tBUF
Bus idle time between a START and STOP condition
1.3
-
-
s
tLOW
When SCL = "L"
1.3
-
-
s
tHIGH
When SCL = "H"
0.6
-
-
s
tr
Rise time for SCL and SDA
-
-
0.3
s
tf
Fall time for SCL and SDA
-
-
0.3
s
tSP*
Allowable spike time on bus
-
-
50
ns
CB
Capacitance load for each bus line
-
-
400
pF
CI/O *
I/O Capacitance (SDA, SCL)
-
-
10
pF
TOSF
Oscillator Stop Flag (OSF) Delay
-
-
100
ms
* Note: only reference for design
Signal
tf
tr
VHM
VLM
SSr P
tHD;STA tSP
tSU;DAT
tHD;STA tHD;DAT tSU;STA tSU;STO
SCL
SDA
tBUF
tHD;STA
tSU;STA
fSCL
tLOW tHIGH
Sr
S P
Start condition
Restart condition
Stop condition
m5» assassins; (DPERICOM‘ P1704337A/4337AC ‘7 ‘— %. if 4» > T J. a i r 4 4* ‘i l 7 i v v i l 4 e 74 4» <-—> The PT7C4337A uses an external 32.768 kHz crystal. TableZ specifies several crystal parameters for the external crystal. The Block Diagram shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a cwstal with the specified characteristics. The accuracy ofthe clock is dependent upon the accuracy ofthe crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a typical PC board layout for isolating the crystal and oscillator from noise. The PT7C4337AC integrates a standard 32.768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C is approximately 10ppm.
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Document Number DS43090 Rev 1-2 7 © Diodes Incorporated
PT7C4337A/4337AC
Function Block
Oscillator Circuit
PT7C4337A
Table 2. Crystal Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Nominal Frequency
fO
-
32.768
-
kHz
Series Resistance
ESR
-
-
70
k
Load Capacitance
CL
-
6/12.5
-
pF
Note: The crystal, traces, and crystal input pins should be isolated from RF generating signals.
Clock Accuracy
PT7C4337AC
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
Interrupt Control
Square Wave Output Control
Comparator 1
Alarm 2 Register
(Min, Hour, Day/Date)
Comparator 2
Alarm 1 Register
(Sec, Min, Hour, Day/Date)
Shift Register
Address
Decoder Address
Register
INTA
SQW/INTB
SCL
SDA
PT7C4337
OSC
X1
X2
CG
CD
32.768
kHz
Control Register
Counter Chain
I /O
Interface
(I2C)
PT7C4337A
mm Dismisses; (DPBe/com P1704337A/4337AC CPU cAn rend or write (Lita including the year (last two digits), monrht data» day, hour, minute, and second. Any ([M'Ordlgii) year that is a multiple 0” is treated as a leap year and calculated automatically as such until the year 2100. On a power-on reset (FOR), the time and date are set to 00:00:00 01/01/00 (hh:mm:ss DD/MM/YY) and the Day register is set to 01. This device has two alarm system (Alarm 1 and Alarm 2) that outputs interrupt signals from INTA or INTB to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time, The alarm is be selectable between on and off for matching alarm or repeating alarm. A square wave output enable bit controls square wave output at pin 7. Frequencies are selectable: 1, 4.096k, 8.192k, 32.768k Hz. Data is read and written via the PC bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the [/0 pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output 1/0 is also open drain. The SCL‘s maximum clock frequency is 400 kHz. which supports the 17C bus's high-speed mode. When oscillator fail. PT7C4337A OSF bit will be set. Oscillator and time count chain can be enabled or disabled at the same time by /ETIME bit.
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PT7C4337A/4337AC
Function Description
Overview of Functions
Clock Function
Alarm Function
Programmable Square Wave Output
Interface with CPU
Oscillator Fail Detect
Oscillator Enable/Disable
Registers
Allocation of registers
Addr.
(hex)*1
Function
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
Seconds (00-59)
0
S40
S20
S10
S8
S4
S2
S1
01
Minutes (00-59)
0
M40
M20
M10
M8
M4
M2
M1
02
Hours (00-23 / 01-12)
0
12, /24
H20 or
P, /A
H10
H8
H4
H2
H1
03
Days of the week (01-07)
0
0
0
0
0
W4
W2
W1
04
Dates (01-31)
0
0
D20
D10
D8
D4
D2
D1
05
Months (01-12)
Century
0
0
MO10
MO8
MO4
MO2
MO1
06
Years (00-99)
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
07
Alarm 1: Seconds
A1M1*2
S40
S20
S10
S8
S4
S2
S1
08
Alarm 1: Minutes
A1M2*2
M40
M20
M10
M8
M4
M2
M1
09
Alarm 1: Hours
A1M3*2
12, /24
H20 or
P, /A
H10
H8
H4
H2
H1
0A
Alarm 1: Day, Date
A1M4*2
Day,
/Date
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
0B
Alarm 2: Minutes
A2M2*3
M40
M20
M10
M8
M4
M2
M1
0C
Alarm 2: Hours
A2M3*3
12, /24
H20 or
P, /A
H10
H8
H4
H2
H1
m5» Dismisses; (DPERICOM‘ P1704337A/4337AC Oscillator Stops Flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the Validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the USP bit to be set: 1) The first time power is applied. 2) The voltage present on VCC is insufficrent to support oscillation. 3) The /ETIME bit is turned off. 4) External influences on the crystal (eg t noise, leakaget etc.). This bit remains at logic 1 until written to logic 0.
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PT7C4337A/4337AC
Addr.
(hex)*1
Function
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0D
Alarm 2: Day, Date
A2M4*3
Day,
/Date
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
0E
Control
/ETIME*4
0
0
RS2*5
RS1*5
INTCN*6
A2IE*7
A1IE*7
0F
Status
OSF*9
0
0
0
0
0
A2F*8
A1F*8
Caution points:
*1. PT7C4337A uses 8 bits for address. For excess 0FH address, PT7C4337A will not respond (no acknowledge signal was given).
*2. Alarm 1 mask bits. Select alarm repeated rate when an alarm occurs.
*3. Alarm 2 mask bits. Select alarm repeated rate when an alarm occurs.
*4. Oscillator and time count chain enable/disable bit.
*5. Square wave output frequency select.
*6. Interrupt output pin select bit.
*7. Alarm 1 and alarm 2 enable bits.
*8. Alarm 1 and alarm 2 flag bits.
*9. Oscillator stops flag.
*10. All bits marked with "0" are read-only bits. Their value when read is always "0".
Control and Status Register
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
0E
Control
/ETIME
0
0
RS2
RS1
INTCN
A2IE
A1IE
(default)
0
0
0
1
1
0
0
0
0F
Status
OSF
0
0
0
0
0
A2F
A1F
(default)
1
0
0
0
0
0
Undefined
Undefined
Oscillator Related Bits
/ETIME
Enable oscillator and time count chain bit.
/ETIME
Data
Description
Read / Write
0
Enable oscillator and time count chain.
Default
1
Disable oscillator and time count chain.
OSF
A Product Line of Diodes Incorporated ms; IDPER/CDM‘ P1704337A/4337AC Square wave Rate Select. These bits control the frequency of [he square-wave output when the square wave has been enabled‘
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PT7C4337A/4337AC
Square Wave Frequency Selection Bits
RS2, RS1
RS2, RS1
Data
SQW output freq. (Hz)
Read / Write
00
1
01
4.096k
10
8.192k
11
32.768k
Default
Interrupt Related Bits
INTCN
Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins.
INTCN
Data
Description
Read /
Write
1
A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the
alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates
the SQW/INTB pin (if the alarm 2 is enabled).
0
A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates
the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on
the SQW/INTB pin.
Default
A1IE
Alarm 1 Interrupt Enable.
A1IE
Data
Description
Read / Write
0
The A1F bit does not initiate the INTA signal.
Default
1
Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.
A1F
Alarm 1 Flag.
A1F
Data
Description
Read / Write
0
The time do not match the alarm 1 registers.
Default
Read
1
Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes
low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
A2IE
Alarm 2 Interrupt Enable.
A2IE
Data
Description
Read /
Write
0
The A2F bit does not initiate an interrupt signal.
Default
1
Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert
SQW/INTB (when INTCN = 1).
m5» mosgiaifigtigiss (DPERICDM‘ P1704337A/4337AC Time digit displ '(in BCD code); Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00, Hour digits; See description on the /12, 24 bit, Carried to day and day-of—the-week digits when incremented from 11 pm, to 12 am or 23 to 00,
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Document Number DS43090 Rev 1-2 11 © Diodes Incorporated
PT7C4337A/4337AC
A2F
Alarm 2 Flag.
A1F
Data
Description
Read /
Write
0
The time do not match the alarm 2 registers.
Default
Read
1
Indicates that the time matched the alarm 1 registers. This flag can be used to generate an interrupt on
either INTA or SQW/INTB depending on the status of the INTCN bit. If the INTCN = 0 and A2F = 1
(and A2IE = 1), the INTA pin goes low. If the INTCN = 1 and A2F = 1 (and A2IE = 1), the
SQW/INTB pin goes low. A2F is cleared when written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Time Counter
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
00
Seconds
0
S40
S20
S10
S8
S4
S2
S1
(default)
0
0
0
0
0
0
0
0
01
Minutes
0
M40
M20
M10
M8
M4
M2
M1
(default)
0
0
0
0
0
0
0
0
02
Hours
0
12, /24
H20 or P,/A
H10
H8
H4
H2
H1
(default)
0
0
0
0
0
0
0
0
Note: Any registered imaginary time should be replaced with correct time, otherwise it will cause the clock counter malfunction.
12, /24 bit
This bit is used to select between 12-hour clock system and 24-hour clock system.
12, /24
Data
Description
Read / Write
0
24-hour system
1
12-hour system
m5. mosgiaisfigtisiss (DPERICOM‘ P1704337A/4337AC The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. The data format is BCD format. Day digits: Range from 1 to 31 (for January, March. May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 23 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and 00, 04. 08, , 92 and 96 are counted as leap years.
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Document Number DS43090 Rev 1-2 12 © Diodes Incorporated
PT7C4337A/4337AC
This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12, /24
Description
Hours register
0
24-hour time display
1
12-hour time display
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
Days of the week Counter
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
03
Days of the week
0
0
0
0
0
W4
W2
W1
(default)
0
0
0
0
0
0
0
1
Calendar Counter
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
04
Dates
0
0
D20
D10
D8
D4
D2
D1
(default)
0
0
0
0
0
0
0
1
05
Months
Century*1
0
0
M10
M8
M4
M2
M1
(default)
0
0
0
0
0
0
0
1
06
Years
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(default)
0
0
0
0
0
0
0
0
*1: The century bit is toggled when the years register overflows from 99 to 00.
24-hour clock
12-hour clock
24-hour clock
12-hour clock
00
52 ( AM 12 )
12
72 ( PM 12)
01
41 ( AM 01 )
13
61 ( PM 01 )
02
42 ( AM 02 )
14
62 ( PM 02 )
03
43 ( AM 03 )
15
63 ( PM 03 )
04
44 ( AM 04 )
16
64 ( PM 04 )
05
45 ( AM 05 )
17
65 ( PM 05 )
06
46 ( AM 06 )
18
66 ( PM 06 )
07
47 ( AM 07 )
19
67 ( PM 07 )
08
48 ( AM 08 )
20
68 ( PM 08 )
09
49 ( AM 09 )
21
69 ( PM 09 )
10
50 ( AM 10 )
22
70 ( PM 10 )
11
51 ( AM 11 )
23
71 ( PM 11 )
ms omfii’fifiéfifié’é IDPER/CDM‘ PT704337A/4337AC
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PT7C4337A/4337AC
Alarm Register
Alarm 1, Alarm 2 Register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
07
Alarm 1: Seconds
A1M1*1
S40
S20
S10
S8
S4
S2
S1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
08
Alarm 1: Minutes
A1M2*1
M40
M20
M10
M8
M4
M2
M1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
09
Alarm 1: Hours
A1M3*1
12, /24
H20 or P,/A
H10
H8
H4
H2
H1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0A
Alarm 1: Day, Date
A1M4*1
Day,
/Date*1
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0B
Alarm 2: Minutes
A2M2*2
M40
M20
M10
M8
M4
M2
M1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0C
Alarm 2: Hours
A2M3*2
12, /24
H20 or P,/A
H10
H8
H4
H2
H1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0D
Alarm 2: Day, Date
A2M4*2
Day,
/Date*2
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
(default)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
*1 Note: Alarm mask bit, using to select Alarm 1 alarm rate.
*2 Note: Alarm mask bit, using to select Alarm 2 alarm rate.
Alarm Function
Related Register
Addr.
(hex)
Function
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
Seconds
0
S40
S20
S10
S8
S4
S2
S1
01
Minutes
0
M40
M20
M10
M8
M4
M2
M1
02
Hours
0
12, /24
H20 or
A, /P
H10
H8
H4
H2
H1
03
Days of the week
0
0
0
0
0
W4
W2
W1
04
Dates
0
0
D20
D10
D8
D4
D2
D1
07
Alarm 1: Seconds
A1M1
S40
S20
S10
S8
S4
S2
S1
08
Alarm 1: Minutes
A1M2
M40
M20
M10
M8
M4
M2
M1
09
Alarm 1: Hours
A1M3
12, /24
H20 or
A, /P
H10
H8
H4
H2
H1
0A
Alarm 1: Day, Date
A1M4
Day,
/Date
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
0B
Alarm 2: Minutes
A2M2
M40
M20
M10
M8
M4
M2
M1
0C
Alarm 2: Hours
A2M3
12, /24
H20 or
A, /P
H10
H8
H4
H2
H1
0D
Alarm 2: Day, Date
A2M4
Day,
/Date
0,
D20
0,
D10
0,
D8
W4,
D4
W2,
D2
W1,
D1
0E
Control
/ETIME
0
0
RS2
RS1
INTCN
A2IE
A1IE
0F
Status
OSF
0
0
0
0
0
A2F
A1F
Note: Alarm function does not support different hour system adopted in time and alarm register.
MS. assesses; (DPBe/com P1704337A/4337AC The PT7C4337A contains two time-of—day/date alarms. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes , each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of—day/date alarm registers are mask bits. When all ofthe mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers ooh ~ 04h match the values stored in the time-of—day/date alarm registers, The alarms can also be programmed to repeat every second, minute. hour, day. or date. Table 2 and Table 3 showthe possible settings. The Day. /Date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register reflects the day of the week or the date ofthe month. If the bit is written to logic 0. the alarm is the result ofa match with date of the month. lithe bit is written to logic 1. the alarm is the result ofa match with day ofthe week. When the PT7C4337A register values match alarm register settings. the corresponding alarm flag (AIF or AZF) bit is set to logic 1. lithe corresponding alarm interrupt enable (AlIE or AZIE) is also set to logic 1. the alarm condition activates one ofthe interrupt output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update ofthe time and date registers.
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PT7C4337A/4337AC
Table 3. Alarm 1 Mask Bits
Day,
/Date
Alarm 1 register mask bits
Alarm Rate
A1M4
A1M3
A1M2
A1M1
1
1
1
1
Alarm once per second
1
1
1
0
Alarm when seconds match
1
1
0
0
Alarm when minutes and seconds match
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
Others
Ignored.
Table 4. Alarm 2 Mask Bits
Day,
/Date
Alarm 2 register mask bits
Alarm Rate
A2M4
A2M3
A2M2
1
1
1
Alarm once per minute (00 seconds of every minute)
1
1
0
Alarm when minutes match
1
0
0
Alarm when hours, minutes
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
Others
Ignored.
m5. D.o§;'.°.d.:i;t:s%:; (DPBe/com P1704337A/4337AC The PC bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination ofthese two signals is used to transmit and receive communication start/stop signals, data signals. acknowledge signals. and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping ofcommunications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case. the data is transferred via the SCL line at a rate ofone bit per clock pulse. The PC bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. All ports connected to the PC bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed).
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PT7C4337A/4337AC
I2C Bus Interface
Overview of I2C-BUS
System Configuration
Figure 1. System Configuration
Master
MCU Slave
RTC Other Peripheral
Device
Vcc
SDA
SCL
Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
RPRP
m5. assesses; IDPER/caM P1704337A/4337AC Repealed START 055(Max) a) START condition SDA level changes from high to low while SCL is at high level h) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP Conditions in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. a) Data Transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred, There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating ofdata on the transmitter (transmitting side)‘s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. SCL \ SDA Data is valid Data can be when data line is changed stable when transferring data» the receiver generates a confirmation response (ACK signal, low active) each time an 87bit data segment is received. Ifthere is no ACK signal from the receiver. it indicates that normal communication has not been established, (This does not include instances where the master device intentionally does not generate an ACK signal.)
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PT7C4337A/4337AC
Starting and Stopping I2C Bus Communications
Figure 2. Starting and Stopping on I2C Bus
1) START Condition, Repeated START Condition, and STOP Condition
2) Data Transfers and Acknowledge Responses during I2C-BUS Communication
a) Data Transfers
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP
condition.
b) Data Acknowledge Response (ACK signal)
MS. assassinate"; (DPBe/com P1704337A/4337AC Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (: acknowledge) level. After transmitting the ACK signal. if the Master remains the receiver for transfer of the next lme, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slav . that indicates to the transmitter that data transfer has ended. At that point. the transmitter continues to release the SDA and awaits a STOP condition from the Master. The PC bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin. slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ Rm} specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/Wbit is added to each 7-bit slave address during 8-bit transfers.
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Document Number DS43090 Rev 1-2 17 © Diodes Incorporated
PT7C4337A/4337AC
Slave Address
Operation
Transfer data
Slave address
R / W bit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
D1 h
1
1
0
1
0
0
0
1 (= Read)
Write
D0 h
0 (= Write)
I2C Bus’s Basic Transfer Format
SCL from Master 128 9
SDA from transmitter
(sending side)
SDA from receiver
(receiving side)
Release SDA
Low active
ACK signal
SStart indication PStop indication
Sr Restart indication
ARTC Acknowledge
AMaster Acknowledge
ms omfii’fifiéfifié’é IDPER/CDM‘ PT704337A/4337AC
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PT7C4337A/4337AC
1) Write via I2C Bus
2) Read via I2C bus
a) Standard Read
b) Simplified Read
Note:
1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications.
2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
Slave address (7 bits)
1 1 0 1 0 0 0 0
write
Addr. setting
Slave address + write specification Address
Specifies the write start address.
Abit
7 6 5 4 3 2 1 0
bit bit bit bit bit bit bit A P
Write data
S A
A
C
K
A
C
K
A
C
K
Start Stop
Slave address (7 bits)
1 1 0 1 0 0 0 0
write
Slave address + write specification Address
Specifies the read start address.
Addr. setting AS
Slave address (7 bits)
1 1 0 1 0 0 0 1
Read
Slave address + read specification Data read (1)
Data is read from the specified start
address and address auto increment.
Abit
7 6 5 4 3 2 1 0
bit bit bit bit bit bit bit /A PSr 7 6 5 4 3 2 1 0
bit bit bit bit bit bit bitbit
Data read (2)
Address auto increment to set the
address for the next data to be read.
A
C
K
N
O
A
C
K
A
A
C
K
A
C
K
A
C
K
A
Start
StopRestart
Data read (2)
Address register auto increment to set
the address for the next data to be
read.
Data read (1)
Data is read from the address pointed
by the internal address register and
address auto increment.
Slave address (7 bits)
1 1 0 1 0 0 0 1
Read Abit
7 6 5 4 3 2 1 0
bit bit bit bit bit bit bit /A PS 7 6 5 4 3 2 1 0
bit bit bit bit bit bit bitbit
A
C
K
N
O
A
C
K
A
C
K
A
StopStart Slave address + read specification
w Package PT7C 4337AWE SYWXX 5, Die Rev Yi Date Code (Year) W' Date Code (Workweek) 2nd X: Assembly Site Code 3rd X. Fab Site Code U and 1. Package s Package 7C4337ACSE PT swwwee 8 Die Rev YYWW Dale Code (Year & Workweek) 131 G. Assembly Site Code 2nd (3: Wafer Fab Site Code A Product Line of Diodes Incorporated (DPBe/caM‘ P1704337A/4337AC
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Part Marking
PT7C4337A
Top mark not available at this time. To obtain advance information regarding the top mark, please contact your local sales representative.
PT7C4337AC
dd. (DPEHCDM‘ P1704337A/4337AC H5 H H ’- 5 “NEWS MIN. WM. ”AX. A — — 1.75 M 0.10 - 0.25 A2 ‘25 - - E w ,3, b DJI _ I) 5| 1 c 0.10 0.25 O D 4.80 ‘30 5.00 E 5.80 5.00 6.20 — H j [I 5.30 3.90 L00 — ‘ ‘ o 1.17 BSD c L 0J0 - 1.17 h ' h {1.25 — 0.50 9' o - a a um : mm fi 4 Emma sum mi 5 mm ‘ m ME 7 :m m7 5' IDPBQIL‘DM‘ “'2 W" _........._..., mm: l—Pill. INHIW,“ m‘m‘mu_m-miu mm: cons: w m) :wflflmmeum nocuuzmeoumt Inn-11m mm: a .5 am:
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Packaging Mechanical
8-SOIC (W)
ms» S-MSOP (U) A Product Line of Diodes Incorporated (DPBe/caM‘ P1704337A/4337AC L1 A1 mate: I. Au. mueuaous ARE Iu MILLIMEI'ES. AueLes m neenees. mesa: Jenec no.1 ”MA 3. rAcKAae ouruue meuaons no um- Incwne mm mm Ann METAL sum. 4. we FATIERN nereneuce mane: "sop-l rAcKAee mrommou. 4 a We D‘MENS‘ONstl vaBoL Mm Max _ A 7 «m m nun ms A2 H75 095 b n22 m 0 one 023 D m m E 455 515 a m 320 e usaasc L m | m u was; s e o- | s- RECOMMENDED LAND FAITEKMumczmm) onenunms ms DESCRIPTION: x-Pm, Mlm Small outline Package, MsoP PACKAGE cone: U (U8) nocuMENr CONTROL a: PD-1ZB1 REVISION: u 1971147
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8-MSOP (U)
ms. dd. (DPEHCDM‘ P17c4337A/4337AC S-TSSOP (L) ITH H W ' SYMBOLS MIN. NOM. MAX. A , , 1.20 A. 0.05 — 0.15 42 0.00 1.00 1.05 b 0.19 — 0.30 .0 c 0.09 — 0.20 D 290 3.00 3 ‘D E 5.20 5.40 5.60 O E] 0.55 asc :1 4.30 4.40 4.50 U L 0.45 0.60 0.75 _ 4 LI 100 REF 5 0.20 , , n a 9' 0 , 5 UNIT : MM D a o MICE PLANE } 9 same mu: : a < u="" (dpbq/cam'="" ”"e="" w“="" ”we...“="" notes:="" 55mm="" *1",="" imi="" wis!="" rm="" 1.="" u="" numsoeos="" m="" 04mm,="" mu:="" m="" mm="" 2.="" m="" mam/u="" mum-soon="" .="" (u;="" 0="" mm="" um="" um="" mum:="" mu:="" mn.="" ”www="" on="" we="" was.="" mulancoumt="" fl!"="" rhiiioi:="" fl="" iboogz="">
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PT7C4337A/4337AC
8-TSSOP (L)
mm Diosgfnifitigiss (DPBe/com P1704337A/4337AC lfi-SOIC (S) 1 6 H H H H 'H H H H 0 g L 0 E1 we DIMENswoNsMM» swam. win Max < a="" 2="" 35="" 2="" an="" m="" o="" 10="" o="" w="" n="" a="" 33="" a="" 51="" c="" a="" u="" o="" 32="" u="" m="" m="" «a="" 59="" e="" 7="" w="" 7="" so="" 51="" 10="" no="" «0="" as="" 1="" 21="" 35¢="" a="" u="" «21="" 0°="" 3°="" one:="" 08129114="" (ppr/mill="" "a";="" “nun-m.="" 4="" ref="" jedec="" n‘s-013m="" description:="" is-pvn‘="" so":="" (3w="" milwide)="" package="" cone:="" 5="" [513)="" nocumem="" con'irol="" *="" pn-mos="" revision:="" e="" 14-0235="" fur="" mm="" package="" info.="" please="" check-="" http'//www.dlodes.comldeslgnlsuppoli/packngmg/pelicem-packngmg/pnckagmg-mechamcals-nnd-||\2rmal-chalacxensllcs/="" pt7c4337acsex="" lfirfin,="" 300m|l="" w|de="" soic="">
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PT7C4337A/4337AC
16-SOIC (S)
Ordering Information
Part Number
Package Code
Package Description
PT7C4337AWEX
W
8-Pin, 150mil-Wide (SOIC)
PT7C4337AUEX
U
8-Pin, Mini Small Outline Package (MSOP)
PT7C4337ALEX
L
8-Pin, 173mil Wide (TSSOP)
PT7C4337ACSEX
S
16-Pin, 300mil Wide (SOIC)
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and
Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. E = Pb-free and Green
5. X suffix = Tape/Reel
ms!) mosgmfigtigiss (DPHe/com P1704337A/4337AC
PT7C4337A/4337AC www.diodes.com August 2020
Document Number DS43090 Rev 1-2 24 © Diodes Incorporated
PT7C4337A/4337AC
IMPORTANT NOTICE
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE
LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice
to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any
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whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes
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LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of
the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and
agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in
such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated.
Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such
safety-critical, life support devices or systems.
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