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BQ297xx Cost-Effective Voltage and Current Protection Integrated Circuit for Single-

Cell Li-Ion and Li-Polymer Batteries

1 Features

• Input voltage range pack+: VSS – 0.3 V to 12 V

• FET drive:

– CHG and DSG FET drive output

• Voltage sensing across external FETs for

overcurrent protection (OCP) is within ±5 mV

(typical)

• Fault detection

– Overcharge detection (OVP)

– Over-discharge detection (UVP)

– Charge overcurrent detection (OCC)

– Discharge overcurrent detection (OCD)

– Load short-circuit detection (SCP)

• Zero voltage charging for depleted battery

• Factory programmed fault protection thresholds

– Fault detection voltage thresholds

– Fault trigger timers

– Fault recovery timers

• Modes of operation without battery charger

enabled

– NORMAL mode ICC = 4 µA

– Shutdown Iq = 100 nA

• Operating temperature range TA = –40°C to +85°C

• Package:

– 6-pin DSE (1.50 mm × 1.50 mm × 0.75 mm)

2 Applications

•Tablet PCs

•Mobile handsets

•Handheld data terminals

3 Description

The BQ2970 battery cell protection device provides

an accurate monitor and trigger threshold for

overcurrent protection during high discharge/charge

current operation or battery overcharge conditions.

The BQ2970 device provides the protection functions

for Li-ion/Li-polymer cells, and monitors across the

external power FETs for protection due to high

charge or discharge currents. In addition, there is

overcharge and depleted battery monitoring and

protection. These features are implemented with low

current consumption in NORMAL mode operation.

Device Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)

BQ2970, BQ2971,

BQ2972, BQ2973 WSON (6) 1.50 mm × 1.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DOUT

COUT

V–

BAT

VSS

PACK +

PACK–

CELLN

CELLP

S S

0.1 µF

2.2 k

DSGCHG

330

Simplified Schematic

±4.0

±3.5

±3.0

±2.5

±2.0

±1.5

±1.0

±0.5

0.0

±40 ±20 0 20 40 60 80 100 120

OCD Detection Accuracy (mV)

Temperature (ƒC)

C012

OCD Detection Accuracy Versus Temperature

BQ2970, BQ2971, BQ2972, BQ2973

SLUSBU9H – MARCH 2014 – REVISED JUNE 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table............................................... 3

6 Pin Configuration and Functions...................................3

6.1 Pin Descriptions.......................................................... 4

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................5

7.5 DC Characteristics...................................................... 5

7.6 Programmable Fault Detection Thresholds................ 6

7.7 Programmable Fault Detection Timer Ranges............6

7.8 Typical Characteristics................................................ 7

8 Parameter Measurement Information.......................... 10

8.1 Timing Charts............................................................10

8.2 Test Circuits.............................................................. 12

8.3 Test Circuit Diagrams................................................14

9 Detailed Description......................................................14

9.1 Overview................................................................... 14

9.2 Functional Block Diagram......................................... 15

9.3 Feature Description...................................................15

9.4 Device Functional Modes..........................................15

10 Application and Implementation................................ 19

10.1 Application Information........................................... 19

10.2 Typical Application.................................................. 19

11 Power Supply Recommendations..............................22

12 Layout...........................................................................22

12.1 Layout Guidelines................................................... 22

12.2 Layout Example...................................................... 22

13 Device and Documentation Support..........................23

13.1 Related Documentation.......................................... 23

13.2 Support Resources................................................. 23

13.3 Trademarks............................................................. 23

13.4 Electrostatic Discharge Caution..............................23

13.5 Glossary..................................................................23

14 Mechanical, Packaging, and Orderable

Information.................................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (December 2018) to Revision H (June 2021) Page

• Changed the BQ29728 and BQ29737 devices to Production Data....................................................................3

Changes from Revision F (December 2018) to Revision G (January 2020) Page

• Changed the Device Comparison Table ............................................................................................................ 3

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5 Device Comparison Table

PART NUMBER(1) OVP (V) OVP DELAY

(s) UVP (V) UVP DELAY

(ms) OCC (V) OCC DELAY

(ms) OCD (V)

OCD

DELAY

(ms)

SCD (V) SCD DELAY

(µs)

BQ29700 4.275 1.25 2.800 144 –0.100 8 0.100 20 0.5 250

BQ29701 4.280 1.25 2.300 144 –0.100 8 0.125 8 0.5 250

BQ29702 4.350 1 2.800 96 –0.155 8 0.160 16 0.3 250

BQ29703 4.425 1.25 2.300 20 –0.100 8 0.160 8 0.5 250

BQ29704 4.425 1.25 2.500 20 –0.100 8 0.125 8 0.5 250

BQ29705 4.425 1.25 2.500 20 –0.100 8 0.150 8 0.5 250

BQ29706 3.850 1.25 2.500 144 –0.150 8 0.200 8 0.6 250

BQ29707 4.280 1 2.800 96 –0.090 6 0.090 16 0.3 250

BQ29716 4.425 1.25 2.300 20 –0.100 8 0.165 8 0.5 250

BQ29717 4.425 1.25 2.500 20 –0.100 8 0.130 8 0.5 250

BQ29718 4.425 1.25 2.500 20 –0.100 8 0.100 8 0.5 250

BQ29723 4.425 1 2.500 96 –0.060 4 0.100 8 0.3 250

BQ29728 4.280 1.25 2.800 144 –0.100 8 0.150 8 0.5 250

BQ29729 4.275 1.25 2.300 20 –0.100 8 0.130 8 0.5 250

BQ29732 4.280 1.25 2.500 144 –0.100 8 0.190 8 0.5 250

BQ29733 4.400 1.25 2.800 20 –0.100 8 0.120 8 0.3 250

BQ29737 4.250 1 2.800 96 –0.050 16 0.100 16 0.3 250

BQ297xy 3.85–4.6 0.25, 1,

1.25, 4.5 2.0–2.8 20, 96, 125,

144

–0.045 to

–0.155 4, 6, 8, 16 0.090–0.200 8, 16, 20,

0.3, 0.4, 0.5,

0.6 250

(1) All of the protections have a recovery delay time. The recovery timer starts as soon as the fault is triggered. The device starts to check

for a recovery condition only when the recovery timer expires. This is NOT a delay time between recovery condition to FETs recovery.

OVP recovery delay = 12 ms; UVP/OCC/OCD recovery delay = 8 ms.

6 Pin Configuration and Functions

1NC 6 V–

2COUT 5 BAT

3DOUT 4 VSS

Figure 6-1. DSE Package 6-PIN WSON Top View

Table 6-1. Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

BAT 5 P VDD pin

COUT 2 O Gate Drive Output for Charge FET

DOUT 3 O Gate Drive Output for Discharge FET

NC 1 NC No Connection (electrically open, do not connect to BAT or VSS)

VSS 4 P Ground pin

V– 6 I/O Input pin for charger negative voltage

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6.1 Pin Descriptions

6.1.1 Supply Input: BAT

This pin is the input supply for the device and is connected to the positive terminal of the battery pack. A 0.1-µF

input capacitor is connected to ground for filtering noise.

6.1.2 Cell Negative Connection: VSS

This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage

measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense

resistor sensing will be referenced to this node.

6.1.3 Voltage Sense Node: V–

This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or

overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the

differential measurement for the stated fault detection conditions. A 2.2-kΩ resistor is connected between this

input pin and Pack– terminal of the system in the application.

6.1.4 Discharge FET Gate Drive Output: DOUT

This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output transitions from high to low when a fault is detected, and requires the DSG FET to turn

OFF. A 5-MΩ high impedance resistor is connected from DOUT to VSS for gate capacitance discharge when the

FET is turned OFF.

6.1.5 Charge FET Gate Drive Output: COUT

This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn

OFF. A 5-MΩ high impedance resistor is connected from COUT to Pack– for gate capacitance discharge when

FET is turned OFF.

7 Specifications

7.1 Absolute Maximum Ratings

MIN(1) MAX UNIT

Supply control and input Input voltage: BAT –0.3 12 V

V– pin(pack–) BAT – 28 BAT + 0.3 V

FET drive and protection

DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive) VSS – 0.3 BAT + 0.3 V

COUT (Charge FET Output), GCHG (Charge FET Gate Drive) BAT – 28 BAT + 0.3 V

Operating temperature: TFUNC –40 85 °C

Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device

reliability.

7.2 ESD Ratings

VALUE UNIT

VESD (1) Electrostatic

Discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001, all pins(2) ±2000

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins(3) ±500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000

V can have higher performance.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250

V can have higher performance.

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7.3 Recommended Operating Conditions

MIN MAX UNIT

Supply control and input Positive input voltage: BAT –0.3 8 V

Negative input voltage: V– BAT – 25 BAT V

FET drive and protection Discharge FET control: DOUT VSS BAT V

Charge FET control: COUT BAT – 25 BAT V

Temperature Ratings

Operating temperature: TAmb –40 85 °C

Storage temperature: TS–55 150 °C

Lead temperature (soldering 10 s) 300 °C

Thermal resistance junction to ambient, θJA 250 °C/W

7.4 Thermal Information

THERMAL METRIC(1)

BQ297xx

UNITDSE (WSON)

12 PINS

RθJA, High K Junction-to-ambient thermal resistance 190.5 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 94.9 °C/W

RθJB Junction-to-board thermal resistance 149.3 °C/W

ψJT Junction-to-top characterization parameter 6.4 °C/W

ψJB Junction-to-board characterization parameter 152.8 °C/W

RθJC(bottom) Junction-to-case(bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 DC Characteristics

Typical Values stated where TA = 25°C and BAT = 3.6 V. Min/Max values stated where TA = –40°C to 85°C, and BAT = 3 V to

4.2 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Current consumption

VBAT Device operating range BAT – VSS 1.5 8 V

BAT – V– 1.5 28

INORMAL Current consumption in NORMAL mode BAT = 3.8 V, V– = 0 V 4 5.5 µA

IPower_down Current consumption in power down mode BAT = V– = 1.5 V 0.1 µA

FET Output, DOUT and COUT

VOL Charge FET low output IOL = 30 µA, BAT = 3.8 V 0.4 0.5 V

VOH Charge FET high output IOH = –30 µA, BAT = 3.8 V 3.4 3.7 V

VOL Discharge FET low output IOL = 30 µA, BAT = 2 V 0.2 0.5 V

VOH Discharge FET high output IOH = –30 µA, BAT = 3.8 V 3.4 3.7 V

Pullup Internal Resistance on V–

RV–D Resistance between V– and VBAT VBAT = 1.8 V, V– = 0 V 100 300 550 kΩ

Current sink on V–

IV–S Current sink on V– to VSS VBAT = 3.8 V 8 24 µA

Load short detection on V–

Vshort Short detection voltage VBAT = 3.8 V and RPackN = 2.2 kΩ VBAT –

1 V V

0-V battery charge function

V0CHG 0-V battery charging start voltage 0-V battery charging function allowed 1.7 V

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7.5 DC Characteristics (continued)

Typical Values stated where TA = 25°C and BAT = 3.6 V. Min/Max values stated where TA = –40°C to 85°C, and BAT = 3 V to

4.2 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-V battery charge inhibit function

V0INH

0-V battery charging inhibit voltage

threshold 0-V battery charging function disallowed 0.75 V

7.6 Programmable Fault Detection Thresholds

PARAMETER CONDITION MIN TYP MAX UNIT

VOVP Overcharge detection voltage Factory Device Configuration: 3.85 V to

4.60 V in 50-mV steps

TA = 25°C –10 10 mV

TA = 0°C to

60°C –20 20 mV

VOVP–Hys

Overcharge release hysteresis

voltage

100 mV and (VSS – V–) > OCC (min) for release, TA =

25°C –20 20 mV

VUVP

Over-discharge detection

voltage

Factory Device Configuration: 2.00 V to 2.80 V in 50-mV

steps, TA = 25°C –50 50 mV

VUVP+Hys

Over-discharge release

hysteresis voltage 100 mV and (BAT – V–) > 1 V for release, TA = 25°C –50 50 mV

VOCD

Discharging overcurrent

detection voltage

Factory Device Configuration: 90 mV to

200 mV in 5-mV steps

TA = 25°C –10 10 mV

TA = –40°C to

85°C –15 15 mV

Release of

VOCD

Release of discharging

overcurrent detection voltage Release when BAT – V– > 1 V 1 V

VOCC

Charging overcurrent detection

voltage

Factory Device Configuration: –45 mV to

–155 mV in 5-mV steps

TA = 25°C –10 10 mV

TA = –40°C to

85°C –15 15 mV

Release of

VOCC

Release of overcurrent

detection voltage Release when VSS – V– ≥ OCC (min) 40 mV

VSCC Short Circuit detection voltage Factory Device Configuration: 300 mV,

400 mV, 500 mV, 600 mV TA = 25°C –100 100 mV

VSCCR

Release of Short Circuit

detection voltage Release when BAT – V– ≥ 1 V 1 V

7.7 Programmable Fault Detection Timer Ranges

PARAMETER CONDITION MIN TYP MAX UNIT

tOVPD Overcharge detection delay time Factory Device Configuration: 0.25 s, 1 s, 1.25 s, 4.5 s –20% 20% s

tUVPD

Over-discharge detection delay

time

Factory Device Configuration: 20 ms, 96 ms, 125 ms, 144

ms –20% 20% ms

tOCDD

Discharging overcurrent

detection delay time Factory Device Configuration: 8 ms, 16 ms, 20 ms, 48 ms –20% 20% ms

tOCCD

Charging overcurrent detection

delay time Factory Device Configuration: 4 ms, 6 ms, 8 ms, 16 ms –20% 20% ms

tSCCD Short Circuit detection delay time 250 µs (fixed) –50% 50% µs

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7.8 Typical Characteristics

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

±40 ±20 0 20 40 60 80 100 120

Current Consumption (A)

Temperature (ƒC)

C001

VBAT = 1.5 V

Figure 7-1. 1.5-V IBAT Versus Temperature

±40 ±20 0 20 40 60 80 100 120

Current Consumption (A)

Temperature (ƒC)

C002

VBAT = 3.9 V

Figure 7-2. 3.9-V IBAT Versus Temperature

1.18

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

±40 ±20 0 20 40 60 80 100 120

Internal Oscillator Frequency (kHz)

Temperature (ƒC)

C003

FOSC, Setting = 1.255

kHz

Figure 7-3. Internal Oscillator Frequency Versus

Temperature

±1.46

±1.44

±1.42

±1.40

±1.38

±1.36

±1.34

±1.32

±40 ±20 0 20 40 60 80 100 120

V(±) ± BAT Voltage (V)

Temperature (ƒC)

C004

VBAT, Setting = 0 V

Figure 7-4. 0-V Charging Allowed Versus

Temperature

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

±40 ±20 0 20 40 60 80 100 120

BAT ± VSS Voltage (V)

Temperature (ƒC)

C005

Figure 7-5. 0-V Charging Disallowed Versus

Temperature

±12

±10

±8

±6

±4

±2

±40 ±20 0 20 40 60 80 100 120

OVP Deetction Threshold Accuracy (mV)

Temperature (ƒC)

C006

OVP, Setting = 4.275 V

Figure 7-6. OVP Detection Accuracy Versus

Temperature

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1100

1150

1200

1250

1300

1350

±40 ±20 0 20 40 60 80 100 120

OVP Detection Delay Time (ms)

Temperature (ƒC)

C007

tOVPD, Setting = 1.25 s

Figure 7-7. OVP Detection Dely Time Versus

Temperature

±12

±10

±8

±6

±4

±2

±40 ±20 0 20 40 60 80 100 120

UVP Detection Accuracy Threshold (mV)

Temperature (ƒC)

C008

UVP, Setting = 2.800 V

Figure 7-8. UVP Detection Accuracy Versus

Temperature

130

135

140

145

150

155

160

±40 ±20 0 20 40 60 80 100 120

UVP Detection Delay Time (ms)

Temperature (ƒC)

C009

tUVPD, Setting = 144 ms

Figure 7-9. UVP Detection Delay Time Versus

Temperature

±1.8

±1.6

±1.4

±1.2

±1.0

±0.8

±0.6

±0.4

±0.2

0.0

±40 ±20 0 20 40 60 80 100 120

OCC Detection Accuracy (mV)

Temperature (ƒC)

C010

VOCC, Setting = –100 mV

Figure 7-10. OCC Detection Accuracy Versus

Temperature

7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

8.6

±40 ±20 0 20 40 60 80 100 120

OCC Detection Delay Time (ms)

Temperature (ƒC)

C011

tOCCD, Setting = 8 ms

Figure 7-11. OCC Detection Delay Time Versus

Temperature

±4.0

±3.5

±3.0

±2.5

±2.0

±1.5

±1.0

±0.5

0.0

±40 ±20 0 20 40 60 80 100 120

OCD Detection Accuracy (mV)

Temperature (ƒC)

C012

VOCD, Setting = 100 mV

Figure 7-12. OCD Detection Accuracy Versus

Temperature

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18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

±40 ±20 0 20 40 60 80 100 120

OCD Detection Delay Time (ms)

Temperature (ƒC)

C013

tUVPD, Setting = 20 ms

Figure 7-13. OCD Detection Delay Time Versus

Temperature

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

±40 ±20 0 20 40 60 80 100 120

SCC Detection Accuracy (mV)

Temperature (ƒC)

C014

VSCC, Setting = 500 mV

Figure 7-14. SCC Detection Accuracy Versus

Temperature

1.10

1.12

1.14

1.16

1.18

1.20

1.22

1.24

±40 ±20 0 20 40 60 80 100 120

Power On Reset Threshold (V)

Temperature (ƒC)

C015

Figure 7-15. Power On Reset Versus Temperature

3.765

3.770

3.775

3.780

3.785

3.790

3.795

±40 ±20 0 20 40 60 80 100 120

VOH (V)

Temperature (ƒC)

C016

VBAT, Setting = 3.9 V

Figure 7-16. COUT Versus Temperature with Ioh =

–30 µA

3.7135

3.7140

3.7145

3.7150

3.7155

3.7160

±40 ±20 0 20 40 60 80 100 120

VOH (V)

Temperature (ƒC)

C017

VBAT, Setting = 3.9 V

Figure 7-17. DOUT Versus Temperature with Ioh = –30 µA

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8 Parameter Measurement Information

8.1 Timing Charts

BAT

DOUT

COUT

V–

OVP

VOVP–Hys

tOVPD

VUVP

BAT

VSS

BAT

VSS

PACK–

BAT

VSS

PACK–

OCD

Normal Overcharge Normal

Over-

Discharge Normal

tUVPD

Charger

Connected

Charger

Connected

Load

Connected

UVP–Hys

Figure 8-1. Overcharge Detection, Over-Discharge Detection

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*9 TEXAS INSTRUMENTS Norma‘ Dwscharge Overcurrent Norma‘ Dwscharge Overcurrent Norma‘ Disconneded

BAT

DOUT

COUT

V–

VOVP

OVP–Hys

tOCDD

UVP

BAT

VSS

BAT

VSS

PACK–

BAT

VSS

OCD

Normal Discharge Overcurrent Normal Normal

tSCCD

Load

Connected

VSCC

Load Short-

Circuit

Discharge Overcurrent

Load

Disconnected

VUVP+Hys

Figure 8-2. Discharge Overcurrent Detection

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8.2 Test Circuits

The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than

the threshold voltage of the external logic level FETs and regarded as ON state. “L” is less than the turn ON

threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the

DOUT pin is with respect to VSS.

1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):

The overcharge detection voltage (VOVP) is measured between the BAT and VSS pins, respectively. Once

V1 is increased, the over-detection is triggered, and the delay timer expires. Then, COUT transitions from a

high to low state and reduces the V1 voltage to check for the overcharge hysteresis parameter (VOVP-Hys).

The delta voltage between overcharge detection voltages (VOVP) and the overcharge release occurs when

the CHG FET drive output goes from low to high.

2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):

Over-discharge detection (VUVP) is defined as the voltage between BAT and VSS at which the DSG drive

output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is

set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the

DOUT drive output transition from low to high when V1 voltage is gradually increased from a VUVP condition.

The overcharge hysteresis voltage is defined as the delta voltage between VUVP and the instance at which

the DOUT output drive goes from low to high.

3. Discharge overcurrent detection voltage (Test Circuit 2):

The discharge overcurrent detection voltage (VOCD) is measured between V– and VSS pins and triggered

when the V2 voltage is increased above VOCD threshold with respect to VSS. This delta voltage once

satisfied will trigger an internal timer tOCDD before the DOUT output drive transitions from high to low.

4. Load short circuit detection voltage (Test Circuit 2):

Load short-circuit detection voltage (VSCC) is measured between V– and VSS pins and triggered when the

V2 voltage is increased above VSCC threshold with respect to VSS within 10 µs. This delta voltage, once

satisfied, triggers an internal timer tSCCD before the DOUT output drive transitions from high to low.

5. Charge overcurrent detection voltage (Test Circuit 2):

The charge overcurrent detection voltage (VOCC) is measured between VSS and V– pins and triggered when

the V2 voltage is increased above VOCC threshold with respect to V–. This delta voltage, once satisfied,

triggers an internal timer tOCCD before the COUT output drive transitions from high to low.

6. Operating current consumption (Test Circuit 2):

The operating current consumption IBNORMAL is the current measured going into the BAT pin under the

following conditions: V1 = 3.9 V and V2 = 0 V.

7. Power down current consumption (Test Circuit 2):

The operating current consumption IPower_down is the current measured going into the BAT pin under the

following conditions: V1 = 1.5 V and V2 = 1.5 V.

8. Resistance between V– and BAT pin (Test Circuit 3):

Measure the resistance (RV_D) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and

V2 = 0 V.

9. Current sink between V– and VSS (Test Circuit 3):

Measure the current sink IV–S between V– and VSS pins by setting the following condition: V1 = 4 V.

10. COUT current source when activated High (Test Circuit 4):

Measure ICOUT current source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and

V3 = 3.4 V.

11. COUT current sink when activated Low (Test Circuit 4):

Measure ICOUT current sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V, and V3 =

0.5 V.

12. DOUT current source when activated High (Test Circuit 4):

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Measure IDOUT current source on DOUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and V3

= 3.4 V.

13. DOUT current sink when activated Low (Test Circuit 4):

Measure IDOUT current sink on DOUT pin by setting the following conditions: V1 = 2.0 V, V2 = 0 V, and V3 =

0.4 V.

14. Overcharge detection delay (Test Circuit 5):

The overcharge detection delay time tOVPD is the time delay before the COUT drive output transitions from

high to low once the voltage on V1 exceeds the VOVP threshold. Set V2 = 0 V and then increase V1 until BAT

input exceeds the VOVP threshold, then check the time for when COUT goes from high to low.

15. Over-discharge detection delay (Test Circuit 5):

The over-discharge detection delay time tUVPD is the time delay before the DOUT drive output transitions

from high to low once the voltage on V1 decreases to VUVP threshold. Set V2 = 0 V and then decrease V1

until BAT input reduces to the VUVPthreshold, then check the time of when DOUT goes from high to low.

16. Discharge overcurrent detection delay (Test Circuit 5):

The discharge overcurrent detection delay time tOCDD is the time for DOUT drive output to transition from

high to low after the voltage on V2 is increased from 0 V to 0.35 V. V1 = 3.5 V and V2 starts from 0 V and

increases to trigger threshold.

17. Load short circuit detection delay (Test Circuit 5):

The load short-circuit detection delay time tSCCD is the time for DOUT drive output to transition from high

to low after the voltage on V2 is increased from 0 V to V1 – 1 V. V1 = 3.5 V and V2 starts from 0 V and

increases to trigger threshold.

18. Charge overcurrent detection delay (Test Circuit 5):

The charge overcurrent detection delay time tOCCD is the time for COUT drive output to transition from high

to low after the voltage on V2 is decreased from 0 V to –0.3 V. V1 = 3.5 V and V2 starts from 0 V and

decreases to trigger threshold.

19. 0-V battery charge starting charger voltage (Test Circuit 2):

The 0-V charge for start charging voltage V0CHA is defined as the voltage between BAT and V– pins at which

COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0 V.

20. 0-V battery charge inhibition battery voltage (Test Circuit 2):

The 0-V charge inhibit for charger voltage V0INH is defined as the voltage between BAT and VSS pins at

which COUT should go low as V1 is gradually decreased from V1 = 2 V and V2 = –4 V.

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8.3 Test Circuit Diagrams

COUT

DOUT

V-

BAT

VSS

220Ω

VDOUT

VCOUT

3 4

Figure 8-3. Test Circuit 1

COUT

DOUT

V-

BAT

VSS

VDOUT

VCOUT

3 4

IBAT

Figure 8-4. Test Circuit 2

COUT

DOUT

V-

BAT

VSS

3 4

IBAT

IV-

Figure 8-5. Test Circuit 3

COUT

DOUT

V-

BAT

VSS

IDOUT

ICOUT

3 4

Figure 8-6. Test Circuit 4

COUT

DOUT

V-

BAT

VSS

3 4

Oscilloscope

Figure 8-7. Test Circuit 5

9 Detailed Description

9.1 Overview

This BQ2970 device is a primary protector for a single-cell Li-ion/Li-polymer battery pack. The device uses a

minimum number of external components to protect for overcurrent conditions due to high discharge/charge

currents in the application. In addition, it monitors and helps to protect against battery pack overcharging or

depletion of energy in the pack. The BQ2970 device is capable of having an input voltage of 8 V from a charging

adapter and can tolerate a voltage of BAT – 25 V across the two input pins. In the condition when a fault is

triggered, there are timer delays before the appropriate action is taken to turn OFF either the CHG or DSG

FETs. The recovery period also has a timer delay once the threshold for recovery condition is satisfied. These

parameters are fixed once they are programmed. There is also a feature called zero voltage charging that

enables depleted cells to be charged to an acceptable level before the battery pack can be used for normal

operation. Zero voltage charging is allowed if the charger voltage is above 1.7 V. For Factory Programmable

Options, see Table 9-1.

Table 9-1. Factory Programmable Options

PARAMETER FACTORY DEVICE CONFIGURATION

VOVP Overcharge detection voltage 3.85 V to 4.60 V in 50-mV steps

VUVP Over-discharge detection voltage 2.00 V to 2.80 V in 50-mV steps

VOCD Discharging overcurrent detection voltage 90 mV to 200 mV in 5-mV steps

VOCC Charging overcurrent detection voltage –45 mV to –155 mV in 5-mV steps

VSCC Short Circuit detection voltage 300 mV, 400 mV, 500 mV, 600 mV

tOVPD Overcharge detection delay time 0.25 s, 1.00 s, 1.25 s, 4.50 s

tUVPD Over-discharge detection delay time 20 ms, 96 ms, 125 ms, 144 ms

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Table 9-1. Factory Programmable Options (continued)

PARAMETER FACTORY DEVICE CONFIGURATION

tOCDD Discharging overcurrent detection delay time 8 ms, 16 ms, 20 ms, 48 ms

tOCCD Charging overcurrent detection delay time 4 ms, 6 ms, 8 ms, 16 ms

tSCCD Short Circuit detection delay time 250 µs (fixed)

For available released devices, see the Released Device Configurations table.

9.2 Functional Block Diagram

Overcharge

Comparator (OVP)

with Hys

Over-Discharge

Comparator (UVP)

with Hys

Oscillator Counter

Over-Discharge

Current Comparator

Overcharge

Current

Comparator

Logic circuit

Delay

Logic circuit

Short Detect

BAT

VSS

DOUT

V–

5COUT

Charger

Detection

Circuit

BAT

IV–S

RV–D

9.3 Feature Description

The BQ2970 family of devices measures voltage drops across several input pins for monitoring and detection

of the following faults: OCC, OCD, OVP, and UVP. An internal oscillator initiates a timer to the fixed delays

associated with each parameter once the fault is triggered. Once the timer expires due to a fault condition, the

appropriate FET drive output (COUT or DOUT) is activated to turn OFF the external FET. The same method is

applicable for the recovery feature once the system fault is removed and the recovery parameter is satisfied,

then the recovery timer is initiated. If there are no reoccurrences of this fault during this period, the appropriate

gate drive is activated to turn ON the appropriate external FET.

9.4 Device Functional Modes

9.4.1 Normal Operation

This device monitors the voltage of the battery connected between BAT pin and VSS pin and the differential

voltage between V– pin and VSS pin to control charging and discharging. The system is operating in NORMAL

mode when the battery voltage range is between the over-discharge detection threshold (VUVP) and the

overcharge detection threshold (VOVP), and the V– pin voltage is within the range for charge overcurrent

threshold (VOCC) to over-discharge current threshold (VOCD) when measured with respect to VSS. If these

conditions are satisfied, the device turns ON the drive for COUT and DOUT FET control.

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CAUTION

When the battery is connected for the first time, the discharging circuit might not be enabled. In this

case, short the V– pin to the VSS pin.

Alternatively, connect the charger between the Pack+ and Pack– terminals in the system.

9.4.2 Overcharge Status

This mode is detected when the battery voltage measured is higher than the overcharge detection threshold

(VOVP) during charging. If this condition exists for a period greater than the overcharge detection delay (tOVPD) or

longer, the COUT output signal is driven low to turn OFF the charging FET to prevent any further charging of the

battery.

The overcharge condition is released if one of the following conditions occurs:

• If the V– pin is higher than the overcharge detection voltage (VOCC_Min), the device releases the overcharge

status when the battery voltage drops below the overcharge release voltage (VOVP-Hys).

• If the V– pin is higher than or equal to the over-discharge detection voltage (VOCD), the device releases the

overcharge status when the battery voltage drops below the overcharge detection voltage (VOVP).

The discharge is initiated by connecting a load after the overcharge detection. The V– pin rises to a voltage

greater than VSS due to the parasitic diode of the charge FET conducting to support the load. If the V– pin

voltage is higher than or equal to the discharge overcurrent detection threshold (VOCD), the overcurrent condition

status is released only if the battery voltage drops lower than or equal to the overcharge detection voltage

(VOVP).

CAUTION

1. If the battery is overcharged to a level greater than overcharge detection (VOVP) and the

battery voltage does not drop below the overcharge detection voltage (VOVP) with a heavy load

connected, the discharge overcurrent and load short-circuit detection features do not function

until the battery voltage drops below the overcharge detection voltage (VOVP). The internal

impedance of a battery is in the order of tens of mΩ, so application of a heavy load on the output

should allow the battery voltage to drop immediately, enabling discharge overcurrent detection

and load short-circuit detection features after an overcharge release delay.

2. When a charger is connected after an overcharge detection, the overcharge status does

not release even if the battery voltage drops below the overcharge release threshold. The

overcharge status is released when the V– pin voltage exceeds the overcurrent detection

voltage (VOCD) by removing the charger.

9.4.3 Over-Discharge Status

If the battery voltage drops below the over-discharge detection voltage (VUVP) for a time greater than (tUVPD)

the discharge control output, DOUT is switched to a low state and the discharge FET is turned OFF to prevent

further discharging of the battery. This is referred to as an over-discharge detection status. In this condition, the

V– pin is internally pulled up to BAT by the resistor RV–D. When this occurs, the voltage difference between

V– and BAT pins is 1.3 V or lower, and the current consumption of the device is reduced to power-down level

ISTANDBY. The current sink IV–S is not active in power-down state or over-discharge state. The power-down state

is released when a charger is connected and the voltage delta between V– and BAT pins is greater than 1.3 V.

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is lower than

–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the

discharge FET once the battery voltage exceeds over-discharge detection voltage (VUVP).

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is higher

than –0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn

ON the discharge FET once the battery voltage exceeds over-discharge detection release hysteresis voltage

(VUVP +Hys).

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9.4.4 Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)

When a battery is in normal operation and the V– pin is equal to or higher than the discharge overcurrent

threshold for a time greater than the discharge overcurrent detection delay, the DOUT pin is pulled low to turn

OFF the discharge FET and prevent further discharge of the battery. This is known as the discharge overcurrent

status. In the discharge overcurrent status, the V– and VSS pins are connected by a constant current sink IV–S.

When this occurs and a load is connected, the V– pin is at BAT potential. If the load is disconnected, the V– pin

goes to VSS (BAT/2) potential.

This device detects the status when the impedance between Pack+ and Pack– (see Figure 26) increases and

is equal to the impedance that enables the voltage at the V– pin to return to BAT – 1 V or lower. The discharge

overcurrent status is restored to the normal status.

Alternatively, by connecting the charger to the system, the device returns to normal status from discharge

overcurrent detection status, because the voltage at the V– pin drops to BAT – 1 V or lower.

The resistance RV–D between V– and BAT is not connected in the discharge overcurrent detection status.

9.4.5 Charge Overcurrent Status

When a battery is in normal operation status and the voltage at V– pin is lower than the charge overcurrent

detection due to high charge current for a time greater than charge overcurrent detection delay, the COUT pin

is pulled low to turn OFF the charge FET and prevent further charging to continue. This is known as charge

overcurrent status.

The device is restored to normal status from charge overcurrent status when the voltage at the V– pin returns to

charge overcurrent detection voltage or higher by removing the charger from the system.

The charge overcurrent detection feature does not work in the over-discharge status.

The resistance RV–D between V– and BAT and the current sink IV–S is not connected in the charge overcurrent

status.

9.4.6 0-V Charging Function Enabled

This feature enables recharging a connected battery that has very low voltage due to self-discharge. When the

charger applies a voltage greater than or equal to V0CHG to Pack+ and Pack– connections, the COUT pin gate

drive is fixed by the BAT pin voltage.

Once the voltage between the gate and the source of the charging FET becomes equal to or greater than the

turn ON voltage due to the charger voltage, the charging FET is ON and the battery is charged with current flow

through the charging FET and the internal parasitic diode of the discharging FET. Once the battery voltage is

equal to or higher than the over-discharge release voltage, the device enters normal status.

CAUTION

1. Some battery providers do not recommend charging a depleted (self-discharged) battery.

Consult the battery supplier to determine whether to have the 0-V battery charger function.

2. The 0-V battery charge feature has a higher priority than the charge overcurrent detection

function. In this case, the 0-V charging will be allowed and the battery charges forcibly, which

results in charge overcurrent detection being disabled if the battery voltage is lower than the

over-discharge detection voltage.

9.4.7 0-V Charging Inhibit Function

This feature inhibits recharging a battery that has an internal short circuit of a 0-V battery. If the battery voltage

is below the charge inhibit voltage V0INH or lower, the charge FET control gate is fixed to the Pack– voltage to

inhibit charging. When the battery is equal to V0INH or higher, charging can be performed. The 0-V charge inhibit

function is available in all configurations of the BQ297xx device.

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CAUTION

Some battery providers do not recommend charging a depleted (self-discharged) battery. Consult

the battery supplier to determine whether to enable or inhibit the 0-V battery charger function.

9.4.8 Delay Circuit

The detection delay timers are based from an internal clock with a frequency of 10 kHz.

Time

DOUT

V–

BAT

VSS

VSCC

OCD

0≤tD≤ tSCCD

tD˂tOCDD

Figure 9-1. Delay Circuit

If the over-discharge current is detected, but remains below the over-discharge short circuit detection threshold,

the over-discharge detection conditions must be valid for a time greater than or equal to over-discharge current

delay tOCCD time before the DOUT goes low to turn OFF the discharge FET. However, during any time the

discharge overcurrent detection exceeds the short circuit detection threshold for a time greater than or equal to

load circuit detection delay tSCCD, the DOUT pin goes low in a faster delay for protection.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The BQ2970 devices are a family of primary protectors used for protection of the battery pack in the application.

The application drives two low-side NMOS FETs that are controlled to provide energy to the system loads or

interrupt the power in the event of a fault condition.

10.2 Typical Application

DOUT

COUT

V–

BAT

VSS

PACK +

PACK–

CELLN

CELLP

S S

0.1 µF

2.2k

DSGCHG

330

The 5-M resistor for an external gate-source is optional.

Figure 10-1. Typical Application Schematic, BQ2970

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 10-1.

Table 10-1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE at TA = 25°C

Input voltage range 4.5 V to 7 V

Maximum operating discharge current 7 A

Maximum Charge Current for battery pack 4.5 A

Overvoltage Protection (OVP) 4.275 V

Overvoltage detection delay timer 1.2 s

Overvoltage Protection (OVP) release voltage 4.175 V

Undervoltage Protection (UVP) 2.8 V

Undervoltage detection delay timer 150 ms

Undervoltage Protection (UVP) release voltage 2.9 V

Charge Overcurrent detection (OCC) voltage –70 mV

Charge Overcurrent Detection (OCC) delay timer 9 ms

Discharge Overcurrent Detection (OCD) voltage 100 mV

Discharge Overcurrent Detection (OCD) delay timer 18 ms

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Table 10-1. Design Parameters (continued)

DESIGN PARAMETER EXAMPLE VALUE at TA = 25°C

Load Short Circuit Detection SCC) voltage, BAT to –V ≤ threshold 500 mV

Load Short Circuit Detection (SCC) delay timer 250 µs

Load Short Circuit release voltage, BAT to –V ≥ Threshold 1 V

10.2.2 Detailed Design Procedure

Note

The external FET selection is important to ensure the battery pack protection is sufficient and

complies to the requirements of the system.

• FET Selection: Because the maximum desired discharge current is 7 A, ensure that the Discharge

Overcurrent circuit does not trigger until the discharge current is above this value.

• The total resistance tolerated across the two external FETs (CHG + DSG) should be 100 mV/7 A = 14.3 mΩ.

• Based on the information of the total ON resistance of the two switches, determine what would be the Charge

Overcurrent Detection threshold, 14.3 mΩ × 4.5 A = 65 mV. Selecting a device with a 70-mV trigger threshold

for Charge Overcurrent trigger is acceptable.

• The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, de-rating due

to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the

FET choice should meet the following criteria:

Vdss = 25 V

Each FET Rds ON = 7.5 mΩ at Tj = 25°C and Vgs = 3.5 V

• Imax > 50 A to allow for short Circuit Current condition for 350 µs (max delay timer). The only limiting factor

during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).

• Use the CSD16406Q3 FET for the application.

• An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative

transients. The 330-Ω resistor also limits the current during a reverse connection on the system.

• TI recommends placing a high impedance 5-MΩ across the gate source of each external FET to deplete any

charge on the gate-source capacitance.

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10.2.3 Application Performance Plots

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output

DOUT goes from low to high when UVP Recovery = UVP Set

Threshold +100 mV

Figure 10-2. UVP Recovery

Orange Line (Channel 1) = Power Down Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Date Drive Output

DOUT goes from high to low when UVP threshold = UVP set

Threshold + set delay time

Figure 10-3. UVP Set Condition

Orange Line (Channel 1) = Power Up Ramp on BAT pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output

Figure 10-4. Initial Power Up, DOUT

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

Figure 10-5. Initial Power Up, COUT

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

COUT goes from high to low when OVP threshold = OVP set

Threshold + set delay time

Figure 10-6. OVP Set Condition

Orange Line (Channel 1) = Decrease Voltage on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

COUT goes from low to high when OVP Recovery = OVP Set

Threshold –100 mV

Figure 10-7. OVP Recovery Condition

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11 Power Supply Recommendations

The recommended power supply for this device is a maximum 8-V operation on the BAT input pin.

12 Layout

12.1 Layout Guidelines

The following are the recommended layout guidelines:

1. Ensure the external power FETs are adequately compensated for heat dissipation with sufficient thermal

heat spreader based on worst-case power delivery.

2. The connection between the two external power FETs should be very close to ensure there is not an

additional drop for fault sensing.

3. The input RC filter on the BAT pin should be close to the terminal of the IC.

12.2 Layout Example

COUT

DOUT

V–

BAT

VSS

4D5

CSD16406Q3 CSD16406Q3

Power Trace

Power Trace Line

PACK+

PACK–

Via connects between two layers

Power Trace Line

Figure 12-1. BQ2970 Board Layout

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13 Device and Documentation Support

13.1 Related Documentation

BQ29700 Single-Cell Li-Ion Protector EVM User's Guide (SLUUAZ3)

13.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.3 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

BQ29700DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FA

BQ29700DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FA

BQ29701DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FY

BQ29701DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FY

BQ29702DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FZ

BQ29702DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FZ

BQ29703DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F1

BQ29703DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F1

BQ29704DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F2

BQ29704DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F2

BQ29705DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F3

BQ29705DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F3

BQ29706DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F4

BQ29706DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F4

BQ29707DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F5

BQ29707DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 F5

BQ29716DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3P

BQ29716DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3P

BQ29717DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3Q

BQ29717DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3Q

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jun-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

BQ29718DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3R

BQ29718DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3R

BQ29723DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3S

BQ29723DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3S

BQ29728DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EJ

BQ29728DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EJ

BQ29729DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3T

BQ29729DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3T

BQ29732DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3U

BQ29732DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3U

BQ29733DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4Q

BQ29733DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4Q

BQ29737DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EI

BQ29737DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jun-2021

Addendum-Page 3

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS Reel Dlameter Cavtty AD Dimension destgned to accommodate the component wmth Eu Dimension destgned to accommodate the componenl tengtn K0 Dtmenston destgned to accommodate the component thickness 7 w Ovevau with at the earner tape i Pt Pttch between successtve cavtty cemers i T ReelWidIh(W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O O C) O O O ispmcketHutes —> User Dtrecllnn 0' Feed \1/ Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ29700DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29700DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29701DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29701DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29702DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29702DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29703DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29703DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29704DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29704DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29705DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29705DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29706DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29706DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29707DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29707DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29716DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29716DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jun-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ29717DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29717DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29718DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29718DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29723DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29723DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29728DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29728DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29729DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29729DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29732DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29732DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29733DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29733DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29737DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29737DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ29700DSER WSON DSE 6 3000 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jun-2021

Pack Materials-Page 2

l TEXAS INSTRUMENTS

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ29700DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29701DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29701DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29702DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29702DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29703DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29703DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29704DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29704DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29705DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29705DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29706DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29706DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29707DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29707DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29716DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29716DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29717DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29717DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29718DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29718DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29723DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29723DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29728DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29728DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29729DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29729DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29732DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29732DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29733DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29733DSET WSON DSE 6 250 182.0 182.0 20.0

BQ29737DSER WSON DSE 6 3000 182.0 182.0 20.0

BQ29737DSET WSON DSE 6 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jun-2021

Pack Materials-Page 3

MECHANICAL DATA DSE (S—PDSO—N6) PLASTIC SMALL OUTLINE / PW I INDEX AREA 7;; 0,20 ¥EF F I I 0,05 a (A o p N o SEATING FLARE 4207810/A 03/06 NOTES: AII Ihco' cImcns'ons are In mIIrrcIcrs SmuII om‘nc MiLeac (50M package conﬂquuiIon Ihs package IS IeuciIree A R ’m drowmg 's snbjecI In change Wan ranae c D {I} TEXAS INSrRUMEm-s www.1i.com

www.ti.com

PACKAGE OUTLINE

0.05

0.00

5X 0.6

0.4

(0.2) TYP

0.8 MAX

6X 0.3

0.2

0.7

0.5

2X 1

4X 0.5

B1.55

1.45 A

1.55

1.45

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

4220552/A 04/2021

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

0.1 C A B

0.05 C

PIN 1 ID

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

SCALE 6.000

www.ti.com

EXAMPLE BOARD LAYOUT

(0.8)

4X 0.5

(1.6)

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

6X (0.25)

(R0.05) TYP

5X (0.7)

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

4220552/A 04/2021

PKG

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

PADS 1-3

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

PADS 4-6

NON SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(0.8) 5X (0.7)

4X (0.5)

(1.6)

6X (0.25)

(R0.05) TYP

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:40X

PKG

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datenblatt für BQ297xx von Texas Instruments

INFORMATION

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