Datenblatt für OPA197, 2197, 4197 von Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA197

OPA2197

OPA4197

SBOS737C –JANUARY 2016–REVISED MARCH 2018

OPAx197 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage,

Operational Amplifiers

1 Features

1• Low Offset Voltage: ±100 µV (Maximum)

• Low Offset Voltage Drift: ±2.5 µV/°C (Maximum)

• Low Noise: 5.5 nV/√Hz at 1 kHz

• High Common-Mode Rejection: 120 dB

(Minimum)

• Low Bias Current: ±5 pA (Typical)

• Rail-to-Rail Input and Output

• Wide Bandwidth: 10-MHz GBW

• High Slew Rate: 20 V/µs

• Low Quiescent Current: 1 mA per Amplifier

(Typical)

• Wide Supply: ±2.25 V to ±18 V, +4.5 V to +36 V

• EMI- and RFI-Filtered Inputs

• Differential Input Voltage Range to Supply Rail

• High Capacitive Load Drive Capability: 1 nF

• Industry Standard Packages:

– Single in SOIC-8, SOT-5, and VSSOP-8

– Dual in SOIC-8 and VSSOP-8

– Quad in SOIC-14 and TSSOP-14

2 Applications

• Multiplexed Data-Acquisition Systems

• Test and Measurement Equipment

• High-Resolution ADC Driver Amplifiers

• SAR ADC Reference Buffers

• Programmable Logic Controllers

• High-Side and Low-Side Current Sensing

• High Precision Comparators

3 Description

The OPAx197 family (OPA197, OPA2197, and

OPA4197) is a new generation of 36-V operational

amplifiers.

These devices offer outstanding dc precision and ac

performance, including rail-to-rail input/output, low

offset (±25 µV, typical), low offset drift (±0.25 µV/°C,

typ), and 10-MHz bandwidth.

Unique features such as differential input-voltage

range to the supply rail, high output current (±65 mA),

high capacitive load drive of up to 1 nF, and high

slew rate (20 V/µs) make the OPA197 a robust, high-

performance operational amplifier for high-voltage,

industrial applications.

The OPA197 family of op amps is available in

standard packages and is specified from –40°C to

+125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

OPA197

SOIC (8) 4.90 mm × 3.90 mm

SOT (5) 2.90 mm × 1.60 mm

VSSOP (8) 3.00 mm × 3.00 mm

OPA2197 SOIC (8) 4.90 mm × 3.90 mm

VSSOP (8) 3.00 mm × 3.00 mm

OPA4197 SOIC (14) 8.65 mm x 3.90 mm

TSSOP (14) 5.00 mm x 4.40 mm

(1) For all available packages, see the package option addendum

at the end of the data sheet.

OPA197 in a High-Voltage, Multiplexed, Data-Acquisition System

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OPA2197

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Product Folder Links: OPA197 OPA2197 OPA4197

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information: OPA197 .................................. 6

6.5 Thermal Information: OPA2197 ................................ 6

6.6 Thermal Information: OPA4197 ................................ 6

6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8

V to 36 V)................................................................... 7

6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS=

4.5 V to 8 V)............................................................... 9

6.9 Typical Characteristics............................................ 11

7 Detailed Description............................................ 19

7.1 Overview ................................................................. 19

7.2 Functional Block Diagram....................................... 19

7.3 Feature Description................................................. 20

7.4 Device Functional Modes........................................ 26

8 Application and Implementation ........................ 27

8.1 Application Information............................................ 27

8.2 Typical Applications ................................................ 27

9 Power Supply Recommendations...................... 30

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 31

11 Device and Documentation Support ................. 32

11.1 Device Support...................................................... 32

11.2 Documentation Support ........................................ 32

11.3 Related Links ........................................................ 32

11.4 Receiving Notification of Documentation Updates 33

11.5 Community Resources.......................................... 33

11.6 Trademarks........................................................... 33

11.7 Electrostatic Discharge Caution............................ 33

11.8 Glossary................................................................ 33

12 Mechanical, Packaging, and Orderable

Information ........................................................... 33

4 Revision History

Changes from Revision B (October 2016) to Revision C Page

• Changed "Low Offset Voltage: ±250 µV (Maximum)" to "Low Offset Voltage: ±100 µV (Maximum)" ................................... 1

• Changed Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8 V to 36 V) Input offset voltage VS= ±18 V under

OFFSET VOLTAGE from "±250" to "±100"; remove "TA= 0°C to 85°C" and "TA= –40°C to +125°C" rows from same...... 7

• Changed Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8 V to 36 V) Input offset voltage VCM = (V+) – 1.5 V

under OFFSET VOLTAGE from "±250" to "±100"; remove "TA= 0°C to 85°C" and "TA= –40°C to +125°C" rows

from same............................................................................................................................................................................... 7

• Changed Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= 4.5 V to 8 V) Input offset voltage VS= ±2.25 V, VCM

= (V+) – 3 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA= 0°C to 85°C" and "TA= –40°C to

+125°C" rows from same........................................................................................................................................................ 9

• Changed Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8 V to 36 V) Input offset voltage VS= ±3 V, VCM =

(V+) – 1.5 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA= 0°C to 85°C" and "TA= –40°C to

+125°C" rows from same........................................................................................................................................................ 9

• Changed "0" on Frequency (Hz) axis to "0.1" ..................................................................................................................... 11

• Changed "....to achieve a very low offset voltage of 250 µV (max)..." to "...to achieve a very low offset voltage of 100

µV (maximum)..." ................................................................................................................................................................. 19

Changes from Revision A (July 2016) to Revision B Page

• Added new row for PW package to Input bias current parameter ......................................................................................... 7

• Added new row for PW package to Input offset current parameter ...................................................................................... 7

• Added new footnote (1) to Open-loop gain parameter........................................................................................................... 7

• Changed Slew rate parameter from 20 V/µs : to 14 V/µs .................................................................................................... 10

Changes from Original (January 2016) to Revision A Page

• Added OPA2197 and OPA4197 CDM values to ESD Ratings table...................................................................................... 5

{L} TEXAS INSTRUMENTS j j j j j j j M E7? CECE KKKKKKK 11:: j j % EEC OEEEE

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OPA197

OPA2197

OPA4197

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SBOS737C –JANUARY 2016–REVISED MARCH 2018

Product Folder Links: OPA197 OPA2197 OPA4197

5 Pin Configuration and Functions

D and DGK Packages: OPA197

8-Pin SOIC and VSSOP

Top View

D and DGK Packages: OPA2197

8-Pin SOIC and VSSOP

Top View

DBV Package: OPA197

5-Pin SOT

Top View

D and PW Packages: OPA4197

14-Pin SOIC and TSSOP

Top View

l TEXAS INSTRUMENTS

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OPA2197

OPA4197

SBOS737C –JANUARY 2016–REVISED MARCH 2018

www.ti.com

Product Folder Links: OPA197 OPA2197 OPA4197

Pin Functions: OPA197

I/O DESCRIPTION

NAME

OPA197

D (SOIC),

DGK (VSSOP) DBV (SOT)

+IN 3 3 I Noninverting input

–IN 2 4 I Inverting input

NC 1, 5, 8 — — No internal connection (can be left floating)

OUT 6 1 O Output

V+ 7 5 — Positive (highest) power supply

V– 4 2 — Negative (lowest) power supply

Pin Functions: OPA2197 and OPA4197

I/O DESCRIPTION

NAME

OPA2197 OPA4197

D (SOIC),

DGK (VSSOP) D (SOIC),

PW (TSSOP)

+IN A 3 3 I Noninverting input, channel A

+IN B 5 5 I Noninverting input, channel B

+IN C — 10 I Noninverting input, channel C

+IN D — 12 I Noninverting input, channel D

–IN A 2 2 I Inverting input, channel A

–IN B 6 6 I Inverting input, channel B

–IN C — 9 I Inverting input,,channel C

–IN D — 13 I Inverting input, channel D

OUT A 1 1 O Output, channel A

OUT B 7 7 O Output, channel B

OUT C — 8 O Output, channel C

OUT D — 14 O Output, channel D

V+ 8 4 — Positive (highest) power supply

V– 4 11 — Negative (lowest) power supply

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage, VS= (V+) – (V–) Dual supply ±20 V

Single supply 40

Signal input pins Voltage Common-mode (V–) – 0.5 (V+) + 0.5 V

Differential (V+) – (V–) + 0.2

Current ±10 mA

Output short circuit(2) Continuous

Temperature

Operating, TA–55 150

°CJunction, TJ150

Storage, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

ALL DEVICES

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

OPA197

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V

OPA2197

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 V

OPA4197

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage, VS= (V+) – (V–) Dual supply ±2.25 ±18 V

Single supply 4.5 36

Operating temperature, TA–40 125 °C

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OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information: OPA197

THERMAL METRIC(1)

OPA197

UNITD (SOIC) DBV (SOT) DGK (VSSOP)

8 PINS 5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 115.8 158.8 180.4 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 60.1 60.7 67.9 °C/W

RθJB Junction-to-board thermal resistance 56.4 44.8 102.1 °C/W

ψJT Junction-to-top characterization parameter 12.8 1.6 10.4 °C/W

ψJB Junction-to-board characterization parameter 55.9 4.2 100.3 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Thermal Information: OPA2197

THERMAL METRIC(1)

OPA2197

UNITD (SOIC) DGK (VSSOP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 107.9 158 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 53.9 48.6 °C/W

RθJB Junction-to-board thermal resistance 48.9 78.7 °C/W

ψJT Junction-to-top characterization parameter 6.6 3.9 °C/W

ψJB Junction-to-board characterization parameter 48.3 77.3 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Thermal Information: OPA4197

THERMAL METRIC(1)

OPA4197

UNITD (SOIC) PW (TSSOP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 86.4 92.6 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 46.3 27.5 °C/W

RθJB Junction-to-board thermal resistance 41.0 33.6 °C/W

ψJT Junction-to-top characterization parameter 11.3 1.9 °C/W

ψJB Junction-to-board characterization parameter 40.7 33.1 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W

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OPA4197

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SBOS737C –JANUARY 2016–REVISED MARCH 2018

Product Folder Links: OPA197 OPA2197 OPA4197

(1) For OPA2197, OPA4197: When driving high current loads on multiple channels, make sure the junction temperature does not exceed

125°C.

6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8 V to 36 V)

at TA= 25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

VOS Input offset voltage VS= ±18 V ±25 ±100 µV

VCM = (V+) – 1.5 V ±10 ±100

dVOS/dT Input offset voltage drift VS= ±18 V, VCM = (V+) – 3 V TA= –40°C to +125°C ±0.5 ±2.5 µV/°C

VS= ±18 V, VCM = (V+) – 1.5 V ±0.8 ±4.5

PSRR Power-supply rejection

ratio TA= –40°C to +125°C ±1 ±3 µV/V

INPUT BIAS CURRENT

IBInput bias current

±5 ±20 pA

TA= –40°C to +125°C ±5 nA

PW package only ±15

IOS Input offset current

±2 ±20 pA

TA= –40°C to +125°C ±2 nA

PW package only ±10

NOISE

EnInput voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.30 µVPP

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4

enInput voltage noise

density

(V–) – 0.1 V < VCM < (V+) – 3 V f = 100 Hz 10.5

nV/√Hz

f = 1 kHz 5.5

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 100 Hz 32

f = 1 kHz 12.5

inInput current noise

density f = 1 kHz 1.5 fA/√Hz

INPUT VOLTAGE

VCM Common-mode voltage

range (V–) – 0.1 (V+) + 0.1 V

CMRR Common-mode

rejection ratio

VS= ±18 V,

(V–) – 0.1 V < VCM < (V+) – 3 V

120 140

TA= –40°C to +125°C 110 126

VS= ±18 V,

(V+) – 1.5 V < VCM < (V+)

100 120

TA= –40°C to +125°C 80 100

VS= ±18 V,

(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics

INPUT IMPEDANCE

ZID Differential 100 || 1.6 MΩ|| pF

ZIC Common-mode 1 || 6.4 1013Ω|| pF

OPEN-LOOP GAIN

AOL Open-loop voltage

gain(1)

VS= ±18 V,

(V–) + 0.6 V < VO< (V+) – 0.6 V,

RLOAD = 2 kΩ

120 134

TA= –40°C to +125°C 110 126

VS= ±18 V,

(V–) + 0.3 V < VO< (V+) – 0.3 V,

RLOAD = 10 kΩ

120 143

TA= –40°C to +125°C 110 134

l TEXAS INSTRUMENTS

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OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

Electrical Characteristics: VS= ±4 V to ±18 V (VS= 8 V to 36 V) (continued)

at TA= 25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) For a detailed description of thermal protection, see the Thermal Protection section.

FREQUENCY RESPONSE

GBW Unity gain bandwidth 10 MHz

SR Slew rate VS= ± 18 V, G = 1, 10-V step 20 V/µs

tsSettling time

To 0.01% VS= ±18 V, G = 1, 10-V step 1.4

µs

VS= ±18 V, G = 1, 5-V step 0.9

To 0.001% VS= ±18 V, G = 1, 10-V step 2.1

VS= ±18 V, G = 1, 5-V step 1.8

tOR Overload recovery time VIN × G = VS200 ns

THD+N Total harmonic

distortion + noise G = 1, f = 1 kHz, VO= 3.5 VRMS 0.00008%

OUTPUT

VOVoltage output swing

from rail

Positive rail

No load 5 25

RLOAD = 10 kΩ95 125

RLOAD = 2 kΩ430 500

Negative rail

No load 5 25

RLOAD = 10 kΩ95 125

RLOAD = 2 kΩ430 500

ISC Short-circuit current VS= ±18 V ±65 mA

CLOAD Capacitive load drive See Typical Characteristics

ZOOpen-loop output

impedance f = 1 MHz, IO= 0 A, See Figure 26 375 Ω

POWER SUPPLY

IQQuiescent current per

amplifier

IO= 0 A 1 1.3 mA

TA= –40°C to +125°C, IO= 0 A 1.5

TEMPERATURE

Thermal protection(2) 140 °C

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6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= 4.5 V to 8 V)

at TA= 25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

VOS Input offset voltage

VS= ±2.25 V, VCM = (V+) – 3 V ±5 ±100 µV

(V+) – 3.5 V < VCM < (V+) – 1.5 V See Common-Mode Voltage Range section

VS= ±3 V, VCM = (V+) – 1.5 V ±10 ±100 µV

dVOS/dT Input offset voltage drift VS= ±2.25 V, VCM = (V+) – 3 V TA= –40°C to +125°C ±0.5 ±2.5 µV/°C

VS= ±2.25 V, VCM = (V+) – 1.5 V ±0.8 ±4.5

PSRR Power-supply rejection

ratio TA= –40°C to +125°C, VCM = VS/ 2 – 0.75 V ±2 µV/V

INPUT BIAS CURRENT

IBInput bias current ±5 ±20 pA

TA= –40°C to +125°C ±5 nA

IOS Input offset current ±2 ±20 pA

TA= –40°C to +125°C ±2 nA

NOISE

EnInput voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz 1.30 µVPP

(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz 4

enInput voltage noise

density

(V–) – 0.1 V < VCM < (V+) – 3 V f = 100 Hz 10.5

nV/√Hz

f = 1 kHz 5.5

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 100 Hz 32

f = 1 kHz 12.5

inInput current noise

density f = 1 kHz 1.5 fA/√Hz

INPUT VOLTAGE

VCM Common-mode voltage

range (V–) – 0.1 (V+) + 0.1 V

CMRR Common-mode

rejection ratio

VS= ±2.25 V,

(V–) – 0.1 V < VCM < (V+) – 3 V

90 110

TA= –40°C to +125°C 88 104

VS= ±2.25 V,

(V+) – 1.5 V < VCM < (V+)

94 120

TA= –40°C to +125°C 77 100

VS= ±2.25 V,

(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics

INPUT IMPEDANCE

ZID Differential 100 || 1.6 MΩ|| pF

ZIC Common-mode 1 || 6.4 1013Ω|| pF

OPEN-LOOP GAIN

AOL Open-loop voltage gain

VS= ±2.25 V,

(V–) + 0.6 V < VO< (V+) – 0.6 V,

RLOAD = 2 kΩ

104 126

TA= –40°C to +125°C 100 114

VS= ±2.25 V,

(V–) + 0.3 V < VO< (V+) – 0.3 V,

RLOAD = 10 kΩ

104 134

TA= –40°C to +125°C 100 120

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OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= 4.5 V to 8 V) (continued)

at TA= 25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) For a detailed description of thermal protection, see the Thermal Protection section.

FREQUENCY RESPONSE

GBW Unity gain bandwidth 10 MHz

SR Slew rate G = 1, 1-V step 14 V/µs

tsSettling time To 0.01% VS= ±3 V, G = 1, 5-V step 1 µs

tOR Overload recovery time VIN× G = VS200 ns

OUTPUT

VOVoltage output swing

from rail

Positive rail

No load 5 25

RLOAD = 10 kΩ95 125

RLOAD = 2 kΩ430 500

Negative rail

No load 5 25

RLOAD = 10 kΩ95 125

RLOAD = 2 kΩ430 500

ISC Short-circuit current VS= ±2.25 V ±65 mA

CLOAD Capacitive load drive See Typical Characteristics

ZOOpen-loop output

impedance f = 1 MHz, IO= 0 A, see Figure 26 375 Ω

POWER SUPPLY

IQQuiescent current per

amplifier IO= 0 A 1 1.3 mA

TA= –40°C to +125°C 1.5

TEMPERATURE

Thermal protection(1) 140 °C

l TEXAS INSTRUMENTS

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6.9 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION FIGURE

Offset Voltage Production Distribution Figure 1,Figure 2,Figure 3

Offset Voltage Drift Distribution Figure 4

Offset Voltage vs Temperature Figure 5

Offset Voltage vs Common-Mode Voltage Figure 6,Figure 7,Figure 8

Offset Voltage vs Power Supply Figure 9

Open-Loop Gain and Phase vs Frequency Figure 10

Closed-Loop Gain and Phase vs Frequency Figure 11

Input Bias Current vs Common-Mode Voltage Figure 12

Input Bias Current vs Temperature Figure 13

Output Voltage Swing vs Output Current (maximum supply) Figure 14,Figure 15

CMRR and PSRR vs Frequency Figure 16

CMRR vs Temperature Figure 17

PSRR vs Temperature Figure 18

0.1-Hz to 10-Hz Noise Figure 19

Input Voltage Noise Spectral Density vs Frequency Figure 20

THD+N Ratio vs Frequency Figure 21

THD+N vs Output Amplitude Figure 22

Quiescent Current vs Supply Voltage Figure 23

Quiescent Current vs Temperature Figure 24

Open Loop Gain vs Temperature Figure 25

Open Loop Output Impedance vs Frequency Figure 26

Small Signal Overshoot vs Capacitive Load (100-mV output step) Figure 27,Figure 28

No Phase Reversal Figure 29

Positive Overload Recovery Figure 30

Negative Overload Recovery Figure 31

Small-Signal Step Response (100 mV) Figure 32,Figure 33

Large-Signal Step Response Figure 34

Settling Time Figure 35,Figure 36, ,

Short-Circuit Current vs Temperature Figure 37

Maximum Output Voltage vs Frequency Figure 38

Propagation Delay Rising Edge Figure 39

Propagation Delay Falling Edge Figure 40

l TEXAS INSTRUMENTS 500 35 100 ESWWWWWWWWWWWWWWW ‘5\\\\\\\\\\\\\\\\\\\\\\\

±150

±100

±50

100

150

±75 ±50 ±25 0 25 50 75 100 125 150

Input Offset Voltage (V)

Temperature (ƒC)

C001

Common-Mode Voltage (V)

Input Offset Voltage (PV)

-20 -15 -10 -5 0 5 10 15 20

-75

-50

-25

Input Offset Voltage (PV)

Amplifiers (%)

-200 -150 -100 -50 0 50 100 150 200

Input Offset Voltage Drift (PV/qC)

Amplifiers (%)

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2

Input Offset Voltage (PV)

Number of Amplifiers

100

200

300

400

500

-100 -80 -60 -40 -20 0 20 40 60 80 100

Input Offset Voltage (PV)

Amplifiers (%)

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

4770 production units

Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Production Distribution at 125°C

Figure 3. Offset Voltage Production Distribution at –40°C Figure 4. Offset Voltage Drift Distribution

from –40°C to +125°C

9 typical units

Figure 5. Offset Voltage vs Temperature

6 typical units

Figure 6. Offset Voltage vs Common-Mode Voltage

l TEXAS INSTRUMENTS 100 200 mo mu zau en 50M cm

Frequency (Hz)

Closed Loop Gain (db)

-20

1k 10k 100k 1M 10M 50M

G = 100 V/V

G = +1 V/V

G = 10 V/V

G = -1 V/V

±1000

±800

±600

±400

±200

200

400

600

800

1000

±20.0 ±15.0 ±10.0 ±5.0 0.0 5.0 10.0 15.0 20.0

Input Bias Current (pA)

VCM (V)

C001

Frequency (Hz)

Open Loop Gain (db)

Phase (q)

-20 -40

0 0

20 40

40 80

60 120

80 160

100 200

120 240

140 280

1 10 100 1k 10k 100k 1M 10M 100M

Open Loop Gain

Phase

Power-Supply Voltage (V)

Input Offset Voltage (PV)

0 2 4 6 8 10 12 14 16 18 20

-100

-75

-50

-25

100

Common-Mode Voltage (V)

Input Offset Voltage (PV)

13 14 15 16 17 18 19

-100

-75

-50

-25

100

Common-Mode Voltage (V)

Input Offset Voltage (PV)

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

-200

-150

-100

-50

100

150

200

OPA197

OPA2197

OPA4197

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at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

6 typical units

Figure 7. Offset Voltage vs Common-Mode Voltage

6 typical units

Figure 8. Offset Voltage vs Common-Mode Voltage

6 typical units

Figure 9. Offset Voltage vs Power Supply

CLOAD = 15 pF

Figure 10. Open-Loop Gain and Phase vs Frequency

Figure 11. Closed-Loop Gain and Phase vs Frequency Figure 12. Input Bias Current vs Common-Mode Voltage

l TEXAS INSTRUMENTS 3000

±10

±8

±6

±4

±2

±75 ±50 ±25 0 25 50 75 100 125 150

Common-Mode Rejection Ratio (µV/V)

Temperature (ƒC)

C001

VS = ±18 V

VS = ±2.25 V

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

±75 ±50 ±25 0 25 50 75 100 125 150

Power-Supply Rejection Ratio (µV/V)

Temperature (ƒC)

C001

(V+) - 5

(V+) - 4

(V+) - 3

(V+) - 2

(V+) - 1

(V+)

(V+) + 1

0 10 20 30 40 50 60 70 80

Output Voltage (V)

Output Current (mA)

C001

-40°C

+85°C

+125°C

25°C

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

1 10 100 1k 10k 100k 1M

Common-Mode Rejection Ratio (dB),

Power-Supply Rejection Ratio (dB)

Frequency (Hz)

+PSRR

CMRR

-PSRR

C012

(V-) - 1

(V-)

(V-) + 1

(V-) + 2

(V-) + 3

(V-) + 4

(V-) + 5

0 10 20 30 40 50 60 70 80

Output Voltage (V)

Output Current (mA)

C001

-40°C

+125°C

25°C

+85°C

Temperature (qC)

Input Bias Current (pA)

-75 -50 -25 0 25 50 75 100 125

-1000

1000

2000

3000 IB-

IB+

IOS

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

Figure 13. Input Bias Current vs Temperature Figure 14. Output Voltage Swing from Negative Power

Supply vs Output Current (Maximum Supply)

Figure 15. Output Voltage Swing from Positive Power

Supply vs Output Current (Maximum Supply) Figure 16. CMRR and PSRR vs Frequency

Figure 17. CMRR vs Temperature Figure 18. PSRR vs Temperature

l TEXAS INSTRUMENTS VRms 12 12

Supply Voltage (V)

Quiescent Current (mA)

0 4 8 12 16 20 24 28 32 36

0.8

0.9

1.1

1.2

Temperature (qC)

Quiescent Current (mA)

-50 -25 0 25 50 75 100 125

0.8

0.9

1.1

1.2 VS = r2.25 V

VS = r18 V

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

1E-5

0.0001

0.001

0.01

0.1

10 100 1k 10k 100k

G = 1 V/V, RL = 10 k:

G = 1 V/V, RL = 2 k:

G = 1 V/V, RL = 2 k:

G = 1 V/V, RL = 10 k:

Output Amplitude (VRMS)

Total Harmonic Distortion + Noise (%)

0.01 0.1 1 10 2020

1E-5

0.0001

0.001

0.01

0.1

1G = 1 V/V, RL = 10 k:

G = 1 V/V, RL = 2 k:

G = 1 V/V, RL = 2 k:

G = 1 V/V, RL = 10 k:

Time (1 s/div)

400 nV/div

Frequency (Hz)

Voltage Noise Density (nV/—Hz)

100

200

300

500

1000

100m 1 10 100 1k 10k 100k

VCM = 0 V (P-Channel)

VCM = V+ - 100 mV (N-Channel)

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at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

Peak-to-peak noise = VRMS × 6.6 = 1.30 VPP

Figure 19. 0.1-Hz to 10-Hz Noise Figure 20. Input Voltage Noise Spectral Density

vs Frequency

VOUT = 3.5 VRMS, BW = 80 kHz

Figure 21. THD+N Ratio vs Frequency

f = 1 kHz, BW = 80 kHz

Figure 22. THD+N vs Output Amplitude

Figure 23. Quiescent Current vs Supply Voltage Figure 24. Quiescent Current vs Temperature

l TEXAS INSTRUMENTS Frequency (Hz)

Time (200 Ps/div)

Voltage (5 V/div)

Output

Input

Time (200 ns/div)

Voltage (5 V/div)

Output

Input

Capacitive Load (pF)

Overshoot (%)

20 30 40 50 70 100 200 300 500 700 1000 2000

45 RISO = 0 :

RISO = 25 :

RISO = 50 :

Capacitive Load (pF)

Overshoot (%)

20 30 40 50 70 100 200 300 500 700 1000 2000

50 RISO = 0 :

RISO = 25 :

RISO = 50 :

Temperature (qC)

AOL (PV/V)

-50 -25 0 25 50 75 100 125

-3

-2

-1

3VS = r2.25 V

VS = r18 V

100

10k

0.1 1 10 100 1k 10k 100k 1M 10M

Output Impedance (Ω)

Frequency (Hz) C016

OPA197

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at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

Figure 25. Open-Loop Gain vs Temperature Figure 26. Open-Loop Output Impedance vs Frequency

G = –1 V/V

Figure 27. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step)

G = 1 V/V

Figure 28. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step)

VS= ±18 V, input = ±18.5 VPP

Figure 29. No Phase Reversal

G = –10 V/V

Figure 30. Positive Overload Recovery

‘5‘ TEXAS INSTRUMENTS

Time (Ps)

Output Voltage Delta from Final Value (mV)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

-4

-3

-2

-1

Time (Ps)

Output Voltage Delta from Final Value (mV)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

-4

-3

-2

-1

Time (150 ns/Div)

Output (50 mV/Div)

Time (300 ns/Div)

Output (2.5 V/Div)

Time (200 ns/div)

Voltage (5 V/div)

Output

Input

Time (200 ns/Div)

Output (50 mV/Div)

OPA197

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at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

G = –10 V/V

Figure 31. Negative Overload Recovery

G = 1 V/V

Figure 32. Small-Signal Step Response

G = –1 V/V

Figure 33. Small-Signal Step Response

G = 1 V/V

Figure 34. Large-Signal Step Response

G = 1, 0.01% settling = ±1 mV, step applied at t = 0

Figure 35. Settling Time (10-V Positive Step)

G = 1, 0.01% settling = ±500 µV, step applied at t = 0

Figure 36. Settling Time (5-V Positive Step)

l TEXAS INSTRUMENTS mu '/ //

Output Voltage (5 V/div)

Time (200 ns/div)

C025

VOUT Voltage

Overdrive = 100 mV

tpLH = 0.97 s

Output Voltage (1 V/div)

Time (200 ns/div)

C026

VOUT Voltage

Overdrive = 100 mV

tpLH = 1.1 s

10k 100k 1M 10M

Output Voltage (VPP)

Frequency (Hz)

C033

VS = ±2.25 V

VS = ±5 V

VS = ±15 V

Maximum output voltage without

slew-rate induced distortion.

Temperature (qC)

Short-Circuit Current (mA)

-75 -50 -25 0 25 50 75 100 125 150

100 Sinking current

Sourcing current

OPA197

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OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

at TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF (unless otherwise noted)

Figure 37. Short-Circuit Current vs Temperature Figure 38. Maximum Output Voltage vs Frequency

Figure 39. Propagation Delay Rising Edge Figure 40. Propagation Delay Falling Edge

l TEXAS INSTRUMENTS





36-V

Differential

Front End

Slew

Boost

High

Capacitive Load

Compensation

+IN

-IN

OUT

OPAx197





NCH Input

Stage

PCH Input

Stage

Output

Stage

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

7 Detailed Description

7.1 Overview

The OPAx197 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 250 µV

(max) and low voltage offset drift of 0.75 µV/°C (maximum) over the full specified temperature range. This level

of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial

sensors, filters, and high-voltage data acquisition.

7.2 Functional Block Diagram

‘5‘ TEXAS INSTRUMENTS |||||||||||| 100

Time (Ps)

Output Delta from Final Value (mV)

0 6 12 18 24 30 36 42 48 54 60

-100

-50

100

0.1% settling = r10 mV

Op amp with standard input diodes

OPA197

Input Low Pass Filter

Ron_mux

Sn+1

Simplified Mux Model

RFILT

CFILT

Vn = +10 V

Vn+1 = ±10 V

+10 V

±10 V

Buffer Amplifier

Idiode_transient

+10 V ~±9.3 V

Vin+

Vin±

~0.7 V Vout

±10 V

Ron_mux

OPAx197

36 V ~0.7 V

OUT

V+

VConventional Input Protection

Limits Differential Input Range

OPAx197 Provides Full 36-V

Differential Input Range

+IN

-IN

OUT

V+

V

+IN

-IN

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

7.3 Feature Description

7.3.1 Input Protection Circuitry

The OPAx197 uses a unique input architecture to eliminate the need for input protection diodes, but still provides

robust input protection under transient conditions. Conventional input diode protection schemes shown in

Figure 41 can be activated by fast transient step responses and can introduce signal distortion and settling time

delays because of alternate current paths, as shown in Figure 42. For low-gain circuits, these fast-ramping input

signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling

time, as shown in Figure 43.

Figure 41. OPA197 Input Protection Does Not Limit Differential Input Capability

Figure 42. Back-to-Back Diodes Create Settling Issues

Figure 43. OPA197 Protection Circuit Maintains Fast-Settling Transient Response

l TEXAS INSTRUMENTS me

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

10M 100M 1G 10G

EMIRR IN+ (dB)

Frequency (Hz)

C017

PRF = -10 dBm

VSUPPLY = ±18 V

VCM = 0 V

OPA197

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Feature Description (continued)

The OPAx197 family of operational amplifiers provides a true high-impedance differential input capability for high-

voltage applications. This patented input protection architecture does not introduce additional signal distortion or

delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.

The OPA197 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the

op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping

input signals such as multiplexed data-acquisition systems, as shown in Figure 53.

7.3.2 EMI Rejection

The OPAx197 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the OPAx197 benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.

Figure 44 shows the results of this testing on the OPA197. Table 2 shows the EMIRR IN+ values for the OPA197

at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be

centered on or operated near the particular frequency shown. Detailed information can also be found in the

application report EMI Rejection Ratio of Operational Amplifiers,SBOA128, available for download from

www.ti.com.

Figure 44. EMIRR Testing

Table 2. OPA197 EMIRR IN+ For Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+

400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications 44.1 dB

900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 52.8 dB

1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB

2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 69.5 dB

3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB

5.0 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz) 105.5 dB

VOUT

140ºC

3 V

0 V

Temperature

Normal

Operation

Output

High-Z

150°C

+30 V

100 Ÿ





VIN

3 V

IOUT = 30 mA

OPAx197

TA = 65°C

PD = 0.81W

JA = 116°C/W

TJ = 116°C/W × 0.81W + 65°C

TJ = 159°C (expected)

Time (200 Ps/div)

Voltage (5 V/div)

Output

Input

OPA197

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Product Folder Links: OPA197 OPA2197 OPA4197

7.3.3 Phase Reversal Protection

The OPAx197 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The OPAx197 is a rail-to-rail input op amp; therefore, the common-mode range can

extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into

the appropriate rail. This performance is shown in Figure 45.

Figure 45. No Phase Reversal

7.3.4 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This

phenomenon is called self heating. The absolute maximum junction temperature of the OPAx197 is 150°C.

Exceeding this temperature causes damage to the device. The OPAx197 has a thermal protection feature that

prevents damage from self heating. The protection works by monitoring the temperature of the device and

turning off the op amp output drive for temperatures above 140°C. Figure 46 shows an application example for

the OPA197 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal

calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.

The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 46 depicts

how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the

output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal

protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.

Figure 46. Thermal Protection

7.3.5 Capacitive Load and Stability

The OPAx197 features a patented output stage capable of driving large capacitive loads, and in a unity-gain

configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the

amplifier to drive greater capacitive loads; see Figure 47 and Figure 48. The particular op amp circuit

configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an

amplifier will be stable in operation.

l TEXAS INSTRUMENTS 11 PreCIsion

Cload

Vin

Vout

+Vs

Riso

-Vs

Capacitive Load (pF)

Overshoot (%)

20 30 40 50 70 100 200 300 500 700 1000 2000

45 RISO = 0 :

RISO = 25 :

RISO = 50 :

Capacitive Load (pF)

Overshoot (%)

20 30 40 50 70 100 200 300 500 700 1000 2000

50 RISO = 0 :

RISO = 25 :

RISO = 50 :

OPA197

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Figure 47. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step, G = –1 V/V) Figure 48. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step, G = 1 V/V)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small

(10-Ωto 20-Ω) resistor, RISO, in series with the output, as shown in Figure 49. This resistor significantly reduces

ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in

parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly

reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at

low output levels. A high capacitive load drive makes the OPA197 well suited for applications such as reference

buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 49 uses an isolation resistor,

RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase

margin, and results using the OPA197 are summarized in Table 3. For additional information on techniques to

optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,

and test results.

Figure 49. Extending Capacitive Load Drive with the OPA197

Table 3. OPA197 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and

Measured Results

PARAMETER VALUE

Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF

Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60°

RISO (Ω)47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7

Measured

Overshoot (%) 23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6

Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2°

For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,

simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using

an Isolation Resistor .

l TEXAS INSTRUMENTS V PCHZ ’1’ J New NEH)“ {E 3%”

±15.0 ±14.0 «11.0 12.0 13.0 14.0 15.0

Common-Mode Voltage (V)

Input Offset Voltage (V)

200

100

±100

±200

±300

Input Offset Voltage vs Vcm

without a precision trimmed Input

Transition

Region

P-Channel

Region N-Channel

Region

±15.0 ±14.0 «11.0 12.0 13.0 14.0 15.0

Common-Mode Voltage (V)

Input Offset Voltage (V)

200

100

±100

±200

±300

Transition

Region

P-Channel

Region N-Channel

Region

OPAx197

Input Offset Voltage vs Vcm

NCH3

PCH2

PCH1

IS1

NCH4

V±

V+

+IN

±IN

FUSE BANK

TRIM TRIM

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7.3.6 Common-Mode Voltage Range

The OPAx197 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that

extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel

and P-channel differential input pairs, as shown in Figure 50. The N-channel pair is active for input voltages

close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active

for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition

region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary

modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD

performance may be degraded compared to operation outside this region.

Figure 50. Rail-to-Rail Input Stage

To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when

possible. The OPAx197 uses a precision trim for both the N-channel and P-channel regions. This technique

enables significantly lower levels of offset than previous-generation devices, causing variance in the transition

region of the input stages to appear exaggerated relative to offset over the full common-mode voltage range, as

shown in Figure 51.

Figure 51. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers

Power-Supply

ESD Cell

100 Ÿ

VSS

VDD

IN±

IN+

TVS

VIN

+VS

±VS

OPAx197

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

7.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the

output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. See Figure 52 for an illustration of the ESD circuits contained in the OPAx197 (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or

the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

Figure 52. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event

is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled

ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

7.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a

linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the

rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

The overload recovery time for the OPAx197 is approximately 200 ns.

7.4 Device Functional Modes

The OPAx197 has a single functional mode and is operational when the power-supply voltage is greater than

4.5 V (±2.25 V). The maximum power supply voltage for the OPAx197 is 36 V (±18 V).

SAR

ADC

REFP

VINP

VINM

4:2

Mux

+Antialiasing

Filter

Gain

Network

Gain

Network

Gain

Network

High-Voltage Level Translation

VCM

High-Voltage Multiplexed Input

Reference Driver

2 4

Voltage

Reference RC Filter Buffer RC Filter

16 Bits

400 kSPS

Delay

Digital Counter For Multiplexer

CONV

Very Low Output Impedance

Input-Filter Bandwidth

High-Impedance Inputs

No Differential Input Clamps

Fast Settling-Time Requirements

Attenuate High-Voltage Input Signal

Fast-Settling Time Requirements

Stability of the Input Driver

Attenuate ADC Kickback Noise

VREF Output: Value and Accuracy

Low Temp and Long-Term Drift

Fast logic transition

±20-V,

10-kHz

Sine Wave

±20-V,

10-kHz

Sine Wave

Shmidtt

Trigger

Counter

REF3240 Voltage

Divider

OPA350

VCM Generation Circuit

CH0+

CH0-

CH3+

CH3-

OPA197

OPA140

OPA197

OPA197 Gain

Network

OPA197

OPA2197

OPA4197

www.ti.com

SBOS737C –JANUARY 2016–REVISED MARCH 2018

Product Folder Links: OPA197 OPA2197 OPA4197

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The OPAx197 family offers outstanding dc precision and ac performance. These devices operate up to 36-V

supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as

10-MHz bandwidth and high capacitive load drive. These features make the OPAx197 a robust, high-

performance operational amplifier for high-voltage industrial applications.

8.2 Typical Applications

8.2.1 16-Bit Precision Multiplexed Data-Acquisition System

Figure 53 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in

industrial applications that require low distortion and a high-voltage differential input. The circuit uses the

ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along

with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This

application example explains the process for optimizing the precision, high-voltage, front-end drive circuit using

the OPA197 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.

Figure 53. OPA197 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage

Inputs With Lowest Distortion

l TEXAS INSTRUMENTS ADC Dwﬂererma‘ \npm (vy 11 Prec‘l’sion

Integral Nonlinearity Error (LSB)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ADC Differential Input (V)

–20 –15 –10 –5 0 5 10 15 20

OPA197

OPA2197

OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

Typical Applications (continued)

8.2.1.1 Design Requirements

The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest

distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.

The design requirements for this block design are:

• System Supply Voltage: ±15 V

• ADC Supply Voltage: 3.3 V

• ADC Sampling Rate: 400 kSPS

• ADC Reference Voltage (REFP): 4.096 V

• System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency

(fIN) of 10 kHz are applied to each differential input of the mux.

8.2.1.2 Detailed Design Procedure

The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for

highest system linearity and fast settling. The overall system block diagram is shown in Figure 53. The circuit is a

multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output

buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast

sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design

considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input

analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each

analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit

resolution and lowest distortion system. The diagram includes the most important specifications for each

individual analog block.

This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input

stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design

is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding

helps in the decision of an appropriate input filter and selection of a mux to meet the system settling

requirements. The next important step is the design of the attenuating analog front end (AFE) used to level

translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability. The

next step is to design a digital interface to switch the mux input channels with minimum delay. The final design

challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage

with low offset, drift, and noise contributions.

8.2.1.3 Application Curve

Figure 54. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition

System for High Voltage Inputs with Lowest Distortion.

‘5‘ TEXAS INSTRUMENTS “Prec‘l’sion

VCC

VEE

1.6 0Ÿ

VOUT

V+

VIN

10 NŸ

1.69 NŸ

470 nF

Op Amp Gain Stage Slew Rate Limiter

OPA197

VCC

VEE

V+

OPA197

OPA2197

OPA4197

www.ti.com

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Product Folder Links: OPA197 OPA2197 OPA4197

8.2.2 Slew Rate Limit for Input Protection

In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.

By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down

at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one

additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high

output current and slew rate of the OPAx197 make the device an optimal amplifier to achieve slew rate control

for both dual- and single-supply systems.Figure 55 shows the OPA197 in a slew-rate limit design.

Figure 55. Slew Rate Limiter Uses One Op Amp

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.

l TEXAS INSTRUMENTS “HM WH%A

1 NŸ

10 µF

RISO

37.4 Ÿ

VREF

2.5 V

RFx

10 NŸ

39 nF

V+

OPA197 VOUT

VCC

OPA197

OPA2197

OPA4197

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8.2.3 Precision Reference Buffer

The OPAx197 features high output current drive capability and low input offset voltage, making the device an

excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the

10-µF ceramic capacitor shown in Figure 56, RISO, a 37.4-Ωisolation resistor, provides separation of two

feedback paths for optimal stability. Feedback path number one is through RFand is directly at the output, VOUT.

Feedback path number two is through RFx and CFand is connected at the output of the op amp. The optimized

stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz, while still

providing a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability

components: RF, RFx, CF, and RISO.

Figure 56. Precision Reference Buffer

9 Power Supply Recommendations

The OPAx197 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from

–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see the

Absolute Maximum Ratings.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout

section.

l TEXAS INSTRUMENTS RG

±IN

+IN

V±

V+

OUT

VS+

GND

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Use low-ESR, ceramic

bypass capacitor

Place components

close to device and

to each other to

reduce parasitic

errors

VIN VOUT

(Schematic Representation)

Use low-ESR,

ceramic bypass

capacitor

OPA197

OPA2197

OPA4197

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10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds paying attention to the flow of the ground current. For more detailed

information refer to Circuit Board Layout Techniques,SLOA089.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much

better as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 57, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

• Cleaning the PCB following board assembly is recommended for best performance.

• Any precision integrated circuit may experience performance shifts due to moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is

recommended to remove moisture introduced into the device packaging during the cleaning process. A

low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.2 Layout Example

Figure 57. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE

These files require that either the TINA software (from DesignSoft™) or TINA-TI software

be installed. Download the free TINA-TI software from the TINA-TI folder.

11.1.1.2 TI Precision Designs

The OPA197 is featured in several TI Precision Designs, available online at the TI Precision Designs website. TI

Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory

of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and

measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•Circuit Board Layout Techniques (SLOA089)

•Op Amps for Everyone (SLOD006)

11.3 Related Links

Table 4 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 4. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

OPA197 Click here Click here Click here Click here Click here

OPA2197 Click here Click here Click here Click here Click here

OPA4197 Click here Click here Click here Click here Click here

l TEXAS INSTRUMENTS

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OPA4197

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Product Folder Links: OPA197 OPA2197 OPA4197

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.6 Trademarks

E2E is a trademark of Texas Instruments.

TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

TINA, DesignSoft are trademarks of DesignSoft, Inc.

All other trademarks are the property of their respective owners.

11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

OPA197ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197

OPA197IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV

OPA197IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV

OPA197IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST

OPA197IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST

OPA197IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197

OPA2197ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2197

OPA2197IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV

OPA2197IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV

OPA2197IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2197

OPA4197ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197

OPA4197IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197

OPA4197IPW ACTIVE TSSOP PW 14 90 RoHS & Green SN Level-3-260C-168 HR -40 to 125 OPA4197

OPA4197IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 OPA4197

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA197, OPA2197 :

•Automotive: OPA197-Q1, OPA2197-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS 5:. V.’

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

OPA197IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA197IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA197IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA197IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA197IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA2197IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2197IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2197IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA4197IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

OPA4197IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA197IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0

OPA197IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0

OPA197IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0

OPA197IDGKT VSSOP DGK 8 250 223.0 270.0 35.0

OPA197IDR SOIC D 8 2500 356.0 356.0 35.0

OPA2197IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0

OPA2197IDGKT VSSOP DGK 8 250 223.0 270.0 35.0

OPA2197IDR SOIC D 8 2500 356.0 356.0 35.0

OPA4197IDR SOIC D 14 2500 356.0 356.0 35.0

OPA4197IPWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

OPA197ID D SOIC 8 75 506.6 8 3940 4.32

OPA2197ID D SOIC 8 75 506.6 8 3940 4.32

OPA4197ID D SOIC 14 50 506.6 8 3940 4.32

OPA4197IPW PW TSSOP 14 90 508 8.5 3250 2.8

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/F 06/2021

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam AB, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddiﬁ§n%="" 5.40="" 5,40="" @eeeeeej="" rﬁhﬂ§eﬂhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com

MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end ﬂair \Meﬁead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud ﬂasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com

LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Deﬁned Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH oﬂer eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com

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