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December, 2017 − Rev. 7

1Publication Order Number:

NCP1602/D

NCP1602

Enhanced, High-Efficiency

Power Factor Controller

The 6−pin PFC controller NCP1602 is designed to drive PFC boost

stages. It is based on an innovative Valley Synchronized Frequency

Fold−back (VSFF) method. In this mode, the circuit classically

operates in Critical conduction Mode (CrM) when Vcontrol voltage

exceeds a programmable value Vctrl,FF. When Vcontrol is below this

preset level Vctrl,FF, the NCP1602 (versions [B**] and [D**]) linearly

decays the frequency down to about 30 kHz until Vcontrol reaches the

SKIP mode threshold. VSFF maximizes the efficiency at both

nominal and light load. In particular, the stand−by losses are reduced

to a minimum. Like in FCCrM controllers, internal circuitry allows

near−unity power factor even when the switching frequency is

reduced. Housed in a TSOP6 package, the circuit also incorporates the

features necessary for robust and compact PFC stages, with few

external components.

General Features

•Near−Unity Power Factor

•Critical Conduction Mode (CrM)

•Valley Synchronized Frequency Fold−back (VSFF): Low Frequency

Operation is Forced at Low Current Levels

•Works With or Without a Transformer w/ ZCD Winding (simple inductor)

•On−time Modulation to Maintain a Proper Current Shaping in VSFF Mode

•Skip Mode at Very Low Load Current (versions[ B**] and [D**])

•Fast Line / Load Transient Compensation (Dynamic Response Enhancer)

•Valley Turn−on

•High Drive Capability: −500 mA / +800 mA

•VCC Range: from 9.5 V to 30 V

•Low Start−up Consumption for:

[**C] & [**D] Versions: Low Vcc Start−up level (10.5 V)

[**A] & [**B] Versions: High Vcc Start−up level (17.0 V)

•Line Range Detection for Reduced Crossover Frequency Spread

•This is a Pb−Free Device

Safety Features

•Thermal Shutdown

•Non−latching, Over−Voltage Protection

•Second Over−Voltage Protection

•Brown−Out Detection

•Soft−Start for Smooth Start−up Operation ([**C] &

[**D] Versions)

•Over Current Limitation

•Disable Protection if the Feedback Pin is Not Connected

•Low Duty−Cycle Operation if the Bypass Diode is

Shorted

•Open Ground Pin Fault Monitoring

Typical Applications

•PC Power Supplies

•Lighting Ballasts (LED, Fluorescent)

•Flat TV

•All Off Line Appliances Requiring Power Factor

Correction

PIN CONNECTIONS

3DRV

VCTRL

CS / ZCD 4

(Top View)

5VCC

TSOP−6

SN SUFFIX

CASE 318G

MARKING DIAGRAM

GND

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(Note: Microdot may be in either location)

XXX AYWG

XXX = Specific Device Code

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

See detailed ordering, marking and shipping information in the

package dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

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DEVICE ORDERING INFORMATION

Operating Part Number (OPN) L1, L2, L3 Option Marking Package Type Shipping

NCP1602ABASNT1G ABA ABA

TSOP−6

(Pb−Free) 3000 / Tape & Reel

NCP1602ACCSNT1G ACC A6C

NCP1602AEASNT1G AEA AEA

NCP1602AFCSNT1G AFC AFC

NCP1602BEASNT1G BEA 2EA

NCP1602DCCSNT1G DCC DCC

NCP1602DFCSNT1G DFC DFC

NOTE: Other L1, L2, L3 combinations are available upon request.

Product versions are coded with three letters (L1,L2,L3).

Table 1. NCP1602 1st LETTER CODING OF PRODUCT VERSIONS

L1Brown−out Function Skip Mode Function

A NO NO

BNO YES (trim)

CYES (trim) NO

DYES (trim) YES (trim)

Table 2. NCP1602 2nd LETTER CODING OF PRODUCT VERSIONS

L2CrM to DCM VCTRL Threshold (V) tON,max,LL (ms) tON,max,HL(ms)

B 1.026 25 8.33

C 1.296 25 8.33

E1.553 12.5 4.17

F 2.079 12.5 4.17

Table 3. NCP1602 3rd LETTER CODING OF PRODUCT VERSIONS

L3VCC Startup Level (V)

A 17.0

C 10.5

T T IL L1 KT N VI N VI EZ -—4va www.cnsemi.com

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EMI

Filter

AC line

LOAD

L1 D1

Vin Vbulk

Rsense

Cbulk

RzCp

Rcs1

Rcs2

Cin

Rfb2

Rfb1

VCTRL

CS / ZCD

GND

DRV

VCC

Rcszcd

Figure 1. NCP1602 Application Schematic

Table 4. DETAILED PIN DESCRIPTION

Pin Number Name Function

1 VCTRL The error amplifier output is available on this pin. The network connected between this pin

and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve

high Power Factor ratios.

VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the

power increases slowly to provide a soft−start function.

VCTRL pin must not be controlled or pulled down externally.

2 GND Connect this pin to the PFC stage ground.

3CS / ZCD This pin monitors the MOSFET current to limit its maximum current.

This pin is the output of a resistor bridge connected between the drain and the source of the

power MOSFET. Internal circuitry takes care of extracting Vin , Vout, Iind and ZCD

4 DRV The high−current capability of the totem pole gate drive (−0.5/+0.8A) makes it suitable to

effectively drive high gate charge power MOSFETs.

5 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds

17.0 V ([**A] Versions) or 10.5 V ([**C] Versions) and turns off when VCC goes below 9.0 V

(typical values). After start−up, the operating range is 9.5 V up to 30 V.

6 FB This pin receives a portion of the PFC output voltage for the regulation and the Dynamic

Response Enhancer (DRE) that drastically speeds−up the loop response when the output

voltage drops below 95.5% of the desired output level.

FB pin voltage VFB is also the input signal for the (non−latching) Over−Voltage (OVP) and

Under−Voltage (UVP) comparators. The UVP comparator prevents operation as long as FB

pin voltage is lower than VUVPH internal voltage reference. A SOFTOVP comparator gradual-

ly reduces the duty−ratio when FB pin voltage exceeds 105% of VREF. If the output voltage

still increases, the driver is immediately disabled if the output voltage exceeds 107% of the

desired level (fast OVP).

A 250 nA sink current is built−in to trigger the UVP protection and disable the part if the feed-

back pin is accidentally open.

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Table 5. MAXIMUM RATINGS TABLE

Symbol Pin Rating Value Unit

VCTRL 1 VCONTROL pin −0.3, Vctrl,max(*) V

CS/ZCD 3 CS/ZCD Pin −0.3, +9 V

DRV 4 Driver Voltage

Driver Current

−0.3, VDRV (*)

−500, +800

VCC 5 Power Supply Input −0.3, + 30 V

VCC 5 Maximum (dV/dt) that can be applied to VCC TBD upon test engineer

measurements

V/s

FB 6 Feedback Pin −0.3, +9 V

RqJA

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation @ TA = 70°C

Thermal Resistance Junction to Air

550

145

°C/W

TJOperating Junction Temperature Range −40 to+125 °C

TJ,max Maximum Junction Temperature 150 °C

TS,max Storage Temperature Range −65 to 150 °C

TL,max Lead Temperature (Soldering, 10 s) 300 °C

MSL Moisture Sensitivity Level 1−

ESD Capability, HBM model (Note 1) > 2000 V

ESD Capability, Charged Device Model (Note 1) > 1500 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

*“Vctrl,max” is the VCTRL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC otherwise.

1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Charged Device Model Method 1500 V per JEDEC Standard JESD22−C101E.

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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Table 6. TYPICAL ELECTRICAL CHARACTERISTICS

(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol Rating Min Typ Max Unit

START−UP AND SUPPLY CIRCUIT

VCC,on Start−Up Threshold, VCC increasing:

[**C] Versions

[**A] Versions

9.75

15.80

10.50

17.00

11.25

18.20

VCC,off Minimum Operating Voltage, VCC falling 8.50 9.00 9.50 V

VCC,hyst Hysteresis (VCC ,on − VCC ,off)

[**C] Versions

[**A] Versions

0.75

6.00

1.50

8.00

−

ICC,start Maximum Start−Up Current, for VCC lower than 9.4 V, below startup voltage − − 480 mA

ICC,op1 Operating Consumption, no switching. −0.5 1.00 mA

ICC,op2 Operating Consumption, 50 kHz switching, no load on DRV pin −2.00 3.00 mA

FREQUENCY FOLD−BACK DEAD TIME FOR CONFIGURATIONS L2 = B, C, E, F @ Km = 2.28

tDT,B,1 Dead−Time, Vctrl = 0.65V w/ B config 5.73 7.64 9.55 ms

tDT,B,2 Dead−Time, Vctrl = 0.75V w/ B config 2.91 3.88 4.85 ms

tDT,C,1 Dead−Time, Vctrl = 0.65V w/ C config 8.90 11.90 14.84 ms

tDT,C,2 Dead−Time, Vctrl = 0.75V w/ C config 5.69 7.50 9.48 ms

tDT,E,1 Dead−Time, Vctrl = 0.65V w/ E config 9.96 13.28 16.60 ms

tDT,E,2 Dead−Time, Vctrl = 0.75V w/ E config 6.70 8.93 10.80 ms

tDT,F,1 Dead−Time, Vctrl = 0.65V w/ F config 13.00 17.30 21.66 ms

tDT,F,2 Dead−Time, Vctrl = 0.75V w/ F config 9.97 13.10 16.61 ms

CrM TO DCM THRESHOLD AND HYSTERESIS

Vctrl,th,B Vctrl threshold CrM to DCM mode w/ B config 0.923 1.026 1.129 V

Vctrl,th,C Vctrl threshold CrM to DCM mode w/ C config 1.16 1.29 1.43 V

Vctrl,th,E Vctrl threshold CrM to DCM mode w/ E config 1.398 1.553 1.708 V

Vctrl,th,F Vctrl threshold CrM to DCM mode w/ F config 1.865 2.08 2.29 V

SKIP CONTROL ([B**] & [D**] Versions)

VSKIP−HVctrl pin SKIP Level, Vcontrol rising 555 617 678 mV

VSKIP−LVctrl pin SKIP Level, Vcontrol falling 516 593 665 mV

VSKIP−Hyst Vctrl pin SKIP Hysteresis −30 −mV

GATE DRIVE

tROutput voltage rise−time @ CL = 1 nF, 10−90% of output signal −30 −ns

tFOutput voltage fall−time @ CL = 1 nF, 10−90% of output signal −20 −ns

ROH Source resistance @ 200 mV under High VCC −10 −Ω

ROL Sink resistance @200 mV above Low VCC −7−Ω

VDRV,low DRV pin level for VCC = VCC ,off +200 mV (10 kΩ resistor between DRV and GND) 8.0 − − V

VDRV,high DRV pin level at VCC = 30 V (RL = 33 kΩ & CL = 1 nF) 10 12 14 V

REGULATION BLOCK

VREF Feedback Voltage Reference 2.44 2.50 2.56 V

IEA Error Amplifier Current Capability, Sinking and Sourcing 15 20 26 mA

GEA Error Amplifier Gain 110 200 290 mS

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit

characterization has been performed.

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Table 6. TYPICAL ELECTRICAL CHARACTERISTICS

(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol UnitMaxTypMinRating

REGULATION BLOCK

Vctrl

Vctrl,min

Vctrl,max

VCTRL pin Voltage (Vctrl):

− @ VFB = 2 V (OTA is sourcing 20 mA)

− @ VFB = 3 V (OTA is sinking 20 mA)

−

4.5

0.5

−

Vout,L / VREF2 Ratio (Vout Low Detect Threshold / VREF ) (guaranteed by design) −95.5 −%

Hout,L / VREF2 Ratio (VoutLow Detect Hysteresis / VREF) (guaranteed by design) −0.35 −%

IBOOST VCTRL pin Source Current when (VOUT Low Detect) is activated 147 220 277 mA

CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS

VCS(th) Current Sense Voltage Reference 450 500 550 mV

VCS,OVS(th) Current Sense Overstress Voltage Reference 675 750 825 mV

tLEB,OVS “Overstress” Leading edge Blanking Time (guaranteed by design) −250 −ns

tLEB,OCP “Over−Current Protection” Leading edge Blanking Time (guaranteed by design) −400 −ns

tOCP Over−Current Protection Delay from VCS/ZCD >VCS(th) to

DRV low (dVCS/ZCD / dt = 10 V/ms)

−40 200 ns

VZCD(th)H Zero Current Detection, VCS/ZCD rising 8 35 62 mV

VZCD(th)L Zero Current Detection, VCS/ZCD falling −68 −46 −25 mV

VZCD(hyst) Hysteresis of the Zero Current Detection Comparator 46 84 −mV

To discuss versus what esd protection will be used

VCL(pos) CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA (guaranteed by design) −9.5 −V

tZCD (VCS/ZCD < VZCD (th )L) to (DRV high) −60 200 ns

tSYNC Minimum ZCD Pulse Width −110 200 ns

tWDG Watch Dog Timer 80 200 320 ms

tWDG(OS) Watch Dog Timer in “OverStress” Situation 400 800 1200 ms

IZCD(gnd) Source Current for CS/ZCD pin impedance Testing −50 −mA

IZCD(Vcc) Pull−up current source referenced to Vcc for open pin detection −200 −nA

STATIC OVP

DMIN Duty Cycle, VFB = 3 V ( When low clamp of Vctrl is reached) −−0 %

ON−TIME CONTROL (Options [*E*], [*B*], [*F*], [*C*] for maximum tON value)

ton,LL,B Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 22 25 28 ms

ton,HL,B Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 7.49 8.33 9.16 ms

ton,LL,C Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 22 25 28 ms

ton,HL,C Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 7.49 8.40 9.16 ms

ton,LL,E Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 11.4 12.5 13.6 ms

ton,HL,E Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 3.75 4.17 4.59 ms

ton,LL,F Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 11.4 12.5 13.6 ms

ton,HL,F Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 3.75 4.20 4.59 ms

Kton,LL−HL tON @LL over tON @HL ratio (all tON versions) −3−w/o

Specifying max tON,min means tON,min can go down to zero

ton,LL,min Minimum On Time, avg(Vcs ) = 0.9 V

(not tested, guaranteed by design)

−300 −ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit

characterization has been performed.

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Table 6. TYPICAL ELECTRICAL CHARACTERISTICS

(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol UnitMaxTypMinRating

ON−TIME CONTROL (Options [*E*], [*B*], [*F*], [*C*] for maximum tON value)

ton,HL,min Minimum On Time, avg(Vcs ) = 2.8 V

(not tested, guaranteed by design)

−200 −ns

FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP and UVP)

RsoftOVP Ratio (Soft OVP Threshold, VFB rising) over VREF (or VREF2)

(guaranteed by design)

−105 −%

RsoftOVP(HYST) Ratio (Soft OVP Hysteresis) over VREF (or VREF2) (guaranteed by design) −1.87 −%

RfastOVP Ratio (Fast OVP Threshold, VFB rising) over VREF (or VREF2)

(guaranteed by design)

−107 −%

RfastOVP(HYST) Ratio (Fast OVP Hysteresis) over VREF (or VREF2) (guaranteed by design) −4.0 −%

VUVPH UVP Threshold, VFB increasing 555 612 670 mV

VUVPL UVP Threshold, VFB decreasing 252 303 357 mV

VUVP(HYST) UVP Hysteresis 273 307 342 mV

IB,FB FB pin Bias Current @ VFB = VOV P and VFB = VUVP 50 200 450 nA

BROWN−OUT PROTECTION AND FEED−FORWARD (Vsns is an internal pin that replaces Vsense)

VBOH Brown−Out Threshold Vmains increasing, VFB based

([C**] and [D**] versions)

754 819 894 mV

VBOL Brown−Out Threshold, Vmains decreasing, avg(VCS) based

([C**] and [D**] versions)

659 737 801 mV

VBO(HYST) Brown−Out Comparator Hysteresis ([C**] and [D**] versions) 75 100 −mV

tBO(blank) Brown−Out Blanking Time ([C**] and [D**] versions) 36 50 67 ms

IVCTRL(BO) VCTRL pin sink current during BO condition 20 30 42 mA

VHL Comparator Threshold for Line Range Detection, avg(VCS ) rising 1.718 1.801 1.882 V

VLL Comparator Threshold for Line Range Detection, avg(VCS ) falling 1.310 1.392 1.474 V

VHL(hyst) Comparator Hysteresis for Line Range Detection 75 400 −mV

tHL(blank) Blanking Time for Line Range Detection 13 25 43 ms

THERMAL SHUTDOWN

TLIMIT Thermal Shutdown Threshold 150 − − °C

HTEMP Thermal Shutdown Hysteresis −50 −°C

SECOND OVERVOLTAGE PROTECTION (OVP2)

VOVP2H,HL OVP2 Threshold, VCS rising, KCS = 138, @ VREF2 = 2.5 V 3.048 3.175 3.302 V

VOVP2L,HL OVP2 Threshold, VCS falling, KCS = 138, @ VREF2 = 2.5 V 2.969 3.093 3.217 V

VOVP2(HYST),HL OVP2 Comparator Hysteresis, KCS = 138, @ VREF2 = 2.5 V 50 100 −mV

tLEB,OVP2 OVP2 Leading Edge Blanking Time, VCS rising (guaranteed by design) −1000 −ns

tRST(OVP2) Reset Timer for OVP2 latch 400 800 1200 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit

characterization has been performed.

VCTRL I] ‘ W EH7 H H HHH HM J J -J EU W SLZETW CS/ZCD % VCC I] % \ T HH A t LLNE l wNaK l Y Y ’J I? DRV www.cnsemi.com

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Figure 2. NCP1602 Block Diagram

PFCOK

OVLFLAG1

OFF

BONOK

STOP

STATICOVP

OVERSTRESS

OCP

FASTOVP

SECOND

OVP

OVP2

ZCD

VREF,VCC

VREF

VREF,XXXX

VDD

THERMAL

SHUTDOWN

TSD

UVP

BONOK

OFF

STATICOVP

OFF

VREF FB

Transconductance

Error Amplifier

OVLFLAG1

UVLO

OVP2

VCC

Output

Buffer

CLK

SKIPDEL

CLK & DT

MANAGMENT

CLK

SKIP

Internal

Timing

Ramp

DRV

LLINE

tON

Processing

Circuitry

VCC

ZCD

VSNS

DRV

DEMAG

LINE SENSE

FAULT

MANAGMENT

DRV

CURRENT

SENSE

OVERSTRESS

OCP

VREF,OVS

VREF,OCP

VCTRL

MANAGMENT

VREGUL

STATICOVP

OFF

BONOK FB

MANAGMENT VREF,DRE

VREF,FAST_OVP

VREF,SOFT_OVP

VREF,UVP

OVP2

PFCOK

FASTOVP

SOFTOVP

UVP

DRE

VREF,LLINE

VREF,BONOK

LINE & BO

MANAGMENT

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TYPICAL CHARACTERISTICS

Figure 3. Start−Up Threshold, VCC Increasing

(VCC,on) vs. Junction Temperature

(versions [**C]&[**D])

Figure 4. Start−Up Threshold, VCC Increasing

(VCC,on) vs. Junction Temperature

(versions [**A]&[**B])

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

120806040200−40−60

9.75

9.95

10.15

10.35

10.55

10.75

10.95

11.15

15.8

16.3

16.8

17.3

17.8

Figure 5. Minimum Operating Voltage, VCC

Falling (VCC,off) vs. Junction Temperature

Figure 6. Hysteresis (VCC,on – VCC,off) vs.

Junction Temperature (versions [**C]&[**D])

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

8.5

8.6

8.8

8.9

9.0

9.2

9.3

9.5

0.75

1.25

1.75

2.25

2.75

Figure 7. Hysteresis (VCC,on – VCC,off) vs.

Junction Temperature (versions [**A]&[**B])

TJ, JUNCTION TEMPERATURE (°C)

VCC(on) (V)

VCC(off) (V)

VCC(hyst) (V)

−20 100 140 120806040200−40−60 −20 100 140

120806040200−40−60 −20 100 140120806040200−40−60 −20 100 140

120806040200−40−60 −20 100 140

8.7

9.1

9.4

Figure 8. Dead−Time, Vctrl = 0.65 V w/

E Config (tDT,E,1) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

9.96

10.96

11.96

12.96

13.96

14.96

15.96

tDT,E,1 (ms)

120806040200−40−60 −20 100 140

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TYPICAL CHARACTERISTICS

Figure 9. Dead−Time, Vctrl = 0.75 V w/

E Config (tDT,E,2) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

6.7

7.2

7.7

8.2

8.7

9.7

10.2

10.7

tDT,E,2 (ms)

120806040200−40−60 −20 100 140

9.2

Figure 10. Vctrl Threshold CrM to DCM Mode

w/ E Config (Vctrl,th,E) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

1.398

1.448

1.498

1.548

1.598

1.648

1.698

Vctrl,th,E (V)

120806040200−40−60 −20 100 140

Figure 11. Vcrtl Pin SKIP Level, Vctrl Rising

(VSKIP−H) vs. Junction Temperature

Figure 12. Vcrtl pin SKIP Level, Vctrl Falling

(VSKIP−L) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.555

0.575

0.595

0.615

0.635

0.655

0.675

0.516

0.536

0.556

0.576

0.596

0.616

0.636

0.656

Figure 13. DRV Pin Level for VCC = VCC,off +

200 mV (10−kW Resistor between DRV and

GND) (VDRV,low) vs. Junction Temperature

Figure 14. DRV Pin Level @ VCC = 30 V (RL =

33 kW & CL = 1 nF) (VDRV,high) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

8.0

8.5

9.0

9.5

10.0

11.0

11.5

12.0

10.0

10.5

11.0

11.5

12.0

13.0

13.5

14.0

VSKIP−H (V)

VSKIP−L (V)

VDRV,low (V)

VDRV,high (V)

120806040200−40−60 −20 100 140120806040200−40−60 −20 100 140

120806040200−40−60 −20 100 140 120806040200−40−60 −20 100 140

10.5 12.5

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TYPICAL CHARACTERISTICS

Figure 15. Feedback Voltage Reference (VREF)

vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

120806040200−40−60

2.44

2.46

2.48

2.50

2.52

2.54

2.56

Figure 16. Error Amplifier Current Capability,

Sourcing (IEA1) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

15.6

16.6

17.6

18.6

20.6

21.6

22.6

23.6

Figure 17. Error Amplifier Current Capability,

Sinking (IEA2) vs. Junction Temperature

Figure 18. Error Amplifier Transconductance

(GEA) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

−24

−23

−22

−21

−19

−18

−17

−16

110

130

150

190

210

250

270

290

VREF (Vbg Post) (V)

IEA1 (mA)

IEA2 (mA)

GEA (mS)

−20 100 140 120806040200−40−60 −20 100 140

120806040200−40−60 −20 100 140 120806040200−40−60 −20 100 140

19.6

−20

170

230

Figure 19. Watch Dog Timer Duration (tWDG)

vs. Junction Temperature

Figure 20. Watch Dog Timer Duration in

“OverStress” Situation (tWDG(OS)) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

130

180

230

280

400

500

600

700

900

1000

1100

1200

tWDG (ms)

tWDG(os) (ms)

120806040200−40−60 −20 100 140120806040200−40−60 −20 100 140

800

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Figure 21. Maximum On Time, avg(VCS) = 0.9 V

& Vctrl Maximum (CrM) & Low Line for

E Version (ton,LL,E) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

11.4

11.9

12.4

12.9

13.4

ton,LL(E) (ms)

120806040200−40−60 −20 100 140

Figure 22. Maximum On Time, avg(VCS) = 2.8 V

& Vctrl Maximum (CrM) & High Line for

E Version (ton,HL,E) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

3.75

3.85

3.95

4.05

4.25

4.35

4.45

4.55

ton,HL(E) (ms)

120806040200−40−60 −20 100 140

4.15

Figure 23. UVP Threshold, VFB Increasing

(VUVPH) vs. Junction Temperature

Figure 24. UVP Threshold, VFB Decreasing

(VUVPL) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

120806040200−40−60

555

575

595

615

635

655

200

220

260

280

320

340

380

400

Figure 25. UVP Threshold Hysteresis

(VUVPL(HYST)) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

200

220

260

280

300

340

380

400

VUVPH (mV)

VUVPL (mV)

VUVPL(HYST) (mV)

−20 100 140 120806040200−40−60 −20 100 140

120806040200−40−60 −20 100 140

240

300

360

240

320

360

Figure 26. Comparator Threshold for Line

Range Detection, avg(VCS) Rising, (VHL) vs.

Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

1.718

1.738

1.758

1.778

1.818

1.838

1.858

1.878

VHL (V)

120806040200−40−60 −20 100 140

1.798

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TYPICAL CHARACTERISTICS

Figure 27. Comparator Threshold for Line

Range Detection, avg(VCS) Falling, (VLL) vs.

Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

1.31

1.33

1.35

1.37

1.39

1.43

1.45

1.47

VLL (V)

120806040200−40−60 −20 100 140

1.41

Figure 28. Comparator Hysteresis for Line

Range Detection, (VHL(hyst)) vs. Junction

Temperature

TJ, JUNCTION TEMPERATURE (°C)

120806040200−40−60

0.075

0.125

0.175

0.225

0.325

0.375

0.425

0.475

VHLhys (V)

−20 100 140

0.275

Detailed Operating Description Introduction NCPlo02 is designed to optimize the efficiency of your PFC stage throughout the load range. ln addition, it incorporates protection features for rugged operation. More generally, NCPlo02 is ideal in systems where cost—effectiveness, reliability, low stand—by power and high efficiency are key requirements: I Valley Synchronized Frequency Fold—back: NCPlo02 is designed to drive PFC boost stages in so—called Valley Synchronized Frequency Fold—back (vs F). In this mode, the circuit cl ‘cally operates in Critical conduction Mode (CrM) when le exceeds a programmable value. when the vs,r1 is below this preset level, NCPlooz linearly reduces the frequency down to about 33 kHz before reaching the SKIP threshold voltage (SKIP Mode versions [5”] and [D""]). VSFF maximizes the efficiency at both nominal and light load 1 particular ~tand—by lo -- s are reduced to a mi mum. Similarly to FCCrM controllers, an internal circuitry allows near—unity power factor even when the switching frequency is reduced. I SKIP Mode (Versions [B**] and [D**]): to further optimize the efficiency, the circuit skips cycles at low load current when Vdrl reaches the SKIP threshold voltage. Th' ' to avoid circuit operation when the power tra :fer i. particularly inefficient at the cost of current distortion. This SKIP function is not present on versions [A""] and [C"]). I Low Start—up Current and large Vcc range ([**A] versions): The start—up consumption of the circuit is minimized to allow the use of high—impedance start—up r . ors to pre—charge the Vcc capacitor. Also, the minimum value of the UVLO hysteresi (i V to avoid the need for large v65 capacitors and help : orten the start—up time without the need for too d pative start—up elements. The [MC] version is preferred in applications where the circuit ed by an external power source (from an auxiliary power supply or from a downstream converter). lts maximum start—up level (11.25 v) i, 'et low enough so that the circuit can be powered from a 12—v rail. After start—up, the high vgc maximum rating allows a large operating range from 9.5 v up to 30 v. I Fast Line / Load Transient Compensation (Dynamic Response Enhancer): Since PFC stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start—up) m' under—shoot. This circuit limits p from the regulation level as follows. . NCPlo02 linearly decays the power deliverv to zero when the output voltage exceeds 105% of its desired cause excessive over or ble deviations level (soft OVP). If [h yft OVP is too smooth and the output continues to :e, the circuit immediately interrupts the power delivery when the output voltage is 107% above its desired level. s NCPlo02, dramatically speeds—up the regulation loop when the output voltage goes below 95.5% of its regulation level. Thi. unctioo is enabled only after the PFC stage hat 1 arted—up to allow normal soft—start operation to occur. I Safety Protections: Permanently monitoring the input and output voltages, the MOSFET current and the die temperature to protect the s ' em from p ' ble over—stress making the PFC stage extremely robust and reliable. In addition to the OVP protection, the following methods of protection are provided: s Maximum Current Lim' The circuit sen s the MOSFET current and turns off the power , witch if the set current limit is exceeded. In addition, the circuit enters a low duty—cycle operation mode whe the current reaches 150% of the current limit as a result of the inductor saturation or a short of the bypas diode. s Under—Voltage Protection: This circuit turns off when it detects that the output voltage i. below 12% of the voltage reference (typically). T _ eature protects the PFC stage if the ac line is too low or if there 1 a failure in the feedback network (e.g., bad connection). s Brown—Out Detection: The circuit detects low ac line conditions and stops operation thus protecting the PFC stage from excess ve stress. s Thermal Shutdown: An internal thermal circuitry disables the gate drive when the junction temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 100°C (50°C hysteresi . 0 Output Stage Totem Pole: NCPlﬁllZ incorporat ' —o.5 A / +0.8 A gate driver to efficiently drive m :t T0220 or T0247 power MOSFETs. NCP1602 Operation Modes As mentioned, NCPlﬁIlZ PFC controller implements Valley Synchronized Frequency Fold—back (VSFF) where s The circuit operates in cla ‘IC’dl Critical conduction Mode (CrM) when van. exceeds a programmable value mums. s When ch is below this whim}, the NCPlﬁUZ linearly reduces the operating frequency down to about 33 kHz s when Vctrl reaches vsn1 minimum value or the var SKIP mode threshold, the system works in low frequency burst mode. www.cnsemi.eam

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Detailed Operating Description

Introduction

NCP1602 is designed to optimize the efficiency of your

PFC stage throughout the load range. In addition, it

incorporates protection features for rugged operation. More

generally, NCP1602 is ideal in systems where

cost−effectiveness, reliability, low stand−by power and high

efficiency are key requirements:

•Valley Synchronized Frequency Fold−back:

NCP1602 is designed to drive PFC boost stages in

so−called Valley Synchronized Frequency Fold−back

(VSFF). In this mode, the circuit classically operates in

Critical conduction Mode (CrM) when Vctrl exceeds a

programmable value. When the Vctrl is below this

preset level, NCP1602 linearly reduces the frequency

down to about 33 kHz before reaching the SKIP

threshold voltage (SKIP Mode versions [B**] and

[D**]). VSFF maximizes the efficiency at both nominal

and light load. In particular, stand−by losses are

reduced to a minimum. Similarly to FCCrM

controllers, an internal circuitry allows near−unity

power factor even when the switching frequency is

reduced.

•SKIP Mode (Versions [B**] and [D**]):

to further optimize the efficiency, the circuit skips

cycles at low load current when Vctrl reaches the SKIP

threshold voltage. This is to avoid circuit operation

when the power transfer is particularly inefficient at the

cost of current distortion. This SKIP function is not

present on versions [A**] and [C**]).

•Low Start−up Current and large VCC range ([**A]

versions): The start−up consumption of the circuit is

minimized to allow the use of high−impedance start−up

resistors to pre−charge the VCC capacitor. Also, the

minimum value of the UVLO hysteresis is 6 V to avoid

the need for large VCC capacitors and help shorten the

start−up time without the need for too dissipative

start−up elements. The [**C] version is preferred in

applications where the circuit is fed by an external

power source (from an auxiliary power supply or from

a downstream converter). Its maximum start−up level

(11.25 V) is set low enough so that the circuit can be

powered from a 12−V rail. After start−up, the high VCC

maximum rating allows a large operating range from

9.5 V up to 30 V.

•Fast Line / Load Transient Compensation (Dynamic

Response Enhancer): Since PFC stages exhibit low

loop bandwidth, abrupt changes in the load or input

voltage (e.g. at start−up) may cause excessive over or

under−shoot. This circuit limits possible deviations

from the regulation level as follows:

♦NCP1602 linearly decays the power delivery to zero

when the output voltage exceeds 105% of its desired

level (soft OVP). If this soft OVP is too smooth and

the output continues to rise, the circuit immediately

interrupts the power delivery when the output

voltage is 107% above its desired level.

♦NCP1602, dramatically speeds−up the regulation

loop when the output voltage goes below 95.5% of

its regulation level. This function is enabled only

after the PFC stage has started−up to allow normal

soft−start operation to occur.

•Safety Protections: Permanently monitoring the input

and output voltages, the MOSFET current and the die

temperature to protect the system from possible

over−stress making the PFC stage extremely robust and

reliable. In addition to the OVP protection, the

following methods of protection are provided:

♦Maximum Current Limit: The circuit senses the

MOSFET current and turns off the power switch if

the set current limit is exceeded. In addition, the

circuit enters a low duty−cycle operation mode when

the current reaches 150% of the current limit as a

result of the inductor saturation or a short of the

bypass diode.

♦Under−Voltage Protection: This circuit turns off

when it detects that the output voltage is below 12%

of the voltage reference (typically). This feature

protects the PFC stage if the ac line is too low or if

there is a failure in the feedback network (e.g., bad

connection).

♦Brown−Out Detection: The circuit detects low ac

line conditions and stops operation thus protecting

the PFC stage from excessive stress.

♦Thermal Shutdown: An internal thermal circuitry

disables the gate drive when the junction

temperature exceeds 150°C (typically). The circuit

resumes operation once the temperature drops below

approximately 100°C (50°C hysteresis).

•Output Stage Totem Pole: NCP1602 incorporates a

−0.5 A / +0.8 A gate driver to efficiently drive most

TO220 or TO247 power MOSFETs.

NCP1602 Operation Modes

As mentioned, NCP1602 PFC controller implements a

Valley Synchronized Frequency Fold−back (VSFF) where:

♦The circuit operates in classical Critical conduction

Mode (CrM) when Vctrl exceeds a programmable

value Vctrl,th,*.

♦When Vctrl is below this Vctrl,th,* , the NCP1602

linearly reduces the operating frequency down to

about 33 kHz

♦When Vctrl reaches Vcrtl minimum value or the Vctrl

SKIP mode threshold, the system works in low

frequency burst mode.

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High Current

No delay èCrM

Low Current

The next cycle is

delayed

Lower Current

Longer dead−time

Timer delay

High Current

No delay èCrM

Low Current

The next cycle is

delayed

Lower Current

Longer dead−time

Timer delay

Figure 29. Valley Switching Operation in CrM and DCM Modes

As illustrated in Figure 29, under high load conditions, the

boost stage is operating in CrM but as the load is reduced, the

controller enters controlled frequency discontinuous

operation.

To further reduce the losses, the MOSFET turns on is

stretched until its drain−source voltage is at its valley. The

end of the dead time is synchronized with the drain−source

ringing.

Valley Synchronized Frequency Foldback (VSFF)

a/ Valley Synchronized (VS)

DRV 200−us

WATCHDOG

CS/ZCD ZCD TIMER

Zero Current Detection Dead−Time (DT) Ramp for DT Control

Clock Generation

DRV

CLK

Vcsint

Vctrl

ZCD

DEMAG

SENSING

CSZCD

BUFFER

DEAD TIME

GENERATOR

END OF DEMAG

SENSING

END OF DEAD TIME

SYNCHRONIZATION

DRV

VCTRL

Figure 30. Valley Synchronized Turn−on Block Diagram

Valley Synchronized is the first half of the VSFF system.

Synchronizing the Turn−on with the drain voltage valley

maximizes the efficiency at both nominal and light load

conditions. In particular, the stand−by losses are reduced to

a minimum. The synchronization of Power MOSFET

Turn−on (rising edge of CLK signal) with drain voltage

valley is depicted on Figure 30. This method avoids system

stalls between valleys. Instead, the circuit acts so that the

PFC controller transitions from the n valley to (n+1) valley

or vice versa from the n valley to (n−1) cleanly as illustrated

by the simulation results of Figure 31. When the Line

voltage and inductor current are very low, or when the

amplitude of the drain voltage gets too low (in the case of

long dead times), the turn−on of the power MOSFET is no

longer synchronized with the drain valley but will start

exactly at the end of a programmed dead time looks to the

ZCD TIMER block.

If no demagnetization is sensed the power MOSFET will

be turned−on after a watchdog timing of 200−ms.

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−0

100

150

200

250

300

350

2.42

2.44

2.46

2.48

2. 5

2.52

2.54

385.69 385.695 385.7 385.705 385.71

−0. 2

0. 2

0. 4

0. 6

0. 8

1. 2

1. 4

1. 6

1. 8

Inductor Current

(100 mA/div)

DRV

(2 V/div)

Ramp + Vffctl

(20mV/div)

Drain Source Voltage

(50 V/div)

Time (5 uSecs /div)

3rd Valley 4th Valley

VREF,DT

Figure 31. Clean Transition Without Hesitation Between Valleys

b/ Frequency Foldback (FF)

Frequency Foldback is the second half of the VSFF system.

When Vctrl falls below an option−programmable Vctrl,th,*

threshold, the NCP1602 enters DCM and linearly reduces

the operating frequency down to about 33 kHz by adding a

dead−time after the end of inductor demagnetization. The

end of the dead−time is synchronized with the valley in the

drain voltage, hence the name Valley Synchronized (VS).

The lower the Vctrl value, the longer the dead−time.

The Frequency Foldback (FF) system adjusts the on−time

versus tDT (see Figure 32) and the output power in order to

ensure that the instantaneous mains current is in phase with

the mains instantaneous voltage (creating a PF=1).

Ipeak ,max

Iind

CLK

tON tDEMAG

Tsw

tDT

time

DRV

Figure 32. NCP1602 Clock, Dead Time and tON Waveforms

hold VSKIP- d whcnc (as dicmmd by NCP1602 Onit analyze boom slagc. Th each switching up when the M0 indud inducmr 5mm 11 umil i1 rc some cascs,‘ 1a. ‘ until the n One can show 2TL 5 me switching (h proportional to

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When the load is at its maximum (the maximum Vctrl

value and inductor peak current limitation is not triggering),

the controller runs in CrM mode and the frequency

(@V

in=V

in,max) has its minimum value. As we start

decreasing the output power, the Vctrl voltage decreases, the

switching frequency (@V

in=V

in,max) increases and the

controller stays in CrM mode until Vctrl reaches a threshold

voltage named Vctrl,th,*. From this point, continuing to

reduce the output power makes the controller to continue

increase the dead time (TDT) after the end of

demagnetization resulting in a DCM conduction mode and

a switching frequency decrease (Frequency Foldback).

When the output power is reduced and we enter DCM

mode, the switching frequency decreases down to a value

given by the following equation, which is valid down to

before entering SKIP mode. This minimum DCM frequency

value is dominated by the dead time value, tON plus tDEMAG

being negligible versus tDT that has reached is maximum

value tDT,max.

FSW, DCM, min +1

tDT,max )tON )tDEMAG [1

tDT,max

(eq. 1)

In order to have, depending on customer application, a

different limitation of the maximum switching frequency

(@Vin=Vin,max), as well as different Vctrl thresholds for

CrM to DCM boundary, different product versions are made

available (see Table 2).

CrM−DCM and DCM−CrM Transition Hysteresis

Hesitation of the system to transition between the modes

CrM and DCM may have a consequences on inductor

current shape and distort the mains current, resulting in a bad

PF value when the operating point is at the CrM−DCM

boundary.

To avoid such undesired behavior, a 40−mV hysteresis is

added on Vctrl threshold. The Vctrl threshold for transitioning

from CrM to DCM mode is named Vctrl,th,* (see Table 6) and

the Vctrl threshold for transitioning from DCM to CrM mode

is Vctrl,th,* + 40 mV.

NCP1602 Skip Mode (Active on Versions [B**] and

[D**], Disabled on Versions [A**] and [C**])

The circuit also skips cycles when Vctrl decreases towards

VSKIP−L threshold. A comparator monitors the Vctrl voltage

and inhibits the drive when Vctrl is lower than the SKIP

Mode threshold VSKIP−L. Switching resumes when Vctrl

exceeds VSKIP−H threshold. The skip mode capability is

disabled whenever the PFC stage is not in nominal operation

(as dictated by the PFCOK signal − see PFCOK Operation

section).

NCP1602 On−time Modulation and VTON Processing

Circuit

Let’s analyze the ac line current absorbed by the PFC

boost stage. The initial inductor current at the beginning of

each switching cycle is always zero. The coil current ramps

up when the MOSFET is on. The slope is (Vin/L) where L is

the coil inductance. At the end of the on−time (t1), the

inductor starts to demagnetize. The inductor current ramps

down until it reaches zero. The duration of this phase is (t2).

In some cases, the system enters then the dead−time (t3) that

lasts until the next clock is generated.

One can show that the ac line current is given by:

Iin +Vin

t1ǒt1)t2Ǔ

2T L (eq. 2)

Where

T+t1)t2)t3(eq. 3)

is the switching period and V

in is the ac line rectified voltage.

In light of this equation, we immediately note that Iin is

proportional to V

in if [t1.(t1+t2)/T] is a constant.

Ipeak,max

Iind t1t2

Vin

time

L1 D1

Vin Vout

Iind

Cbulk

Cin

DRV

Rsense

time

Figure 33. PFC Boost Converter and Inductor Current in DCM

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The NCP1602 operates in voltage mode. As portrayed by

Figure 33 & Figure 34, the MOSFET on−time t1 is set by a

dedicated circuitry monitoring Vctrl and dead−time tDT

ensuring [t1.(t1+t2)/T] is constant and as a result making Iin

proportional to V

in (PF=1)

On−time t1 is also called ton and its maximum value ton,max

is obtained when Vctrl is at maximum level. The internal

circuitry makes ton,max at High Line condition (HLINE) to

be 3 times the ton,max at Low Line condition (LLINE)

(low−pass filtered internal CS−pin voltage is compared to

VHL and VLL for deciding whether we are in HLINE or in

LLINE). Two other values of ton,max are offered as options.

The input current is then proportional to the input voltage.

Hence, the ac line current is properly shaped.

One can note that this analysis is also valid in the CrM

case. This condition is just a particular case of this

functioning where (t3=0), which leads to (t1+t2=T) and

(Vton=Vregul). That is why the NCP1602 automatically

adapts to the conditions and transitions from DCM and CrM

(and vice versa) without power factor degradation and

without discontinuity in the power delivery.

Cramp

Ich

Vton

PWM

Comparator

Turns off

MOSFET

Closed when

output low

Vton

Ramp Voltage

PWM output

Figure 34. PWM Circuit and Timing Diagram

NCP1602 Regulation Block and Output Voltage Control

A trans−conductance error amplifier (OTA) with access to

the inverting input and output is provided. It features a

typical trans−conductance gain of 200 mS and a maximum

current capability of ±20 mA. The output voltage of the PFC

stage is typically scaled down by a resistors divider and

monitored by the inverting input (pin FB). Bias current is

minimized (less than 500 nA) to allow the use of a high

impedance feed−back network. However, it is high enough

so that the pin remains in low state if the pin is not connected.

The output of the error amplifier is brought to pin VCTRL

for external loop compensation. Typically a type−2 network

is applied between pin VCTRL and ground, to set the

regulation bandwidth below about 20 Hz and to provide a

decent phase boost.

The swing of the error amplifier output is limited within

an accurate range:

•It is forced above a voltage drop (VF) by some circuitry.

•It is clamped not to exceed 4.0 V + the same VF voltage

drop.

The VF value is 0.5 V typically. The regulated output voltage

Vout uses a reference voltage VREF = 2.5 V

Given the low bandwidth of the regulation loop, abrupt

variations of the load, may result in excessive over or

under−shoot. Over−shoot is limited by the Over−Voltage

Protection connected to FB pin ( Feedback).

NCP1602 embeds a “Dynamic Response Enhancer”

circuitry (DRE) that contains under−shoots. An internal

comparator monitors the FB pin voltage (VFB) and when

VFB is lower than 95.5% of its nominal value, it connects a

200−mA current source to speed−up the charge of the

compensation network. Effectively this appears as a 10x

increase in the loop gain.

The circuit also detects overshoot and immediately

reduces the power delivery when the output voltage exceeds

105% of its desired level.

The error amplifier OTA and the OVP, UVP and DRE

comparators share the same input information. Based on the

typical value of their parameters and if (Vout,nom) is the

output voltage nominal value (e.g., 390 V), we can deduce:

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•Output Regulation Level: Vout,nom

•Output DRE Level: Vout,dre = 95.5% x Vout,nom

•Output Soft OVP Level: Vout,sovp = 105% x Vout,nom

•Output Fast OVP level: Vout,fovp = 107% x Vout,nom

Current Sense and Zero Current Detection

NCP1602 is designed to monitor the current flowing

through the power switch during On−time for detecting over

current and overstress and to monitor the power MOSFET

drain voltage during demagnetization time and dead time in

order to generate the ZCD signal.

ZCD

CS/ZCD pin

Rcs1

Rcs2

Ccs

DRV

OCP

BLANKING

OVERSTRESS

OCP

VSNS

DRAIN

SOURCE

VOCP,REF

Vcsint

VOVS,REF

DRV

OVS

BLANKING

Vcc

CSZCD

BUFFER

DRV

DEMAG

& LINE SENSE

OVERSTRESS

TIMER

Figure 35. Current Sense, Zero Current Detection Blocks and Vin Sense

Current sense, zero current detection and Vin sense are

using the CS/ZCD pin voltage as depicted in the electrical

schematic of Figure 35.

Current Sense

The power MOSFET current I is sensed during the TON

phase by the resistor Rsense inserted between the MOSFET

source and ground (see Figure 36). During TON phase Rcs1

and Rcs2 are almost in parallel and the signal Rsense.I is equal

to the voltage on pin CS.

Rcs1

Rcs2

Ccs

Rsense

Rdson

Rcs1

Rcs2

Ccs

Rsense

D,S CS

Figure 36. Current Sensing during the TON Phase

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During the On−time and after a 200−ns blanking time, an

OCP (Over Current Protection) signal is generated by an

OCP comparator, comparing (VCS = VCS2) to a 500−mV

internal reference.

When RsenseIds_max = VCS = VCS2 = 500 mV we get:

Ids_max +Vocp

Rsense

(eq. 4)

When VCS exceeds the 500−mV internal reference

threshold, the OCP signal turns high to reset the PWM latch

and forces the driver low. The 200−ns blanking time

prevents the OCP comparator from tripping because of the

switching spikes that occur when the MOSFET turns on.

Zero Current Detection

The CS pin is also designed to receive, during tDEMAG and

tDT, a scaled down (divided by 138) power MOSFET drain

voltage that will be used for Zero Current Detection. It may

happen that the MOSFET turns on while a huge current

flows through the inductor. As an example such a situation

can occur at start−up when large in−rush currents charge the

bulk capacitor to the line peak voltage. Traditionally, a

bypass diode is generally placed between the input and

output high−voltage rails to divert this inrush current. If this

diode is accidently shorted, the demagnetization will be

impossible and cycle after cycle the inductor current will

increase so the MOSFET will also see a high current when

it turns on. In both cases, the current can be large enough to

trigger the OverStress (OVS) comparator. In this case, the

“OverStress” signal goes high and disables the driver for an

800−ms delay. This long delay leads to a very low duty−ratio

operation in case of “OverStress” fault in order to limit the

risk of overheating.

When no signal is received that triggers the ZCD

comparator to indicate the end of inductor demagnetization,

an internal 200−ms watchdog timer initiates the next drive

pulse. At the end of this delay, the circuit senses the CS/ZCD

pin impedance to detect a possible grounding of this pin and

prevent operation.

Brown−Out Detection (Versions [C**] and [D**])

For an application w/o Vaux (using the Drain) and using

Brown−out options ([C**] and [D**]) the Brown−out

feature will use the High and Low Brown−out levels.

Brown−out options ([C**] and [D**]) must not be used on

an application using Vaux as these options are not designed

to work in this case.

By default, the Brown−out flag is set High (BONOK=1),

meaning that V

in,sensed thru CSZCD pin and Vsns (Vsns is

a low−pass filtered scaled down Vin) internal signal (see

Figure 1), when higher than internal reference voltage

VBOH will set the brown−out flag to zero (BONOK=0) and

allow the controller to start. After BONOK is set to zero, and

switching activity starts, the Vin continues to be sensed thru

CSZCD pin and when Vsns falls under Brown−out internal

reference voltage VBOL for 50 ms, BONOK flag will be set

to 1. After BONOK flag will be set to 1, drive is not disabled,

instead, a 30−mA current source is applied to VCTRL pin to

gradually reduce Vctrl. As a result, the circuit only stops

pulsing when the STATICOVP function is activated (that is

when Vctrl reaches the SKIP detection threshold). At that

moment, the circuit stops switching. This method limits any

risk of false triggering.

For an application w/ Vaux (not using the Drain),

Brown−out options ([C**] and [D**]) are not be allowed

and the UVP will act like a brown−in. The reason is that

before controller starts switching, the Vout voltage is equal

to Vmains,rms and sensed by FB pin and compared to UVP

high internal reference voltage VUVPH.

The input of the PFC stage has some impedance that leads

to some sag of the input voltage when the input current is

large. If the PFC stage suddenly stops while a high current

is drawn from the mains, the abrupt decay of the current may

make the input voltage rise and the circuit detect a correct

line level. Instead, the gradual decrease of Vcontrol avoids a

line current discontinuity and limits the risk of false

triggering.

Vsns internal voltage is also used to sense the line for

feed−forward. A similar method is used:

•The Vsns internal pin voltage is compared to a 1.801−V

reference.

•If Vsns exceeds 1.801V, the circuit detects a high−line

condition and the loop gain is divided by three (the

internal PWM ramp slope is three times steeper)

•Once this occurs, if Vsns remains below 1.392 V for

25 ms, the circuit detects a low−line situation (500−mV

hysteresis).

At startup, the circuit is in High−line state (“LLINE” Low”)

and then Vsns will be used to determine the High−Line or

Low−Line state.

The line range detection circuit allows more optimal loop

gain control for universal (wide input mains) applications.

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VREF,LLINE

VREF,BONOK

CSint VSNS

1.801 V if LLINE=1

1.392 V otherwise

0. 819 V if BONOK=1

0. 737 V otherwise

CSZCD

BUFFER

DEMAG

LINE SENSE

DRV

Figure 37. Input Line Sense Monitoring

Thermal Shut−Down (TSD)

An internal thermal circuitry disables the circuit gate drive

and keeps the power switch off when the junction

temperature exceeds 150°C. The output stage is then

enabled once the temperature drops below about 100°C

(50°C hysteresis).

The temperature shutdown remains active as long as the

circuit is not reset, that is, as long as VCC is higher than a reset

threshold.

Output Drive Section

The output stage contains a totem pole optimized to

minimize the cross conduction current during high

frequency operation. Its high current capability (−500 mA /

+800 mA) allows it to effectively drive high gate charge

power MOSFET.

Second Over−Voltage Protection

On top of the existing overvoltage protection, a second

and redundant overvoltage protection named OVP2 has

been added. This overvoltage protection, senses, during

tDEMAG the value of V

out, thru the RCS1, RCS2 divider bridge

connected to the pin CS and compares it to an OVP2 voltage

reference VREF,OVP2. Because it is not possible to adjust the

VREF,OVP2 reference to Rfb1& Rfb2 that programs the V

out

value, it has been decided to set VREF,OVP2 and RCS1, RCS2

in order to get OVP2 triggering for Vout voltages much

higher than for OVP condition (e.g. OVP2 goes high when

Vout goes higher than 438 V)

For Vout = 438 V for OVP2 and given a KCS value equal

to 1/138 (KCS =R

CS2 /(R

CS1 +R

CS2), this gives

VREF,OVP2 = 3.175 V for the threshold voltage to which is

compared to the CS voltage during toff. When VCS goes

above VREF,OVP2 threshold of the OVP2 comparator

(100 mV hysteresis), and after a 1−ms leading edge blanking

time, the OVP2 flag is latched and will stop the switching by

resetting the main PWM latch. The OVP2 latch is reset each

800 ms.

OFF Mode

As previously mentioned, the circuit turns off when one

of the following faults is detected:

•Incorrect feeding of the circuit (“UVLO” high when

VCC <VCC(off), VCC(off) equating 9 V typically).

•Excessive die temperature detected by the thermal

shutdown

•Under−Voltage Protection

•Brown−Out Fault and STATICOVP (see Figure 2)

Generally speaking, the circuit turns off when the

conditions are not proper for desired operation. In this mode,

the controller stops operating. The major part of the circuit

sleeps and its consumption is minimized.

More specifically, when the circuit is in OFF state:

•The drive output is kept low

•All the blocks are off except:

♦The UVLO circuitry that keeps monitoring the VCC

voltage and controlling the start−up current source

accordingly.

♦The TSD (thermal shutdown)

♦The Under−Voltage Protection (“UVP”)

♦The brown−out circuitry

•Vctrl is grounded so that when the fault is removed, the

device starts−up under the soft start mode.

•The internal “PFCOK” signal is grounded.

•The output of the “Vton processing block” is grounded

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Failure Detection

When manufacturing a power supply, elements can be

accidentally shorted or improperly soldered. Such failures

can also happen to occur later on because of the components

fatigue or excessive stress, soldering defaults or external

interactions. In particular, adjacent pins of controllers can be

shorted; a pin can be grounded or badly connected. Such

open/short situations are generally required not to cause fire,

smoke nor big noise. NCP1602 integrate functions that ease

meet this requirement. Among them, we can list:

•Floating feedback pin

A special internal circuitry detects the floating feedback

pin and stops the operation of the IC.

•Fault of the GND connection

If the GND pin is not connected, internal circuitry

detects it and if such a fault is detected for 200 ms, the

circuit stops operating.

•Detection the CS/ZCD pin improper connection

If the CS/ZCD pin is floating or shorted to GND it is

detected by internal circuitry and the circuit stops

operating.

•Boost or bypass diode short

The controller addresses the short situations of the

boost and bypass diodes (a bypass diode is generally

placed between the input and output high−voltage rails

to divert this inrush current). Practically, the overstress

protection is implemented to detect such conditions and

forces a low duty−cycle operation until the fault is gone.

Refer to application note ANDxxxx for more details.

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PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE V

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

STYLE 13:

PIN 1. GATE 1

2. SOURCE 2

3. GATE 2

4. DRAIN 2

5. SOURCE 1

6. DRAIN 1

RECOMMENDED

0.60

3.20 0.95

0.95

PITCH

DIMENSIONS: MILLIMETERS

456

0.05

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

DIM

MIN NOM MAX

MILLIMETERS

0.90 1.00 1.10

A1 0.01 0.06 0.10

b0.25 0.38 0.50

c0.10 0.18 0.26

D2.90 3.00 3.10

E2.50 2.75 3.00

e0.85 0.95 1.05

L0.20 0.40 0.60

0.25 BSC

−

0°10°

1.30 1.50 1.70

NOTE 5

SEATING

PLANE

GAUGE

PLANE

DETAIL Z

DETAIL Z M

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