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Datenblatt für L6229 von STMicroelectronics
This is information on a product in full production.
October 2018 DocID9455 Rev 5 1/33
L6229
DMOS driver for 3-phase brushless DC motor
Datasheet - production data
Features
Operating supply voltage from 8 to 52 V
2.8 A output peak current (1.4 A DC)
RDS(ON) 0.73 typ. value at Tj = 25 °C
Operating frequency up to 100 KHz
Non-dissipative overcurrent detection and
protection
Diagnostic output
Constant tOFF PWM current controller
Slow decay synchr. rectification
60° and 120° hall effect decoding logic
Brake function
Tachometer output for speed loop
Cross conduction protection
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Description
The L6229 is a DMOS fully integrated 3-phase
motor driver with overcurrent protection.
Realized in BCD technology, the device combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip.
The device includes all the circuitry needed to
drive a 3-phase BLDC motor including: a 3-phase
DMOS bridge, a constant off time PWM current
controller and the decoding logic for single ended
hall sensors that generates the required
sequence for the power stage.
Available in PowerSO36 and SO24 (20 + 2 + 2)
packages, the L6229 features a non-dissipative
overcurrent protection on the high-side power
MOSFETs and thermal shutdown.
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Table 1. Order codes
Part number Package
L6229DP PowerSO36
L6229D SO24
www.st.com
Contents L6229
2/33 DocID9455 Rev 5
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Tachometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . 22
11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 26
11.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.2 SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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DocID9455 Rev 5 3/33
L6229 Block diagram
33
1 Block diagram
Figure 1. Block diagram
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Maximum ratings L6229
4/33 DocID9455 Rev 5
2 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Test conditions Value Unit
VSSupply voltage VSA = VSB = VS60 V
VOD
Differential voltage between:
VSA, OUT1, OUT2, SENSEA and VSB, OUT3,
SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB = GND 60 V
VBOOT Bootstrap peak voltage VSA = VSB = VSVS + 10 V
VIN, VEN Logic inputs voltage range - -0.3 to 7 V
VREF Voltage range at pin VREF - -0.3 to 7 V
VRCOFF Voltage range at pin RCOFF - -0.3 to 7 V
VRCPULSE Voltage range at pin RCPULSE - -0.3 to 7 V
VSENSE Voltage range at pins SENSEA and SENSEB- -1 to 4 V
IS(peak)
Pulsed supply current (for each VSA and VSB
pin) VSA = VSB = VS; TPULSE < 1 ms 3.55 A
ISDC supply current (for each VSA and VSB pin) VSA = VSB = VS1.4 A
Tstg, TOP Storage and operating temperature range - -40 to 150 °C
Table 3. Recommended operating condition
Symbol Parameter Test conditions Min. Max. Unit
VSSupply voltage VSA = VSB = VS12 52 V
VOD
Differential voltage between:
VSA, OUT1, OUT2, SENSEA and VSB, OUT3,
SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
-52V
VREF Voltage range at pin VREF - -0.1 5 V
VSENSE Voltage range at pins SENSEA and SENSEB
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
IOUT DC output current VSA = VSB = VS-1.4A
fSW Switching frequency - - 100 KHz
DocID9455 Rev 5 5/33
L6229 Maximum ratings
33
Table 4. Thermal data
Symbol Description SO24 PowerSO36 Unit
Rth(j-pins) Maximum thermal resistance junction pins 15 - C/W
Rth(j-case) Maximum thermal resistance junction case - 2 C/W
Rth(j-amb)1 Maximum thermal resistance junction ambient(1) 55 - C/W
Rth(j-amb)1 Maximum thermal resistance junction ambient(2) -36C/W
Rth(j-amb)1 Maximum thermal resistance junction ambient(3) -16C/W
Rth(j-amb)2 Maximum thermal resistance junction ambient(4) 78 63 C/W
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of
35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm),
16 via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heat-sinking surface on the board.
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Pin connections L6229
6/33 DocID9455 Rev 5
3 Pin connections
Figure 2. Pin connections (top view)
1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
GND
GND
TACHO
RCPULSE
SENSE
B
EN
FWD/REV
1
3
2
4
5
6
7
8
9
VREF
VBOOT
BRAKE
OUT3
VS
B
GND
GND19
18
17
16
15
13
14
D01IN1194A
10
11
12
24
23
22
21
20
H1
DIAG
SENSE
A
RCOFF
OUT1VS
A
OUT2
VCP
H2
H3
GND
N.C.
N.C.
VS
A
RCOFF
OUT1
N.C.
N.C.
N.C. N.C.
N.C.
TACHO
RCPULSE
N.C.
VS
B
N.C.
N.C.
GND
1
3
2
4
13
14
15
16
17
34
33
24
23
22
20
21
19
35
18
36
GND GND
D01IN1195A
H1
SENSE
A
DIAG
SENSE
B
EN
FWD/REV
10
11
12
27
26
25
H3VREF9 28
OUT2
H2
VCP
BRAKE
OUT3
VBOOT
5
7
8
32
30
29
N.C. N.C.6 31
PowerSO36(1)
SO24
Table 5. Pin description
Package
Name Type FunctionSO24 PowerSO36
Pin no. Pin no.
110H
1Sensor input Single ended hall effect sensor input 1.
211DIAG
Open drain
output
Overcurrent detection and thermal protection pin. An
internal open drain transistor pulls to GND when an
overcurrent on one of the high-side MOSFETs is
detected or during thermal protection.
3 12 SENSEAPower supply
Half-bridge 1 and half-bridge 2 source pin. This pin
must be connected together with pin SENSEB to
power ground through a sensing power resistor.
4 13 RCOFF RC pin
RC network pin. A parallel RC network connected
between this pin and ground sets the current
controller OFF-time.
515OUT
1Power output Output 1
DocID9455 Rev 5 7/33
L6229 Pin connections
33
Package
Name Type FunctionSO24 PowerSO36
Pin no. Pin no.
6, 7, 18, 19 1, 18, 19, 36 GND GND
Ground terminals. On SO24 package, these pins are
also used for heat dissipation toward the PCB. On
PowerSO36 package the slug is connected on these
pins.
822TACHO
Open drain
output
Frequency-to-voltage open drain output. Every pulse
from pin H1 is shaped as a fixed and adjustable length
pulse.
9 24 RCPULSE RC pin
RC network pin. A parallel RC network connected
between this pin and ground sets the duration of the
monostable pulse used for the frequency-to-voltage
converter.
10 25 SENSEBPower supply
Half-bridge 3 source pin. This pin must be connected
together with pin SENSEA to power ground through
a sensing power resistor. At this pin also the inverting
input of the sense comparator is connected.
11 26 FWD/REV Logic input
Selects the direction of the rotation. HIGH logic level
sets forward operation, whereas LOW logic level sets
reverse operation. If not used, it has to be connected
to GND or +5 V.
12 27 EN Logic input Chip enable. LOW logic level switches OFF all power
MOSFETs. If not used, it has to be connected to +5 V.
13 28 VREF Logic input Current controller reference voltage.
Do not leave this pin open or connect to GND.
14 29 BRAKE Logic input
Brake input pin. LOW logic level switches ON all high-
side power MOSFETs, implementing the brake
function. If not used, it has to be connected to +5 V.
15 30 VBOOT Supply voltage Bootstrap voltage needed for driving the upper power
MOSFETs.
16 32 OUT3Power output Output 3.
17 33 VSBPower supply Half-bridge 3 power supply voltage. It must be
connected to the supply voltage together with pin VSA.
20 4 VSAPower supply
Half-bridge 1 and half-bridge 2 power supply voltage.
It must be connected to the supply voltage together
with pin VSB.
21 5 OUT2Power output Output 2.
22 7 VCP Output Charge pump oscillator output.
23 8 H2Sensor input Single ended hall effect sensor input 2.
24 9 H3Sensor input Single ended hall effect sensor input 3.
Table 5. Pin description (continued)
Electrical characteristics L6229
8/33 DocID9455 Rev 5
4 Electrical characteristics
Table 6. Electrical characteristics
(VS = 48 V , Tamb = 25 °C , unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSth(ON) Turn ON threshold - 5.8 6.3 6.8 V
VSth(OFF) Turn OFF threshold - 5 5.5 6 V
ISQuiescent supply current All bridges OFF;
Tj = -25 to 125 °C(1) -510mA
TJ(OFF) Thermal shutdown temperature - - 165 - C
Output DMOS transistors
RDS(ON) High-side + low-side switch ON resistance
Tj = 25 °C - 1.47 1.69
Tj = 125 °C(2) -2.352.70
IDSS Leakage current
EN = low; OUT = VCC -- 2mA
EN = low; OUT = GND -0.3 - - mA
Source drain diodes
VSD Forward ON voltage ISD = 1.4 A, EN = low - 1.15 1.3 V
trr Reverse recovery time If = 1.4 A - 300 - ns
tfr Forward recovery time - - 200 - ns
Logic input (H1, H2, H3, EN, FWD/REV, BRAKE)
VIL Low level logic input voltage - -0.3 - 0.8 V
VIH High level logic input voltage - 2 - 7 V
IIL Low level logic input current GND logic input voltage -10 - - A
IIH High level logic input current 7 V logic input voltage - - 10 A
Vth(ON) Turn-ON input threshold - - 1.8 2.0 V
Vth(OFF) Turn-OFF input threshold - 0.8 1.3 - V
VthHYS Input thresholds hysteresis - 0.25 0.5 - V
Switching characteristics
tD(on)EN Enable to out turn-ON delay time(2) ILOAD = 1.4 A, resistive load 500 650 800 ns
tD(off)EN
Enable to out turn-OFF delay time
(2) ILOAD = 1.4 A, resistive load 500 - 1000 ns
tD(on)IN Other logic inputs to output turn-ON delay time ILOAD = 1.4 A, resistive load - 1.6 - µs
tD(off)IN Other logic inputs to out turn-OFF delay time ILOAD = 1.4 A, resistive load - 800 - ns
tRISE Output rise time(2) ILOAD = 1.4 A, resistive load 40 - 250 ns
tFALL Output fall time(2) ILOAD = 1.4 A, resistive load 40 - 250 ns
tDT Deadtime - 0.5 1 - µs
fCP Charge pump frequency Tj = -25 to 125 °C(6) -0.6 1MHz
DocID9455 Rev 5 9/33
L6229 Electrical characteristics
33
Symbol Parameter Test conditions Min. Typ. Max. Unit
PWM comparator and monostable
IRCOFF Source current at pin RCOFF V
RCOFF = 2.5 V 3.5 5.5 - mA
VOFFSET Offset voltage on sense comparator Vref = 0.5 V - ±5 - mV
tprop Turn OFF propagation delay(3) Vref = 0.5 V - 500 - ns
tblank Internal blanking time on sense comparator - - 1 - µs
tON(min) Minimum on time - - 2.5 3 µs
tOFF PWM recirculation time
ROFF = 20 k; COFF 1 nF - 13 - s
ROFF =
100 k; COFF 1 nF - 61 - s
IBIAS Input bias current at pin VREF - - - 10 µA
TACHO monostable
IRCPULSE Source current at pin RCPULSE VRCPULSE = 2.5 V 3.5 5.5 - mA
tPULSE Monostable of time
RPUL = 20 k; CPUL 1 nF - 12 - s
RPUL =
100 k; CPUL 1 nF - 60 - s
RTACHO Open drain ON resistance - - 40 60
Overcurrent detection and protection
ISOVER Supply overcurrent protection threshold TJ = -25 to 125 °C(1) 2 2.8 3.55 A
ROPDR Open drain ON resistance IDIAG = 4 mA - 40 60
IOH OCD high level leakage current VDIAG = 5 V - 1 - µA
tOCD(ON) OCD turn-ON delay time(4) IDIAG = 4 mA;
CDIAG < 100 pF -200 - ns
tOCD(OFF) OCD turn-OFF delay time(9) IDIAG = 4 mA;
CDIAG < 100 pF -100 - ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3: Switching characteristic definition.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4: Overcurrent detection timing definition.
Table 6. Electrical characteristics
(VS = 48 V , Tamb = 25 °C , unless otherwise specified) (continued)
Electrical characteristics L6229
10/33 DocID9455 Rev 5
Figure 3. Switching characteristic definition
Figure 4. Overcurrent detection timing definition
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
ISOVER
90%
10%
IOUT
VDIAG
tOCD(OFF)
tOCD(ON)
D02IN1387
ON
OFF
BRIDGE
DocID9455 Rev 5 11/33
L6229 Circuit description
33
5 Circuit description
5.1 Power stages and charge pump
The L6229 device integrates a 3-phase bridge, which consists of 6 power MOSFETs
connected as shown in Figure 1: Block diagram on page 3. Each power MOS has an
RDS(ON) = 0.73 (typical value at 25 °C) with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see Section 6: PWM current control on page 13 and Section 8: Decoding logic on
page 18). Cross conduction protection is implemented by using a deadtime (tDT = 1 µs
typical value) set by internal timing circuit between the turn off and turn on of two power
MOSFETs in one leg of a bridge.
Pins VSA and VSB MUST be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 KHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 7.
Figure 5. Charge pump circuit
Table 7. Charge pump external component values
Component Value
CBOOT 220 nF
CP10 nF
RP100
D11N4148
D21N4148
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP VBOOT VS
B
D01IN1328
Circuit description L6229
12/33 DocID9455 Rev 5
5.2 Logic inputs
Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS compatible logic inputs. The
internal structure is shown in Figure 6. Typical value for turn-ON and turn-OFF thresholds
are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V.
Pin EN (enable) may be used to implement overcurrent and thermal protection by
connecting it to the open collector DIAG output. If the protection and an external disable
function are both desired, the appropriate connection must be implemented. When the
external signal is from an open collector output, the circuit in Figure 7 can be used . For
external circuits that are push-pull outputs the circuit in Figure 8 could be used. The resistor
REN should be chosen in the range from 2.2 K to 180 K. Recommended values for REN
and CEN are respectively 100 K and 5.6 nF. More information for selecting the values can
be found in Section 10: Non-dissipative overcurrent detection and protection on page 22.
Figure 6. Logic input internal structure
Figure 7. Pin EN open collector driving
Figure 8. Pin EN push-pull driving
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L6229 PWM current control
33
6 PWM current control
The L6229 device includes a constant off time PWM current controller. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense
resistor connected between the source of the three lower power MOS transistors and
ground, as shown in Figure 9. As the current in the motor increases the voltage across the
sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator
triggers the monostable switching the bridge off. The power MOS remains off for the time
set by the monostable and the motor current recirculates around the upper half of the bridge
in slow decay mode as described in Section 7: Slow decay mode on page 17. When the
monostable times out, the bridge will again turn on. Since the internal deadtime, used to
prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective
off time tOFF is the sum of the monostable time plus the deadtime.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
Section 7.
Immediately after the power MOS turns on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6229 device provides
a 1 µs blanking time tBLANK that inhibits the comparator output so that the current spike
cannot prematurely retrigger the monostable.
Figure 9. PWM current controller simplified schematic
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PWM current control L6229
14/33 DocID9455 Rev 5
Figure 10. Output current regulation waveforms
Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
Equation 1
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
deadtime with:
Equation 2
20 K ROFF 100 K
0.47 nF COFF 100 nF
tDT = 1 µs (typical value)
Therefore:
Equation 3
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
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DocID9455 Rev 5 15/33
L6229 PWM current control
33
The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the
pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing
a good current regulation by the PWM stage. Furthermore, the on time tON cannot be
smaller than the minimum on time tON(MIN).
Equation 4
tRCRISE = 600 · COFF
Figure 12 shows the lower limit for the on time tON for having a good PWM current
regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the
device imposes this condition, but it can be smaller than tRCRISE - tDT
. In this last case the
device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for COFF
, the more
influential will be the noises on the circuit performance.
Figure 11. tOFF versus COFF and ROFF
tON tON MIN
>2.5s (typ. value)=
tON tRCRISE tDT
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Figure 12. Area where tON can vary maintaining the PWM regulation
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DocID9455 Rev 5 17/33
L6229 Slow decay mode
33
7 Slow decay mode
Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At
any time only two legs of the 3-phase bridge are active, therefore only the two active legs of
the bridge are shown in Figure 13 and the third leg will be off. At the start of the off time, the
lower power MOS is switched off and the current recirculates around the upper half of the
bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime
the upper power MOS is operated in the synchronous rectification mode reducing the
impedance of the freewheeling diode and the related conducting losses. When the
monostable times out, upper MOS that was operating the synchronous mode turns off and
the lower power MOS is turned on again after some delay set by the deadtime to prevent
cross conduction.
Figure 13. Slow decay mode output stage configurations
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Decoding logic L6229
18/33 DocID9455 Rev 5
8 Decoding logic
The decoding logic section is a combinatory logic that provides the appropriate driving of the
3-phase bridge outputs according to the signals coming from the three hall sensors that
detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates
between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical
degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are
valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions
1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical
degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in
common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical
degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following
Table 8. For any input configuration (H1, H2 and H3) there is one output configuration
(OUT1, OUT2 and OUT3). The output configuration 3a is the same as 3b and analogously
output configuration 6a is the same as 6b.
The sequence of the hall codes for 300 electrical degrees phasing is the reverse of 60 and
the sequence of the hall codes for 240 phasing is the reverse of 120. So, by decoding the 60
and the 120 codes it is possible to drive the motor with all the four conventions by changing
the direction set.
Table 8. 60 and 120 electrical degree decoding logic in forward direction
Hall 120° 1 2 3a - 4 5 6a -
Hall 60° 1 2 - 3b 4 5 - 6b
H1HH L H L LHL
H2LH H HH LLL
H3LL L HHHHL
OUT1Vs High Z GND GND GND High Z Vs Vs
OUT2High Z Vs Vs Vs High Z GND GND GND
OUT3GND GND High Z High Z Vs Vs High Z High Z
Phasing 1 -> 3 2 -> 3 2 -> 1 2 -> 1 3 -> 1 3 -> 2 1 -> 2 1 -> 2
I I o o
o o o o o I o o o o o
1 H H1 1 H H1 H1 H1 H1 H1 H1
0
H H, H H1 H H,
o o 0 o o o
o o o o o o
H H1 H H1 H1 H1
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DocID9455 Rev 5 19/33
L6229 Decoding logic
33
Figure 14. 120° hall sensor sequence
Figure 15. 60° hall sensor sequence
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Tachometer L6229
20/33 DocID9455 Rev 5
9 Tachometer
A tachometer function consists of a monostable, with constant off time (tPULSE), whose input
is one hall effect signal (H1). It allows developing an easy speed control loop by using an
external op amp, as shown in Figure 16. For component values refer to Section 11:
Application information on page 25.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the
hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin
TACHO is turned off for a constant time tPULSE (see Figure 17). The off time tPULSE can be
set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18
gives the relation between tPULSE and CPUL, RPUL. We have approximately:
Equation 5
tPULSE = 0.6 · RPUL · CPUL
where CPUL should be chosen in the range from 1 nF to 100 nF and RPUL in the range from
20 K to 100 K.
By connecting the tachometer pin to an external pull-up resistor, the output signal average
value VM is proportional to the frequency of the hall effect signal and, therefore, to the motor
speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an
integrator, filters the signal and compares it with a reference voltage VREF
, which sets the
speed of the motor.
Equation 6
Figure 16. TACHO operation waveforms
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DocID9455 Rev 5 21/33
L6229 Tachometer
33
Figure 17. Tachometer speed control loop
Figure 18. tPULSE versus CPUL and RPUL
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Non-dissipative overcurrent detection and protection L6229
22/33 DocID9455 Rev 5
10 Non-dissipative overcurrent detection and protection
The L6229 device integrates an “Overcurrent Detection” circuit (OCD) for full protection.
This circuit provides output to output and output to ground short-circuit protection as well.
With this internal overcurrent detection, the external current sense resistor normally used
and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic
for the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high-side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF
. When the
output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a C or to shut down the 3-phase
bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN).
Figure 19. Overcurrent protection simplified schematic
Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when
an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 22.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
delay time and the REN value should be chosen according to the desired disable time.
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DocID9455 Rev 5 23/33
L6229 Non-dissipative overcurrent detection and protection
33
The resistor REN should be chosen in the range from 2.2 K to 180 K. Recommended
values for REN and CEN are respectively 100 K and 5.6 nF that allow obtaining 200 s
disable time.
Figure 20. Overcurrent protection waveforms
Figure 21. tDISABLE versus CEN and REN
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24/33 DocID9455 Rev 5
Figure 22. tDELAY versus CEN
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L6229 Application information
33
11 Application information
A typical application using the L6229 device is shown in Figure 23. Typical component
values for the application are shown in Table 9. A high quality ceramic capacitor (C2) in the
range of 100 nF to 200 nF should be placed between the power pins VSA and VSB and
ground near the L6229 device to improve the high frequency filtering on the power supply
and reduce high frequency transients generated by the switching. The capacitor (CEN)
connected from the EN input to ground sets the shutdown time when an overcurrent is
detected (see Section 10: Non-dissipative overcurrent detection and protection). The two
current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistor
RSENSE with a trace length as short as possible in the layout. The sense resistor should be
non-inductive resistor to minimize the di/dt transients across the resistor. To increase noise
immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic
level) (see Table 5: Pin description on page 6). It is recommended to keep power ground
and signal ground separated on PCB.
Table 9. Component values for typical application
Component Value
C1100 µF
C2100 nF
C3220 nF
CBOOT 220 nF
COFF 1 nF
CPUL 10 nF
CREF1 33 nF
CREF2 100 nF
CEN 5.6 nF
CP10 nF
D11N4148
D21N4148
R15.6 K
R21.8 K
R34.7 K
R41 M
RDD 1 K
REN 100 K
RP100
RSENSE 0.6
ROFF 33 K
RPUL 47 K
RH1, RH2, RH3 10
Application information L6229
26/33 DocID9455 Rev 5
Figure 23. Typical application
11.1 Output current capability and IC power dissipation
In Figure 24 is shown the approximate relation between the output current and the IC power
dissipation using PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper
dissipating area to guarantee a safe operating junction temperature (125 °C maximum).
Figure 24. IC power dissipation versus output power
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L6229 Application information
33
11.2 Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Selecting the
appropriate package and heatsinking configuration for the application is required to maintain
the IC within the allowed operating temperature range for the application. Figure 25 and 26
show the junction to ambient thermal resistance values for the PowerSO36 and SO24
packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper
thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 m), the
Rth(j-amb) is about 35 °C/W. Figure 26 shows mounting methods for this package. Using
a multilayer board with vias to a ground plane, thermal impedance can be reduced down to
15 °C/W.
Figure 25. PowerSO36 junction ambient thermal resistance versus on-board copper
area
Figure 26. SO24 junction ambient thermal resistance versus on-board copper area
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Application information L6229
28/33 DocID9455 Rev 5
Figure 27. Mounting the PowerSO package
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
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DocID9455 Rev 5 29/33
L6229 Package information
33
12 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
12.1 PowerSO36 package information
Figure 28. PowerSO36 package outline
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Package information L6229
30/33 DocID9455 Rev 5
Table 10. PowerSO36 package mechanical data
Symbol
Dimensions
mm inch
Min. Typ. Max. Min. Typ. Max.
A - - 3.60 - - 0.141
a1 0.10 - 0.30 0.004 - 0.012
a2 - - 3.30 - 0.130
a3 0 - 0.10 0 - 0.004
b 0.22 - 0.38 0.008 - 0.015
c 0.23 - 0.32 0.009 - 0.012
D(1)
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.
15.80 - 16.00 0.622 - 0.630
D1 9.40 - 9.80 0.370 - 0.385
E 13.90 - 14.50 0.547 - 0.570
e - 0.65 - - 0.0256 -
e3 - 11.05 - - 0.435 -
E1(1) 10.90 - 11.10 0.429 - 0.437
E2 - - 2.90 - 0.114
E3 5.80 - 6.20 0.228 - 0.244
E4 2.90 - 3.20 0.114 - 0.126
G 0 - 0.10 0 - 0.004
H 15.50 - 15.90 0.610 - 0.626
h - - 1.10 - 0.043
L 0.80 - 1.10 0.031 - 0.043
N 10° (max.)
S 8° (max.)
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DocID9455 Rev 5 31/33
L6229 Package information
33
12.2 SO24 package information
Figure 29. SO24 package outline
Table 11. SO24 package mechanical data
Symbol
Dimensions (mm) Dimensions (inch)
Min. Typ. Max. Min. Typ. Max.
A 2.35 - 2.65 0.093 - 0.104
A1 0.10 - 0.30 0.004 - 0.012
B 0.33 - 0.51 0.013 - 0.020
C 0.23 - 0.32 0.009 - 0.013
D(1)
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
15.20 - 15.60 0.598 - 0.614
E 7.40 - 7.60 0.291 - 0.299
e - 1.27 - - 0.050 -
H 10.0 - 10.65 0.394 - 0.419
h 0.25 - 0.75 0.010 - 0.030
L 0.40 - 1.27 0.016 - 0.050
k 0° (min.), 8° (max.)
ddd - - 0.10 - - 0.004
&
Revision history L6229
32/33 DocID9455 Rev 5
13 Revision history
Table 12. Document revision history
Date Revision Changes
September
2003 1 First Issue
January 2004 2 Migration from ST-Press dms to EDOCS.
October 2004 3 Updated the style graphic form.
06-Mar-2014 4
Updated Section : Features on page 1 (removed section number from: Features,
minor modifications).
Updated Section : Description on page 1 (removed section number from:
Description, removed “MultiPower-” from “MultiPower-BCD technology”).
Added Contents on page 2.
Updated Section 1: Block diagram on page 3 (added section title, renumbered
Figure 1: Block diagram ).
Added title to Section 2: Maximum ratings on page 4.
Added title to Section 3: Pin connections on page 6, renumbered Figure 2: Pin
connections (top view), renumbered note 1 below Figure 2.
Added title to Section 4: Electrical characteristics on page 8, renumbered notes 1
to 4 below Table 6, renumbered Figure 3 and Figure 4.
Renumbered Section 5: Circuit description on page 11, Section 5.1 and
Section 5.2. Removed “and C” from first sentence in Section 5.2. Added header to
Table 7. Renumbered Figure 5 to Figure 8.
Renumbered Section 6: PWM current control on page 13. Renumbered Figure 9 to
Figure 12. Numbered Equation 1 to Equation 4.
Renumbered Section 7: Slow decay mode on page 17 and Figure 13.
Renumbered Section 8: Decoding logic on page 18, Figure 14 and Figure 15.
Renumbered and renamed Section 9: Tachometer on page 20, renumbered
Figure 16 to Figure 18. Numbered Equation 5 and Equation 6.
Renumbered Section 10: Non-dissipative overcurrent detection and protection on
page 22, Figure 19 to Figure 22.
Renumbered Section 11: Application information on page 25, Section 11.1 and
Section 11.2. Added header to Table 9. Renumbered Figure 23 to Figure 28.
Updated Section 12: Package information on page 29 (added main title and
ECOPACK text. Added titles from Table 10: PowerSO36 package mechanical data
to Table 12: SO24 package mechanical data and from Figure 29: PowerSO36
package outline to Figure 31: SO24 package outline, reversed order of named
tables and figures. Removed 3D figures of packages. Replaced 0.200 by 0.020
inch of max. B value in Table 12).
Added cross-references throughout document.
Added section number and title to Section 13: Revision history.
Minor modifications throughout document.
04-Oct-2018 5
Removed PowerDIP24 package from the whole document.
Removed “Tj“ from Table 3 on page 4.
Minor modifications throughout document.
DocID9455 Rev 5 33/33
L6229
33
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