Datenblatt für TPS92692(-Q1) von Texas Instruments

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I TEXAS INSTRUMENTS

VCTRL

TPS92692-Q1

VIN

VREF

FLT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

GND

SLOPE

CSP

CSN

PDRV

RAMP

VIN LED +

LED í

CIN

CVREF

CSS

CDM

CCOMP

CIMON

RADJ2

RADJ1

RDIM2

RDIM1

RSLP

RIS

CVCC

ROV1

ROV2

COUT

CRAMP

RCS

QDIM

DDIM PAD

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS92692

TPS92692-Q1

SLVSDD9 –MARCH 2017

TPS92692, TPS92692-Q1 High Accuracy LED Controller With

Spread Spectrum Frequency Modulation

1 Features

1• Wide Input Voltage: 4.5 V to 65 V

• Better than ± 4% LED Current Accuracy over

–40°C to 150°C Junction Temperature Range

• Spread Spectrum Frequency Modulation for

Improved EMI

• Comprehensive Fault Protection Circuitry with

Current Monitor output and Open Drain Fault Flag

Indicator

• Internal Analog Voltage to PWM Duty Cycle

Generator for stand-alone Dimming Operation

• Compatible with Direct PWM Input with over

1000:1 Dimming Range

• Analog LED Current Adjust Input (IADJ) with over

15:1 Contrast Ratio

• Integrated P-Channel Driver to enable Series FET

Dimming and LED Protection

• TPS92692-Q1: Automotive Q100 Grade 1

Qualified

2 Applications

• TPS92692-Q1: Automotive Exterior Lighting

Applications

• Driver Monitoring Systems (DMS)

• LED General Lighting Applications

• Exit Signs and Emergency Lighting

3 Description

The TPS92692 and TPS92692-Q1 are high accuracy

peak current mode based controllers designed to

support step-up/down LED driver topologies. The

device incorporates a rail-to-rail current amplifier to

measure LED current and spread spectrum frequency

modulation technique for improved EMI performance.

This high performance LED controller can

independently modulate LED current using either

analog or PWM dimming techniques. Linear analog

dimming response with over 15:1 range is obtained

by varying the voltage across the high impedance

analog adjust (IADJ) input. PWM dimming of LED

current is achieved by directly modulating the

DIM/PWM input pin with the desired duty cycle or by

enabling the internal PWM generator circuit. The

PWM generator translates the DC voltage at

DIM/PWM pin to corresponding duty cycle by

comparing it to the internal triangle wave generator.

The optional PDRV gate driver output can be used to

drive an external P-Channel series MOSFET.

The TPS92692 and TPS92692-Q1 devices support

continuous LED status check through the current

monitor (IMON) output. The devices also include an

open drain fault indicator output to indicate LED

overcurrent, output overvoltage and output

undervoltage conditions.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS92692-Q1 HTSSOP (20) 5.10 mm × 6.60 mm

TPS92692

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Typical Boost LED Driver

l TEXAS INSTRUMENTS

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Product Folder Links: TPS92692 TPS92692-Q1

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Typical Boost LED Driver...................................... 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 22

9 Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Applications ................................................ 34

10 Power Supply Recommendations ..................... 46

11 Layout................................................................... 47

11.1 Layout Guidelines ................................................. 47

11.2 Layout Example .................................................... 48

12 Device and Documentation Support ................. 49

12.1 Related Links ........................................................ 49

12.2 Community Resources.......................................... 49

12.3 Trademarks........................................................... 49

12.4 Electrostatic Discharge Caution............................ 49

12.5 Glossary................................................................ 49

13 Mechanical, Packaging, and Orderable

Information ........................................................... 49

5 Revision History

DATE REVISION NOTES

March 2017 * Initial release.

*9 TEXAS INSTRUMENTS

Thermal

Pad

VIN

VREF

FLT

COMP

IMON

VCC

GATE

GND

SLOPE

CSP

CSN

9IADJ

10DIM/PWM

PDRV

RAMP

TPS92692

TPS92692-Q1

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SLVSDD9 –MARCH 2017

Product Folder Links: TPS92692 TPS92692-Q1

6 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP with PowerPAD™

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

COMP 7 I/O Transconductance error amplifier output. Connect compensation network to achieve desired closed-

loop response.

CSN 13 I Current sense amplifier negative input (–). Connect directly to the negative node of LED current

sense resistor, RCS.

CSP 14 I Current sense amplifier positive input (+). Connect directly to the positive node of LED current

sense resistor, RCS.

DIM/PWM 10 I

External analog to PWM dimming command or direct PWM dimming input. The external analog

dimming command between 1 V and 3 V is compared to the internal PWM generator triangle

waveform to set LED current duty cycle between 0% and 100%. With PWM generator disabled, a

direct PWM dimming command can be applied to control the LED current duty cycle and frequency.

The analog or PWM command is used to generate an internal PWM signal that controls the GATE

and PDRV outputs. Setting the internal PWM signal to logic level low, turns off switching, idles the

oscillator, disconnects the COMP pin, and sets PDRV to VCSP. Connect to VREF when not used for

PWM dimming.

DM 5 I/O Triangle wave spread spectrum modulation frequency, fm, programming pin. Connect a capacitor to

GND to set the spread spectrum modulating frequency. Connect directly to GND to disable spread

spectrum modulation of switching frequency.

FLT 3 O Open-drain fault indicator. Connect to VREF with a resistor to create active low fault signal output.

Internal LED short circuit protection and auto-restart timer can enabled by directly connecting the

pin to SS input.

GATE 19 O N-channel MOSFET gate driver output. Connect to gate of external main switching N-channel

MOSFET.

GND 17 — Analog and Power ground connection pin. Connect to circuit ground to complete return path.

IADJ 9 I

LED current reference input. Connect this pin to VCC with a 100-kΩseries resistor to set the

internal reference voltage to 2.42 V and the current sense threshold, V(CSP-CSN) to 170.7 mV. The

pin can be modulated by an external voltage source from 140 mV to 2.25 V to implement analog

dimming.

IMON 8 O LED current report pin. The LED current sensed by CSP/CSN input is reported as VIMON = 14 × ILED

× RCS. Bypass with a 1-nF ceramic capacitor connected to GND.

IS 18 I Switch current sense input. Connect to the switch sense resistor, RIS to set the switch current limit

threshold based on the internal 250 mV reference.

OV 15 I Output voltage input. Connect a resistor divider from output voltage to GND to set output

overvoltage and under-voltage protection thresholds.

PDRV 12 O Series dimming P-channel FET gate driver output. Connect to gate of external P-channel MOSFET

to implement series FET PWM dimming and fault disconnect.

l TEXAS INSTRUMENTS

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SLVSDD9 –MARCH 2017

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Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

RAMP 11 I/O

Programming input for internal PWM generator. Connect a capacitor to GND to set the triangle

wave frequency for PWM generator circuit. Connect a 249-kΩresistor to GND to disable the PWM

generator and to set a fixed reference for direct external PWM dimming input. Do not allow this pin

to float.

RT 6 I/O Oscillator frequency programming pin. Connect a resistor to GND to set the switching frequency.

The internal oscillator can be synchronized by coupling an external clock pulse through a series

capacitor with a value of 100 nF.

SLOPE 16 I/O Slope compensation input. Connect a resistor to GND to set the desired slope compensation ramp

based on inductor value, input and output voltages.

SS 4 I/O Soft-start programming pin. Connect a capacitor to GND to extend the start-up time. Switching can

be disabled by shorting this pin to GND.

VCC 20 — VCC (7.5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value

between 2.2-µF and 4.7-µF). Locate close to the controller.

VIN 1 — Input supply for the internal regulators. Bypass with a low-pass filter using a series 10-Ωresistor

and 10- nF capacitor connected to GND. Locate the capacitor close to the controller.

VREF 2 — VREF (5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value

between 2.2-µF and 4.7-µF) located close to the controller.

Thermal Pad — The GND pin must be connected to the exposed thermal pad for proper operation. This PowerPAD

must be connected to PCB ground plane using multiple vias for good thermal performance.

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted

(3) Continuous sustaining voltage

(4) All output pins are not specified to have an external voltage applied.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Input voltage

VIN, CSP, CSN –0.3 65 V

DIM/PWM –0.3 14 V

IS, RT, FLT –0.3 8.8 V

OV, SS, RAMP, DM, SLOPE, VREF, IADJ –0.3 5.5 V

CSP to CSN(3) –0.3 0.3 V

Output voltage(4)

VCC, GATE –0.3 8.8 V

PDRV VCSP – 8.8 VCSP V

COMP –0.3 5.0 V

Source current

IMON — 100 µA

GATE (pulsed < 20 ns) — 500 mA

PDRV (pulsed < 10 µs) — 50 mA

Sink current GATE (pulsed < 20 ns) — 500 mA

PDRV (pulsed < 10 µs) — 50 mA

Operating junction temperature, TJ–40 150 °C

Storage temperature, Tstg 165 °C

l TEXAS INSTRUMENTS

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SLVSDD9 –MARCH 2017

Product Folder Links: TPS92692 TPS92692-Q1

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

TPS92692-Q1 IN PWP (HTSSOP) PACKAGE

V(ESD) Electrostatic

discharge

Human-body model (HBM), per AEC Q100-002, all pins(1) ±2000

Charged-device model (CDM), per AEC Q100-011 All pins except 1, 10, 11, and 20 ±500

Pins 1, 10, 11, and 20 ±750

TPS92692 IN PWP (HTSSOP) PACKAGE

V(ESD) Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(3) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VIN Supply input voltage 6.5 14 65 V

VIN, crank Supply input, battery crank voltage 4.5 V

VCSP, VCSN Current sense common mode 6.5 60 V

ƒSW Switching frequency 80 800 kHz

ƒmSpread spectrum modulation frequency 0.1 12 kHz

fRAMP Internal PWM ramp generator frequency 100 2000 Hz

VIADJ Current reference voltage 0.14 VIADJ(CLAMP) V

TAOperating ambient temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

TPS92692 TPS92692-Q1

UNITPWP (HTSSOP) PWP (HTSSOP)

20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 40.8 40.8 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 26.1 26.1 °C/W

RθJB Junction-to-board thermal resistance 22.2 22.2 °C/W

ψJT Junction-to-top characterization parameter 0.8 0.8 °C/W

ψJB Junction-to-board characterization parameter 22.0 22.0 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 2.3 °C/W

l TEXAS INSTRUMENTS

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SLVSDD9 –MARCH 2017

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Product Folder Links: TPS92692 TPS92692-Q1

(1) All voltages are with respect to GND unless otherwise noted

7.5 Electrical Characteristics

–40°C ≤TJ≤150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,

CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT VOLTAGE (VIN)

IIN(STBY) Input stand-by current VPWM = 0 V 1.8 2.5 mA

IIN(SW) Input switching current VCC = 7.5 V, CGATE = 1 nF 5.1 6.6 mA

BIAS SUPPLY (VCC)

VCC(REG) Regulation voltage No load 7.0 7.5 8.0 V

VCC(UVLO) Supply undervoltage protection

VCC rising threshold, VIN = 8 V 4.5 4.9 V

VCC falling threshold, VIN = 8 V 3.7 4.1 V

Hysteresis 400 mV

ICC(LIMIT) Supply current limit VCC = 0 V 30 36 46 mA

VDO LDO dropout voltage ICC = 20 mA, VIN = 5 V 300 mV

REFERENCE VOLTAGE (VREF)

VREF Reference voltage No load 4.77 4.96 5.15 V

IREF(LIMIT) Current limit VREF = 0 V 30 36 46 mA

OSCILLATOR (RT)

ƒSW Switching frequency RT= 40 kΩ175 200 225 kHz

RT= 20 kΩ341 390 439 kHz

VRT RT output voltage 1 V

VSYNC SYNC rising threshold VRT rising 2.5 3.1 V

SYNC falling threshold VRT falling 1.8 2 V

tSYNC(MIN) Minimum SYNC clock pulse width 100 ns

SPREAD SPECTRUM FREQUENCY MODULATION (DM)

IDM

Triangle wave generator sink current 10 µA

Triangle wave generator source

current 10 µA

VDM(TR) Triangle wave voltage peak (High) 1.15 V

Triangle wave voltage valley (Low) 850 mV

VDM(EN) Spread spectrum modulation enable

threshold 700 mV

VDM(CLAMP) Internal clamp voltage VPWM = 0 V, RRAMP = 200 kΩ1.25 V

GATE DRIVER (GATE)

RGH Gate driver high side resistance IGATE = –10 mA 5.4 11.2 Ω

RGL Gate driver low side resistance IGATE = 10 mA 4.3 10.5 Ω

CURRENT SENSE (IS)

VIS(LIMIT) Current limit threshold VDIM/PWM = 5 V, RRAMP = 249 kΩ230.6 250 270 mV

VDIM/PWM = 0 V, RRAMP = 249 kΩ665 700 735 mV

tIS(BLANK) Leading edge blanking time 88 118 158 ns

tIS(FAULT) Current limit fault time 35 µs

tILMT(DLY) IS to GATE propagation delay VIS pulsed from 0 V to 1 V 78 ns

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Electrical Characteristics (continued)

–40°C ≤TJ≤150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,

CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PWM COMPARATOR AND SLOPE COMPENSATION (SLOPE)

DMAX Maximum duty cycle 90 %

VSLOPE Adaptive slope compensation VCSP = 24 V 410 mV

VSLOPE(MIN) Minimum slope compensation output

voltage VCSP = 0 V 72 mV

VLV IS to COMP level shift voltage No slope compensation added 1.42 1.60 1.82 V

ILV IS level shift bias current No slope compensation added 17 µA

CURRENT SENSE AMPLIFIER (CSP, CSN)

V(CSP-CSN) Current sense thresholds VCSP = 14 V, VIADJ = 3 V 163.4 170.7 177.6 mV

VCSP = 14 V, VIADJ = 1.4 V 95.83 100.5 103.85 mV

CS(BW) Current sense unity gain bandwidth 500 kHz

GCS Current sense amplifier gain G = VIADJ/V(CSP-CSN) 14

K(OCP) Ratio of over-current detection

threshold to analog adjust voltage K(OCP) = V(OCP-THR)/VIADJ 1.46 1.5 1.61

ICSP(BIAS) CSP bias current VCSN = 14.1 V, VCSP = 14 V 107 µA

ICSN(BIAS) CSN bias current VCSN = 14.1 V, VCSP = 14 V 110 µA

FAULT INDICATOR (FLT)

R(FLT) Open-drain pull down resistance 241 Ω

t(FAULT_TMR) Fault timer 24 36 48 ms

CURRENT MONITOR (IMON)

IIMON(SRC) IMON source current V(CSP-CSN) = 150 mV,

VIMON = 0 V 144 µA

VIMON(CLP) IMON output voltage clamp 3.2 3.7 4.2 V

VIMON(OS) IMON buffer offset voltage –7.2 0 8.5 mV

ANALOG ADJUST (IADJ)

VIADJ(CLP) IADJ internal clamp voltage IIADJ = 1 µA 2.29 2.40 2.55 V

IIADJ(BIAS) IADJ input bias current VIADJ < 2.2 V 10.5 nA

RIADJ(LMT) IADJ current limiting series resistor VIADJ > 2.6 V 12 kΩ

ERROR AMPLIFIER (COMP)

gMTransconductance 121 µA/V

ICOMP(SRC) COMP current source capacity VIADJ = 1.4 V, V(CSP-CSN) = 0 V 130 µA

ICOMP(SINK) COMP current sink capacity VIADJ = 0 V, V(CSP-CSN) = 0.1 V 130 µA

EA(BW) Error amplifier bandwidth Gain = –3 dB 5 MHz

VCOMP(RST) COMP pin reset voltage 100 mV

RCOMP(DCH) COMP discharge FET resistance 246 Ω

SOFT-START (SS)

ISS Soft-start source current 7 10 12.8 µA

VSS(UVP_EN) Soft-start voltage threshold to enable

output under-voltage protection 2.4 V

VSS(RST) Soft-start pin reset voltage 50 mV

RSS(DCH) SS discharge FET resistance 240 Ω

OUTPUT VOLTAGE INPUT (OV)

VOVP(THR) Overvoltage protection threshold 1.195 1.228 1.262 V

VUVP(THR) Undervoltage protection threshold 81.7 100 115.1 mV

t(UVP-BLANK) Undervoltage protection blanking

period 4 µs

IOVP(HYS) OVP hysteresis current 12 20 27.5 µA

l TEXAS INSTRUMENTS

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SLVSDD9 –MARCH 2017

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Product Folder Links: TPS92692 TPS92692-Q1

Electrical Characteristics (continued)

–40°C ≤TJ≤150°C, VIN = 14 V, VIADJ = 2.1 V, VRAMP = 500 mV, VDIM/PWM = 3 V, VOV = 500 mV, CVCC = 1 µF, CVREF = 1 µF,

CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL PWM RAMP GENERATOR (RAMP)

IRAMP Ramp generator source current 7.75 10 12.73 µA

Ramp generator sink current 8.24 10 12.41 µA

VRAMP Ramp signal peak (high) 3 V

Ramp signal valley (low) 1 V

PWM INPUT (DIM/PWM)

VPWM(HIGH) Schmitt trigger logic level (high

threshold) VRAMP = 2.0 V 2.0 2.2 V

VPWM(LOW) Schmitt trigger logic level (low

threshold) VRAMP = 2.0 V 1.8 2.0 V

RPWM(PD) PWM pull-down resistance 10 MΩ

tDLY(RISE) PWM rising to PDRV delay CPDRV = 1 nF 294 ns

tDLY(FALL) PWM falling to PDRV delay CPDRV = 1 nF 326 ns

SERIES P-CHANNEL PWM FET GATE DRIVE OUTPUT (PDRV)

VPDRV(OFF) P-channel gate driver off-state voltage VCSP = 14 V 14 V

VPDRV(ON) P-channel gate driver on-state voltage VCSP = 14 V 7.4 V

IPDRV(SRC) PDRV sink current Pulsed 50 mA

RPDRV(L) PDRV driver pull up resistance 82 Ω

THERMAL SHUTDOWN

TSD Thermal shutdown temperature 175 °C

TSD(HYS) Thermal shutdown hysteresis 25 °C

l TEXAS INSTRUMENTS 754 A 975 600 485 mo

Junction Temperature (oC)

VCC Undervoltage Lockout Thresholds (V)

-40 -20 0 20 40 60 80 100 120 140 160

3.85

3.95

4.05

4.15

4.25

4.35

4.45

4.55

4.65

4.75

4.85

D004

Rising

Falling

Frequency (kHz)

RT (k:)

50 150 250 350 450 550 650 750800

100

D005

Junction Temperature (oC)

VCC Dropout Voltage (mV)

-40 -20 0 20 40 60 80 100 120 140 160

100

200

300

400

500

600

D002

Junction Temperature (oC)

VCC Current Limit (mA)

-40 -20 0 20 40 60 80 100 120 140 160

D003

Junction Temperature (oC)

VCC Regulation Voltage (V)

-40 -20 0 20 40 60 80 100 120 140 160

7.46

7.47

7.48

7.49

7.5

7.51

7.52

7.53

7.54

D001

Junction Temperature (oC)

Reference Voltage (V)

-40 -20 0 20 40 60 80 100 120 140 160

4.935

4.94

4.945

4.95

4.955

4.96

4.965

4.97

4.975

D020

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SLVSDD9 –MARCH 2017

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7.6 Typical Characteristics

TA= 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, VPWM = 5 V, no load on GATE

and PDRV (unless otherwise noted)

Figure 1. VCC Regulation Voltage vs Junction Temperature Figure 2. VREF Reference Voltage vs Junction Temperature

VIN = 5 V, IVCC= 20 mA

Figure 3. VCC Dropout Voltage vs Junction Temperature

Figure 4. VCC Current Limit vs Junction Temperature

Figure 5. VCC UVLO Threshold vs Junction Temperature Figure 6. Timing Resistance (RT) vs Switching Frequency

l TEXAS INSTRUMENTS 398 90 3 /’/// / / / 251 135 / / / \ / / / // 171 2 174 \ \\\ \ l \\ / / \\ /

VCSP (V)

V(CSP-CSN) Threshold (mV)

0 5 10 15 20 25 30 35 40 45 50 55 60 65

169.8

170

170.2

170.4

170.6

170.8

171

171.2

D010

Junction Temperature (oC)

V(CSP-CSN) Threshold (mV)

-40 -20 0 20 40 60 80 100 120 140 160

168

169

170

171

172

173

174

D011

Junction Temperature (oC)

IS Current Limit Threshold (mV)

-40 -20 0 20 40 60 80 100 120 140 160

248.5

249

249.5

250

250.5

251

D008

Junction Temperature (oC)

Leading Edge Blanking Period (ns)

-40 -20 0 20 40 60 80 100 120 140 160

105

110

115

120

125

130

135

D009

Junction Temperature (oC)

Switching Frequency (kHz)

-40 -20 0 20 40 60 80 100 120 140 160

382

384

386

388

390

392

394

396

398

D006

Junction Temperature (oC)

Maximum Duty Cycle (%)

-40 -20 0 20 40 60 80 100 120 140 160

89.7

89.8

89.9

90.1

90.2

90.3

D007

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Typical Characteristics (continued)

TA= 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, VPWM = 5 V, no load on GATE

and PDRV (unless otherwise noted)

RT= 20 kΩ

Figure 7. Switching Frequency vs Junction Temperature

Figure 8. Maximum Duty Cycle vs Junction Temperature

Figure 9. Current Limit Threshold vs Junction Temperature Figure 10. Leading Edge Blanking Period vs Junction

Temperature

VIADJ> 2.6 V

Figure 11. V(CSP-CSN) Threshold vs VCSP Voltage

VIADJ> 2.6 V

Figure 12. V(CSP-CSN) Threshold vs Junction Temperature

l TEXAS INSTRUMENTS 1m 125 \\ 37s 200 2 403

VIADJ (V)

V(CSP-CSN) Threshold (mV)

0 0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 2.52 2.8 3

100

120

140

160

180

200

D016

Junction Temperature (oC)

IADJ Voltage Clamp (V)

-40 -20 0 20 40 60 80 100 120 140 160

2.395

2.396

2.397

2.398

2.399

2.4

2.401

2.402

2.403

D017

V(CSP-CSN) (mV)

VIMON (V)

0 30 60 90 120 150 180 210 240 270 300

0.5

1.5

2.5

3.5

D014

Junction Temperaure (oC)

IMON Output Voltage Clamp (V)

-40 -20 0 20 40 60 80 100 120 140 160

3.64

3.66

3.68

3.7

3.72

3.74

3.76

D015

Junction Temperature (oC)

V(CSP-CSN) Threshold (mV)

-40 -20 0 20 40 60 80 100 120 140 160

99.25

99.5

99.75

100

100.25

100.5

100.75

101

D0012

Junction Temperature (oC)

Bias Current (PA)

-40 -20 0 20 40 60 80 100 120 140 160

100

105

110

115

120

125

D013

CSP

CSN

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Typical Characteristics (continued)

TA= 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, VPWM = 5 V, no load on GATE

and PDRV (unless otherwise noted)

VIADJ= 1.4 V

Figure 13. V(CSP-CSN) Threshold vs Junction Temperature

VCSP= VCSN = 14 V

Figure 14. CSP/CSN Input Bias Current vs Junction

Temperature

Figure 15. VIMON vs V(CSP-CSN) Figure 16. VIMON(CLP) vs Junction Temperature

Figure 17. V(CSP-CSN) Threshold vs VIADJ Figure 18. VIADJ Voltage Clamp vs Junction Temperature

l TEXAS INSTRUMENTS 1 232

Junction Temperature (oC)

OVP Detection Threshold (V)

-40 -20 0 20 40 60 80 100 120 140 160

1.222

1.223

1.224

1.225

1.226

1.227

1.228

1.229

1.23

1.231

1.232

D018

Junction Temperature (oC)

OVP Hysteresis Current (PA)

-40 -20 0 20 40 60 80 100 120 140 160

19.2

19.4

19.6

19.8

20.2

20.4

20.6

20.8

D019

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Typical Characteristics (continued)

TA= 25°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT= 20 kΩ, VPWM = 5 V, no load on GATE

and PDRV (unless otherwise noted)

Figure 19. OVP Detection Threshold vs Junction

Temperature Figure 20. OVP Hysteresis Current vs Junction Temperature

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8 Detailed Description

8.1 Overview

The TPS92692 and TPS92692-Q1 devices feature all of the functions necessary to implement a compact LED

driver based on step-up or step-down power converter topologies. The devices implement a fixed-frequency,

peak current mode control technique to achieve constant output current and fast transient response. The

integrated low offset, rail-to-rail current sense amplifier provides the flexibility required to power a single string

consisting of 1 to 20 series connected LEDs while maintaining better than 4% current accuracy over the

operating temperature range. The LED current regulation threshold is set by the analog adjust input, IADJ and

can be externally programmed to implement analog dimming with over 15:1 linear dimming range. The high

impedance IADJ input simplifies LED current binning and thermal protection.

The TPS92692 and TPS92692-Q1 devices incorporate an internal PWM generator that can be programmed to

implement pulse width modulation (PWM) dimming of LED current. The PWM duty cycle can be varied from 0%

to 100% by modulating the analog voltage on DIM/PWM input from 1 V to 3 V. The PWM dimming frequency is

externally programmable and is set by the capacitor connected to RAMP input. As an alternative, the TPS92692

and TPS92692-Q1 devices can also be configured to implement direct PWM dimming based on the duty cycle of

external PWM signal by connecting a 249-kΩresistor across RAMP pin and GND. The internal PWM signal

controls the GATE and PDRV outputs which control the external n-channel switching FET and p-channel

dimming FET connected in series with LED string, respectively.

The current monitor output, IMON, reports the instantaneous status of LED current measured by the rail-to-rail

current sense amplifier. This feature indicates instantaneous current as a result of LED short circuit and cable

harness failure, independent of LED driver topology. An open-drain fault indicator is also provided to report faults

including cycle-by-cycle current limit, output overvoltage, and output undervoltage conditions. LED driver

protection with auto-restart (hiccup) mode is enabled by connecting the fault pin (FLT) to the SS pin. Other

protection features include VCC undervoltage protection and thermal shutdown. A remote signal can force the

device in to shutdown by pulling down on the SS pin.

Standby

7.5 V LDO

Regulator

UVLO

(4.1 V)

Thermal

Limit

Internal

References

Clock

Oscillator

Max Duty

10 A

LEB

1.23 V

36 ms

Timer

10 A

20 A

Fault

CSP

VIN

DIM/

PWM

COMP

CSP

CSN

IMON

IADJ

GND

GATE

VCC

PDRV

Standby

8 k

Fault

PWM

Comp

3.7 V

2.4 V

12 k

Fault

Reset

Logic 50 mV

100 mV

Current Sense

Amplifier

Gain = 14

VREF

5 V LDO

Regulator

Slope

Generator SLOPE

Triangle

Wave

Generator

RAMP

Spread

Spectrum

Modulator

7 V

100 A

Overcurrent

Detector

Fault

700 mV

250 mV

PWM

FLT

3 V

1 V VIN CSP

1.4 V

Overvoltage

Fault

100 mV

Undervoltage

Fault

Undervoltage

Fault

2.4 V SS_DONE

SS_DONE

35 …s

Timer

PWM

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8.2 Functional Block Diagram

l TEXAS INSTRUMENTS SW IO \ E

Oscillator

CSYNC RT

Clock

fSYNC

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1.432 10

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8.3 Feature Description

8.3.1 Internal Regulator and Undervoltage Lockout (UVLO)

The device incorporates a 65-V input voltage rated linear regulators to generate the 7.5 V (typ) VCC bias supply,

the 5 V (typ) VREF reference supply and other internal reference voltages. The device monitors the VCC output to

implement UVLO protection. Operation is enabled when VCC exceeds the 4.5-V (typ) threshold and is disabled

when VCC drops below the 4.1-V (typ) threshold. The UVLO comparator provides 400 mV of hysteresis to avoid

chatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. An internal current

limit circuit is implemented to protect the device during VCC pin short-circuit conditions. The VCC supply powers

the internal circuitry and the N-channel gate driver output, GATE. Place a bypass capacitor in the range of 2.2 µF

to 4.7 µF across the VCC output and GND to ensure proper operation. The regulator operates in dropout when

input voltage VIN falls below 7.5 V forcing VCC to be lower than VIN by 300 mV for a 20-mA supply current. The

VCC is a regulated output of the internal regulator and is not recommended to be driven from an external power

supply.

The VREF supply is internally used to generate voltage thresholds for the RAMP generator circuit and to power

some digital circuits. This supply can be used in conjunction with a resistor divider to set voltage levels for the

IADJ pin and DIM/PWM pin to set LED current and PWM dimming duty cycle. It can also be used to bias

external circuitry requiring a reference supply. The supply current is internally limited to protect the device from

output overload and short-circuit conditions. Place a bypass capacitor in the range of 2.2 µF to 4.7 µF across the

VREF output to GND to ensure proper operation.

The TPS92692 and TPS92692-Q1 devices incorporate features that simplify compliance with the CISPR and

automotive EMI requirements. The devices have optional spread spectrum frequency modulation circuit that can

be externally configured to reduce peak and average conducted and radiated EMI. The internal programmable

oscillator has a range of 80 kHz to 800 kHz and can be tuned based on the EMI requirements. The devices are

available in HTSSOP-20 package with an exposed pad to aid in thermal dissipation.

8.3.2 Oscillator

The switching frequency is programmable by a single external resistor connected between the RT pin and GND.

To set a desired frequency, ƒSW (Hz), the resistor value can be calculated from Equation 1.

(1)

Figure 6 shows a graph of switching frequency versus resistance, RT. TI recommends a switching frequency

setting between 80 kHz and 700 kHz for optimal performance over input and output voltage operating range and

for best efficiency. Operation at higher switching frequencies requires careful selection of N-channel MOSFET

characteristics as well as detailed analysis of switching losses.

Figure 21. Oscillator Synchronization Through AC Coupling

The internal oscillator can be synchronized by AC coupling an external clock pulse to RT pin as shown in

Figure 21. The positive going synchronization clock at the RT pin must exceed the RT sync threshold and the

negative going synchronization clock at the RT pin must exceed the RT sync falling threshold to trip the internal

synchronization pulse detector. TI recommends that the frequency of the external synchronization pulse is within

±20% of the internal oscillator frequency programmed by the RTresistor. TI recommends a minimum coupling

capacitor of 100 nF and a typical pulse width of 100 ns for proper synchronization. In the case where external

synchronization clock is lost the internal oscillator takes control of the switching rate based on the RTresistor to

maintain output current regulation. The RTresistor is always required whether the oscillator is free running or

externally synchronized.

l TEXAS INSTRUMENTS MOD

GATE

GND

CVCC

VCC

GATE_IN

0.85 V

1.15 V

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1 V

1.15 V

0.85 V

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u u

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Feature Description (continued)

8.3.3 Spread Spectrum Frequency Modulation

The TPS92692 and TPS92692-Q1 devices provide a frequency dithering option that is enabled by connecting a

capacitor from the DM pin to GND. A triangle waveform centered at 1 V is generated across the CDM capacitor.

The triangle waveform modulates the oscillator frequency by ± 15% of the nominal frequency set by an external

timing resistor, RT. The CDM capacitance value sets the rate of the low frequency modulation. To achieve

maximum attenuation in average EMI scan set modulation frequency ranging from 100 Hz to 1.2 kHz. The low

modulating frequency has little impact on the quasi-peak EMI scan. Set the modulation frequency to 10 KHz or

higher to achieve attenuation for quasi-peak EMI measurements. The modulation frequency higher than the

receiver resolution bandwidth (RBW) of 9 kHz only impacts the quasi-peak EMI scan and has little impact on the

average measurement. The device simplifies EMI compliance by providing the means to tune the modulation

frequency based on measured EMI signature. Equation 2 calculates the CDM capacitance required to set the

modulation frequency, fMOD (Hz).

(2)

Figure 22. Frequency Dither Operation

Connect the DM pin to GND to disable frequency dither circuit operation. Internal frequency dithering is not

supported when the devices are synchronized based on an external clock signal.

8.3.4 Gate Driver

The TPS92692 and TPS92692-Q1 devices contain a N-channel gate driver that switches the output VGATE

between VCC and GND. A peak source and sink current of 500 mA allows controlled slew-rate of the MOSFET

gate and drain node voltages, limiting the conducted and radiated EMI generated by switching.

Figure 23. Push-Pull N-Channel Gate Driver Circuit

‘5‘ TEXAS INSTRUMENTS SW

CFDM

RFS

RCS

CFCM

CSP

CSN

Common Mode

Filter Capacitors

Differential Mode

Filter Capacitor

CC(GATE) G SW

I Q f u

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Feature Description (continued)

The gate driver supply current ICC(GATE) depends on the total gate drive charge (QG) of the MOSFET and the

operating frequency of the converter, ƒSW, . Choose a MOSFET with a low gate charge

specification to limit the junction temperature rise and switch transition losses.

It is important to consider the MOSFET threshold voltage when operating in the dropout region when the input

voltage, VIN, is below the VCC regulation level. TI recommends a logic level device with a threshold voltage below

5 V when the device is required to operate at an input voltage less than 7 V.

8.3.5 Rail-to-Rail Current Sense Amplifier

The internal rail-to-rail current sense amplifier measures the average LED current based on the differential

voltage drop between the CSP and CSN inputs over a common mode range of 0 V to 65 V. The differential

voltage, V(CSP-CSN), is amplified by a voltage-gain factor of 14 and is connected to the negative input of the

transconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative input

offset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and

the transconductance error amplifier offset voltage) to less than 5 mV over the recommended common-mode

voltage, and temperature range.

Figure 24. Current Sense Amplifier Input Filter Options

An optional common-mode or differential mode low-pass filter implementation, as shown in Figure 24, can be

used to smooth out the effects of large output current ripple and switching current spikes caused by diode

reverse recovery. TI recommends a filter resistance in the range of 10 Ωto 100 Ωto limit the additional offset

caused by amplifier bias current mismatch to achieve the best accuracy and line regulation.

8.3.6 Transconductance Error Amplifier

The internal transconductance amplifier generates an error signal proportional to the difference between the LED

current sense feedback voltage and the external IADJ input voltage. The output of the error amplifier is

connected to an external compensation network to achieve closed-loop LED current regulation. In most LED

driver applications a simple integral compensation circuit consisting of a capacitor connected from COMP output

to GND provides a stable response over wide range of operating conditions. TI recommends a capacitor value

between 10 nF and 100 nF as a good starting point. To achieve higher closed-loop bandwidth a proportional-

integral compensator, consisting of a series resistor and a capacitor network connected across the COMP output

and GND, is required. Based on the converter topology, tune the compensation network to achieve a minimum of

60° of phase margin and 10 dB of gain margin. The Application and Implementation section includes a

summarized detailed design procedure.

l TEXAS INSTRUMENTS SW SLP

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250 mV

35 …s

TIMER

PWM

150 ns

LEB

ILIM

Comparator

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Feature Description (continued)

8.3.7 Switch Current Sense

The IS input pin monitors the main MOSFET current to implement peak current mode control. The GATE output

duty cycle is derived by comparing the peak switch current, measured by the RIS resistor, to the internal COMP

voltage threshold. An internal slope signal, VSL, generated by slope compensation circuit is added to the

measured sense voltage, VIS, to prevent subharmonic oscillations for duty cycles greater than 50%. An internal

blanking circuit prevents MOSFET switching current spike propagation and premature termination of duty cycle

by internally shunting the IS input for 150 ns after the beginning of the new switching period. For additional noise

suppression connect an external low-pass RC filter with resistor values ranging from 100 Ωto 500 Ωand a 1000

pF capacitor. The external RC filter ensures proper operation when operating in the dropout region (VIN less than

7 V).

Figure 25. Switch Current Limit Circuit

Cycle-by-cycle current limit is accomplished by a redundant internal comparator. The current limit threshold is set

based on the status of internal PWM signal. The current limit threshold is set to 250 mV (typ) when PWM signal

is high and to 700 mV (typ) when PWM signal is low. The transition between the two thresholds work in

conjunction with slope compensation and the error amplifier circuit to allow for higher inductor current

immediately after the PWM transition and to improve LED current transient response during PWM dimming.

Refer to the DIM/PWM Input section for details on PWM Dimming operation.

The device immediately terminates the GATE and PDRV output when the IS input voltage, VIS, exceeds the

threshold value. Upon a current limit event, the SS and COMP pin are internally grounded to reset the state of

the controller. The GATE output is enabled after the expiration of the 35-µs internal fault timer and a new start-up

sequence is initiated through the SS pin. Equation 3 calculates the peak inductor current in the current limit.

(3)

8.3.8 Slope Compensation

Peak current mode based regulators are subject to sub-harmonic oscillations for duty cycle greater than 50%. To

avoid this instability problem, the control scheme is modified by the addition of an artificial ramp to the sensed

switch current waveform. The slope of the artificial ramp required is dependent on the input voltage, VIN, output

voltage, VO, inductor, L, and switch current sense resistor, RIS. The devices incorporate an adaptive slope

compensation technique that modifies the slope of the artificial ramp generated based on the input voltage, VIN

and output voltage measured at CSP pin, VCSP, thus greatly simplifying the design for common LED driver

topologies, such as boost, buck-boost, and boost-to-battery. The magnitude of the internal ramp signal can be

calculated as follows:

where

• D is the converter duty cycle (4)

l TEXAS INSTRUMENTS fD Hz) D \ M 1 DP

DIM

PWM(INT) V 1

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DIM DIM

10 A

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Feature Description (continued)

The resistor, RSLOPE provides the flexibility to set the slope of the internal artificial ramp based on the inductance

value, L and the LED driver topology. The Application and Implementation section includes detailed calculations

for the resistor, RSLOPE, based on the LED driver topology. The SLOPE pin cannot be left floating.

8.3.9 Analog Adjust Input

The voltage across the LED current sense resistor, V(CSP–CSN), is regulated to the analog adjust input voltage,

VIADJ, scaled by the current sense amplifier voltage gain of 14. The LED current can be linearly adjusted by

varying the voltage on IADJ pin from 140 mV to 2.25 V using either a resistor divider from VREF or a voltage

source. The IADJ pin can be connected to VREF through an external resistor to set LED current based on the 2.4-

V internal reference voltage. This device offers different methods to set the IADJ voltage. Figure 27 shows how

the IADJ input can be used in conjunction with a NTC resistor to implement thermal foldback protection. A PWM

signal in conjunction with first- or second-order low-pass filter can be used to program the IADJ voltage as shown

in Figure 28).

Figure 26. Static Reference

Setting Resistor Divider From

VCC

Figure 27. Thermal Fold-back

Circuit Using External NTC

Resistor

Figure 28. Analog Dimming

Achieved By Low-pass Filtering

External PWM Signal

8.3.10 DIM/PWM Input

The TPS92692 and TPS92692-Q1 devices incorporate a PWM generator circuit to facilitate analog voltage to

PWM duty cycle translation. The dimming frequency is set by connecting a capacitor from RAMP pin to GND.

The dimming frequency, fDIM, can be calculated as follows:

(5)

The internal PWM signal can be varied from 0% to 100% by setting the DIM/PWM pin voltage between 1 V and 3

V. Equation 6 describes the relationship between DIM/PWM pin voltage, VDIM and internal PWM duty cycle,

DPWM(INT).

(6)

For improved dimming accuracy, use the VREF pin and a resistor divider to set the DIM/PWM pin voltage, VDIM,

and the corresponding duty cycle. The device can be configured to step the duty cycle between 100% and the

programmed value by diode connecting the external control signal, VCTRL, to the DIM/PWM pin, as shown in

Figure 29. The external control signal, of amplitude 3-V, is usually generated by the command module and is

based on the light output required by the application.

Triangle

Wave

Generator

5V LDO

Regulator

VREF

RAMP

RRAMP

+PWM

3 V

1 V

VPWM(EXT)

CVREF

DIM/PWM

Triangle

Wave

Generator

5V LDO

Regulator

1 V

3 V

VREF

RAMP

CRAMP

+PWM

3 V

1 V

VCTRL DDIM

RDIM2

RDIM1

CVREF

DIM/PWM

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Feature Description (continued)

Figure 29. PWM Dimming Using Internal PWM Generator

The devices can be configured to be compatible with external PWM signal, VPWM(EXT), where the LED current is

modulated based on the duty cycle, DPWM(EXT). To enable direct PWM, it is required to disable the internal

triangle wave generator by connecting a 249-kΩresistor from RAMP pin to GND. In this case, the internal

comparator threshold is set to 2.49-V and the internal PWM duty cycle, DPWM(INT), is controlled by the external

PWM command. The RAMP pin cannot be left floating.

Figure 30. Direct PWM Dimming

The internal PWM signal, VPWM controls the GATE and PDRV outputs. Forcing VPWM in a logic low state turns off

switching, parks the oscillator, disconnects the COMP pin, and sets the PDRV output to VCSP in order to maintain

the charge on the compensation network and output capacitors. On the rising edge of the PWM voltage (VPWM

set to logic level high), the GATE and PDRV outputs are enabled to ramp the inductor current to the previous

steady-state value. The COMP pin is connected and the error amplifier and oscillator are enabled only when the

switch current sense voltage VIS exceeds the COMP voltage, VCOMP, thus immediately forcing the converter into

steady-state operation with minimum LED current overshoot. When dimming is not required, connect the

DIM/PWM pin to the VCC pin. An internal pull-down resistor sets the input to logic-low and disables the device

when the pin is disconnected or left floating.

l TEXAS INSTRUMENTS ow 14

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Feature Description (continued)

8.3.11 Series P-Channel FET Dimming Gate Driver Output

The PDRV output is a function of the internal PWM signal and is capable of sinking and sourcing up to 50 mA of

peak current to control a high-side series connected P-channel dimming FET. The PDRV switches between VCSP

and (VCSP– 7 V) based on the status of PWM signal to completely turn-off and turn-on the external P-channel

dimming FET. The series dimming FET is required to achieve high contrast ratio as it ensures fast rise and fall

times of the LED current in response to the PWM input. Without any dimming FET, the rise and fall times are

limited by the inductor slew rate and the closed-loop bandwidth of the system. Leave the PDRV pin unconnected

if not used.

8.3.12 Soft-Start

The soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startup

stresses and surges. The devices clamp the COMP pin to the SS pin, separated by a diode, until LED current

nears the regulation threshold. The internal 10-µA soft-start current source gradually increases the voltage on an

external soft-start capacitor CSS connected to the SS pin. This results in a gradual rise of the COMP voltage from

GND.

The internal 10-µA current source turns on when VCC exceeds the UVLO threshold. At the beginning of the soft-

start sequence, the SS pull-down switch is active and is released when the voltage VSS drops below 50 mV. The

SS pin can also be pulled down by an external switch to stop switching. When the SS pin is externally driven to

enable switching, the slew-rate on the COMP pin is controlled by the compensation capacitor. In this case, the

startup duration and LED current transient is controlled by tunning the compensation network. It is essential to

ensure that the softstart duration is longer than the time required to charge the output capacitor when selecting

the soft-start capacitor, CSS and the compensation capacitor, CCOMP.

8.3.13 Current Monitor Output

The IMON pin voltage represents the LED current measured by the rail-to-rail current sense amplifier across the

external current shunt resistor. The linear relationship between the IMON voltage and LED current includes the

amplifier gain-factor of 14 (see Feature Description section). The IMON output can be connected to an external

microcontroller or comparator to facilitate LED open, short, or cable harness fault detection and mitigation. The

IMON voltage is internally clamped to 3.7 V.

8.3.14 Output Overvoltage Protection

The TPS92692 and TPS92692-Q1 devices include a dedicated OV pin which can be used for either input or

output overvoltage protection. This pin features a precision 1.228 V (typ) threshold with 20-µA (typ) of hysteresis

current. The overvoltage threshold limit is set by a resistor divider network from the input or output terminal to

GND. When the OV pin voltage exceeds the reference threshold, the GATE pin is immediately pulled low, the

PDRV output is disabled, and the SS and COMP capacitors are discharged. The GATE and PDRV outputs are

enabled and a new startup sequence is initiated after the voltage drops below the hysteresis threshold set by the

20-µA source current and the external resistor divider.

8.3.15 Output Short-circuit Protection

The device monitors the output of the current sense amplifier and the output voltage via OV pin to determine

LED Short-circuit fault. The device signals an output overcurrent fault when the voltage across the current sense

amplifier, (V(CSP-CSN)), exceeds the regulation set point based on the IADJ pin voltage, VIADJ. The overcurrent fault

threshold is calculated as follows:

(7)

The device also indicates a short-circuit condition when the voltage across the OV pin and GND falls below 100

mV. In this case, the output voltage, VO, is below the undervoltage fault threshold determined based on the

resistor divider connected to the OV pin.

(8)

l TEXAS INSTRUMENTS

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Feature Description (continued)

The devices indicate a fault by forcing the open-drain fault indicator FLT pin to GND and initiating a 36-ms timer.

The devices do not internally initiate any protection action and continue to operate until externally disabled by

pulling SS pin to GND. This provides maximum design flexibility to enable user defined fault protection by using

either the fault indicator output, FLT, or the analog IMON output based on the LED driver topology and end

application.

The undervoltage fault detection circuit is internally disable based on the SS pin voltage and internal PWM

status. The fault blanking circuit is designed to prevent false undervoltage detection during the startup sequence

and PWM dimming operation.

8.3.16 Thermal Protection

Internal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 175°C, the controller is forced into a shutdown mode,

disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.

8.3.17 Fault Indicator (FLT)

The devices include an open-drain output to indicate fault conditions. The FLT pin goes low under the following

conditions:

• Overvoltage across the LED string (VOV> 1.24 V)

• Under voltage across the LED string (VOV< 100 mV)

• Overcurrent across the LED string (14 × V(CSP-CSN) > 1.5 × VIADJ)

• Cycle-by-cycle switch current limit condition (VIS > 250 mV)

The FLT pin goes high when the fault conditions ends or when the internal 36-ms timer expires. The status of the

FLT under different fault conditions is summarized in the Device Functional Modes section.

8.4 Device Functional Modes

The following table summarizes the device behavior under fault condition.

Table 1. Fault Descriptions

FAULT DETECTION ACTION

Input undervoltage

(UVLO)

VCC(RISE) < 4.5 V The device enters the standby state when the VCC voltage falls below the UVLO

threshold. In standby state, GATE and PDRV outputs are disabled and the SS and

COMP capacitors are discharged. FLT pin remains in high-impedance state.

VCC(FALL) < 4.1 V

Switch current limit VIS > 250 mV

Cycle-by-cycle current limit is activated when the IS pin voltage exceeds 250 mV. The

GATE and PDRV outputs are disabled, the SS and COMP pin capacitors are discharged

and FLT pin is forced to ground. An internal 35-μs timer is activated. Soft-start sequence

is initiated after expiration of the 35 μs timer period.

Thermal protection TJ> 175°C

Internal thermal shutdown circuitry is activated when the junction temperature exceeds

175 °C. The controller is forced into a shutdown mode, disabling the internal regulators.

A startup sequence is initiated when the junction temperature falls below 155˚C. The

FLT pin remains in a high-impedance state.

Programmable output

overvoltage protection VOV > 1.228 V

When the OV pin voltage exceeds 1.228 V, GATE and PDRV outputs are disabled, SS

and COMP capacitors are discharged, and the FLT pin is forced to GND. A soft-start

sequence is initiated once the output voltage drops below the hysteresis threshold set by

the 20 μA current source.

Fixed LED Overcurrent

protection V(CSP-CSN) > V((CSP-

CSN),OCP)

The FLT pin is forced to ground for 36-ms when the LED current exceeds 1.5 times the

regulation set point. The FLT pin is released after timer expires. Under sustained short-

circuit condition, the FLT pin transitions between a high-impedance state and ground

until the fault is cleared. Device continues to operate while in this condition.

Output undervoltage

protection VOV < 100 mV

The FLT pin is forced to ground for 36-ms when OV pin voltage drops below 100 mV.

The FLT pin is released after timer expires. Under sustained short-circuit condition, the

FLT pin transitions between the high-impedance state and ground until fault is cleared.

Device continues to operate while in this condition.

Programmable LED

overcurrent protection VIMON > VIADJ

Current monitor output (IMON) can be used to externally program current limit. The

IMON output can be connected to an external microcontroller or comparator to facilitate

LED open, short, or cable harness fault detection.

l TEXAS INSTRUMENTS as“ 22‘ 22‘ §WHLML§J§MWM

T(FAULT_TMR)

ILED

SS/FLT

GATE

PDRV

ISS = 10A

Overcurrent

Detected

T(FAULT_TMR) T(FAULT_TMR)

2.4 V

VSS(UVP_EN)

Fault

Cleared

T(FAULT_TMR)

VCSP

SS/FLT

GATE

PDRV

ISS = 10A2.4 V

VSS(UVP_EN)

Undervoltage

Detected

T(FAULT_TMR) T(FAULT_TMR)

Fault

Cleared

FLT

CSS

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Device Functional Modes (continued)

Table 1. Fault Descriptions (continued)

FAULT DETECTION ACTION

COMP pin short to

ground VCOMP < 1.6 V Switching is disabled when COMP voltage falls below 1.6 V. The FLT pin remains a in

high-impedance state.

VREF pin short to

ground VREF < 2.0 V The device enters standby when the VCC voltage falls below the UVLO threshold. In the

standby state, GATE and PDRV outputs are disabled and the SS and COMP capacitors

are discharged. The FLT pin will remain in a high-impedance state.

8.4.1 Hiccup Mode Short-circuit Protection

Connecting the FLT pin to the SS pin enables hiccup mode operation under output short-circuit conditions.

Figure 31. Hiccup Mode Short-Circuit Protection

On detection of output short-circuit fault, the FLT pin forces the SS pin to GND (VSS < 50 mV) and disables

GATE and PDRV outputs for 36-ms. Upon timer expiration, the FLT pin is released and a new soft start

sequence is initiated. Under sustained fault conditions the device operates in hiccup mode, attempting to recover

after every 36-ms period.

Figure 32. Output Overcurrent Fault Protection Figure 33. Output Undervoltage Fault Protection

8.4.2 Fault Indication Mode

The FLT pin output can be setup to indicate fault status to a microcontroller and aid in fault diagnostics and

protection. In case of a fault, the FLT pin is forced low when biased through an external resistor connected either

to reference voltage output, VREF, or an external bias supply. When connected to VREF, the FLT pin is driven

low when the device enters standby mode during UVLO, thermal shutdown, or VREF short-circuit conditions. The

Fault Indicator (FLT) section lists fault diagnostics and system level faults.

‘5‘ TEXAS INSTRUMENTS 57$ 57$

FLT

TPS92692

CSS

RFLT

BIAS

GPIO1

GPIO2

Microcontroller

FLT

TPS92692

CSS

RFLT

VREF

GPIO1

GPIO2

Microcontroller

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Figure 34. FLT Pin Interface With Microcontroller Figure 35. FLT Pin Interface With Microcontroller

l TEXAS INSTRUMENTS

VCTRL

TPS92692-Q1

VIN

VREF

FLT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

GND

SLOPE

CSP

CSN

PDRV

RAMP

VIN LED +

LED í

CIN

CVREF

CSS

CDM

CCOMP

CIMON

RADJ2

RADJ1

RDIM2

RDIM1

RSLP

RIS

CVCC

ROV1

ROV2

COUT

CRAMP

RCS

QDIM

DDIM PAD

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS92692 and TPS92692-Q1 controllers are suitable for implementing step-up or step-down LED driver

topologies including boost, buck-boost, SEPIC, and flyback. Use the following design procedure to select

component values for the TPS92692-Q1 device. This section presents a simplified discussion of the design

process for the boost and buck-boost converter. The expressions derived for the buck-boost topology can be

altered to select components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be easily

adapted for flyback and similar converter topologies.

Figure 36. Boost LED Driver

l TEXAS INSTRUMENTS

TPS92692-Q1

VIN

VREF

FLT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

GND

SLOPE

CSP

CSN

PDRV

RAMP

VIN LED +

LED í

CIN

RSLP

RIS

CVCC

ROV1

ROV2

COUT

CRAMP

RCS

QDIM

PAD

CDC

RDC

VCTRL

CVREF

CSS

CDM

CCOMP

CIMON

RADJ2

RADJ1

RDIM2

RDIM1

DDIM

TPS92692-Q1

VIN

VREF

FLT

COMP

IMON

IADJ

DIM/PWM

VCC

GATE

GND

SLOPE

CSP

CSN

PDRV

RAMP

VIN LED +

LED í

CIN

RSLP

RIS

CVCC

ROV1

ROV2

CRAMP

RCS

QDIM

PAD

COUT

VCTRL

CVREF

CSS

CDM

CCOMP

CIMON

RADJ2

RADJ1

RDIM2

RDIM1

DDIM

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Product Folder Links: TPS92692 TPS92692-Q1

Application Information (continued)

Figure 37. Buck-Boost LED Driver

Figure 38. SEPIC LED Driver

l TEXAS INSTRUMENTS D O D IN + 0 Po Mn N) 4 2 |_ 7 L 1

 

O(MIN) IN(MIN)

L(PK) O(MAX) O(MIN) IN(MIN) SW O(MIN) IN(MIN)

V V

1 1

I P V V 2 L f V V

§ · u

u  

¨ ¸

¨ ¸ u u u 

O(MAX) IN(MIN) IN(MIN)

L(PK) IN(MIN) SW O(MAX) O(MAX)

P V V

i 1

V 2 L f V V

§ ·

 u 

¨ ¸

u u u © ¹

O(BDRY) SW O(MAX) IN(MAX)

L1 1

2 P f V V

§ ·

u u u 

¨ ¸

IN(MAX) IN(MAX)

O(BDRY) SW O(MAX)

V V

L 1

2 P f V

§ ·

u 

¨ ¸

u u © ¹

O(MAX) O(MAX)

O(BDRY)

P P

4 2

d d

O(BDRY) LED(MIN) O(MIN)

P I Vd u

IN O

DV V



O IN

V V



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Application Information (continued)

9.1.1 Duty Cycle Considerations

The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In

steady state, the duty cycle is derived using expression:

Boost:

(9)

Buck-Boost:

(10)

The minimum duty cycle, DMIN, and maximum duty cycle, DMAX, are calculated by substituting maximum input

voltage, VIN(MAX), and the minimum input voltage, VIN(MIN), respectively in the previous expressions. The minimum

duty cycle achievable by the device is determined by the leading edge blanking period and the switching

frequency. The maximum duty cycle is limited by the internal oscillator to 90% (typ) to allow for minimum off-time.

It is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loop

LED current regulation over the specified input and output voltage range.

9.1.2 Inductor Selection

The choice of inductor sets the continuous conduction mode (CCM) and discontinuous conduction mode (DCM)

boundary condition. Therefore, one approach of selecting the inductor value is by deriving the relationship

between the output power corresponding to CCM-DCM boundary condition, PO(BDRY) and inductance, L. This

approach ensures CCM operation in battery-powered LED driver applications that are required to support

different LED string configurations with a wide range of programmable LED current set points. The CCM-DCM

boundary condition can be estimated either based on the lowest LED current and the lowest output voltage

requirements for a given application or as a fraction of maximum output power, PO(MAX).

(11)

(12)

Boost:

(13)

Buck-Boost:

(14)

Select inductor with saturation current rating greater than the peak inductor current, IL(PK), at the maximum

operating temperature.

Boost:

(15)

Buck-Boost:

(16)

l TEXAS INSTRUMENTS MAX

 

O(MAX)

IN SW IN(PP) O(MIN) IN(MIN)

Cf v V V

u ' u 

IN(MIN) IN(MIN)

IN 2O(MAX)

SW IN(PP)

V V

C 1 V

8 L f v

§ ·

u 

¨ ¸

u u u ' © ¹

MAX

COUT(RMS) LED MAX

I I 1 D



 

O(MAX)

OUT LED(PP) SW D(MIN) O(MIN) IN(MIN)

Ci f r V V

' u u u 

O(MAX) IN(MIN)

OUT LED(PP) D(MIN) SW O(MAX) O(MAX)

P V

C 1

i r f V V

§ ·

u 

¨ ¸

' u u u © ¹

TPS92692

TPS92692-Q1

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Product Folder Links: TPS92692 TPS92692-Q1

Application Information (continued)

9.1.3 Output Capacitor Selection

The output capacitors are required to attenuate the discontinuous or large ripple current generated by switching

and achieve the desired peak-to-peak LED current ripple, ΔiLED(PP). The capacitor value depends on the total

series resistance of the LED string, rDand the switching frequency, ƒSW.The capacitance required for the target

LED ripple current can be calculated based on following equations.

Boost:

(17)

Buck-Boost:

(18)

When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they

directly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple

current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is

important to consider the derating factors associated with higher temperature and DC bias operating conditions.

TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An aluminum

electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. The

aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged operating

lifetime. The minimum allowable RMS output capacitor current rating, ICOUT(RMS), can be approximated:

Boost and Buck-Boost:

(19)

9.1.4 Input Capacitor Selection

The input capacitors, CIN, smooth the input voltage ripple and store energy to supply input current during input

voltage or PWM dimming transients. The series inductor in the Boost and SEPIC topologies provides continuous

input current and requires a smaller input capacitor to achieve desired input ripple voltage, ΔvIN(PP). The Buck-

Boost and Flyback topologies have discontinuous input current and require a larger capacitor to achieve the

same input voltage ripple. Based on the switching frequency, ƒSW, and the maximum duty cycle, DMAX, the input

capacitor value can be calculated as follows:

Boost:

(20)

Buck-Boost:

(21)

X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, and

good temperature performance. For applications using PWM dimming, TI recommends an aluminum electrolytic

capacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transients

generated in conjunction with the rising and falling edges of the LED current.

l TEXAS INSTRUMENTS GATE

D LED(MAX)

I I

L SW RSS SW

SW GATE

I V C f

u u u

COND DS Q(RMS)

P R I u

O(MAX) IN(MIN)

Q(RMS) IN(MIN) O(MIN)

P V

I 1

V V

§ ·

u 

¨ ¸

 

DS O(OV) IN(MAX)

V 1.1 V V u 

DS O(OV)

V 1.1 V u

RVIN

CVIN

VIN

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Application Information (continued)

Figure 39. VIN Filter

Decouple VIN pin with a 0.1-µF ceramic capacitor, placed as close as possible to the device and a series 10-Ω

resistor to create a 150-kHz low-pass filter.

9.1.5 Main Power MOSFET Selection

The power MOSFET is required to sustain the maximum switch node voltage, VSW, and switch RMS current

derived based on the converter topology. TI recommends a drain voltage VDS rating of at least 10% greater than

the maximum switch node voltage to ensure safe operation. The MOSFET drain-to-source breakdown voltage,

VDS, is calculated using the following expressions.

Boost:

(22)

Buck-Boost:

(23)

The voltage, VO(OV), is the overvoltage protection threshold and the worst-case output voltage under fault

conditions. The worst case MOSFET RMS current for Boost and Buck-Boost topology is dependent on maximum

output power, PO(MAX), and is calculated as follows:

(24)

Select a MOSFET with low total gate charge, Qg, to minimize gate drive and switching losses. The MOSFET RDS

resistance is usually a less critical parameter because the switch conduction losses are not a significant part of

the total converter losses at high operating frequencies. The switching and conduction losses are calculated as

follows:

(25)

(26)

CRSS is the MOSFET reverse transfer capacitance. ILis the average inductor current. IGATE is gate drive output

current, typically 500 mA. The MOSFET power rating and package is selected based on the total calculated loss,

the ambient operating temperature, and maximum allowable temperature rise.

9.1.6 Rectifier Diode Selection

A Schottky diode (when used as a rectifier) provides the best efficiency due to its low forward voltage drop and

near-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, VD(BR), greater than

or equal to MOSFET drain-to-source voltage, VDS, for reliable performance. It is important to understand the

leakage current characteristics of the Schottky diode, especially at high operating temperatures because it

impacts the overall converter operation and efficiency.

Use Equation 27 to calculate the current through the diode, ID.

(27)

l TEXAS INSTRUMENTS CS L‘ R‘s

SL IS

R 274.4 10 ( )

u u :

VCC

GATE

GND

RIS

100 

1 nF

IS(LIMIT)

IS L(PK)

IADJ

LED CS

I14 R

LED CS

170.7 mV

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Product Folder Links: TPS92692 TPS92692-Q1

Application Information (continued)

The diode power rating and package is selected based on the calculated current, the ambient temperature and

the maximum allowable temperature rise.

9.1.7 LED Current Programming

The LED current is set by the external current sense resistor, RCS, and the analog adjust voltage, VIADJ. The

current sense resistor is placed in series with the LED load. The CSP and CSN inputs of the internal rail-to-rail

current sense amplifier are connected to the RCS resistor to enable closed-loop regulation. When VIADJ > 2.5 V,

the internal 2.4-V reference sets the V(CSP-CSN) threshold to 170.7 mV and the LED current is regulated to:

(28)

The LED current can be programmed by varying VIADJ between 140 mV to 2.25 V. The LED current can be

calculated using:

(29)

TI recommends a low-pass common-mode filter consisting of 10-Ωresistors in series with CSP and CSN inputs

and 0.01-µF capacitors to ground to minimize the impact of voltage ripple and noise on LED current accuracy

(see Figure 24 section). A 0.1-µF capacitor across CSP and CSN is included to filter high-frequency differential

noise.

9.1.8 Switch Current Sense Resistor

The switch current sense resistor, RIS, is used to implement peak current mode control and to set the peak

switch current limit. The value of RIS is selected to protect the main switching MOSFET under fault conditions.

The RIS can be calculated based on peak inductor current, iL(PK), and switch current limit threshold, VIS(LIMIT).

(30)

Figure 40. IS Input Filter

The use of a 1-nF and 100-Ωlow-pass filter is optional. If used, the recommended resistor value is less than 500

Ωin order to limit its influence on the internal slope compensation signal.

9.1.9 Slope Compensation

The magnitude of internal artificial ramp, VSL, is set by slope resistor RSLP. The device compensates for the

changes in input voltage, VIN and output voltage sensed by CSP pin, VCSP to achieve stable inner current loop

operation over wide range of operating conditions. The value of RSLP is determined by the inductor, L and the

switch current sense resistor, RIS and is independent of input and output voltage for Boost, Boost-to-Battery and

Buck-Boost topologies.

(31)

l TEXAS INSTRUMENTS K \ P ( ) 2 o D OUT >

   

COMP COMP

COMP M CS

COMP HF

LED COMP HF

COMP COMP HF

Ö1 s R C

v 14 g R

Ös C C

iC C

1 s R C C

 u u

u u

 u  § ·

§ ·

 u u

¨ ¸



COMP M CS

COMP

LED

v 14 g R

Ös C

u u



 

IS O D LED

(1 D) V

R V D r I

 u

u  u u

 

O D LED

O D OUT

V D r I

V r C

 u u

u u

LED

V (1 D)

D L I

u 

u u

 

IS O D LED

(1 D) V

R V r I

 u

u  u

 

O D LED

O D OUT

V r I

V r C

 u

u u

LED

V (1 D)

L I

u 

LED 0

COMP

§ ·



¨ ¸

u § ·



¨ ¸

TPS92692

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Product Folder Links: TPS92692 TPS92692-Q1

Application Information (continued)

9.1.10 Feedback Compensation

The open-loop response is the product of the modulator transfer function (shown in Equation 32) and the

feedback transfer function. Using a first-order approximation, the modulator transfer function can be modeled as

a single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zero

created by the inductor, where both have a dependence on the LED string dynamic resistance, rD. The ESR of

the output capacitor is neglected in the analysis. The small-signal modulator model also includes a DC gain

factor that is dependent on the duty cycle, output voltage, and LED current.

(32)

The Table 2 summarizes the expression for the small-signal model parameters.

Table 2. Small-Signal Model Parameters

DC GAIN (G0) POLE FREQUENCY (ωP) ZERO FREQUENCY (ωZ)

Boost

Buck-Boost

The feedback transfer function includes the current sense resistor and the loop compensation of the

transconductance amplifier. A compensation network at the output of the error amplifier is used to configure loop

gain and phase characteristics. A simple capacitor, CCOMP, from COMP to GND (as shown in Figure 41) provides

integral compensation and creates a pole at the origin. Alternatively, a network of RCOMP, CCOMP, and CHF, shown

in Figure 42, can be used to implement proportional and integral (PI) compensation to create a pole at the origin,

a low-frequency zero, and a high-frequency pole.

The feedback transfer function is defined as follows.

Feedback transfer function with integral compensation:

(33)

Feedback transfer function with proportional integral compensation:

(34)

The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator

by placing the low-frequency zero an order of magnitude less than the crossover frequency. Use the following

expressions to calculate the compensation network.

l TEXAS INSTRUMENTS ri] OVI

OV1 OV2

O(OV) OVP(THR) OV1

R R

V V R

§ ·



u ¨ ¸

SS SS

C 12.5 10 t



u u

COMP P COMP

Z u

COMP

HF C

C100

3CS 0

COMP Z

R G

C 8.75 10§ ·

u u ¨ ¸

3CS

COMP P

8.75 10 R



u u

COMP

CSP

CSN

IADJ

CURRENT SENSE

AMPLIFIER

GAIN = 14

RCS

ILED

VCC

2.42V

CCOMP

COMP

CSP

CSN

IADJ

CURRENT SENSE

AMPLIFIER

GAIN = 14

RCS

ILED

VCC

2.42V

CHF

CCOMP

RCOMP

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Product Folder Links: TPS92692 TPS92692-Q1

Figure 41. Integral Compensator Figure 42. Proportional Integral Compensator

Boost and Buck-Boost with integral compensator:

(35)

Boost and Buck-Boost with proportional integral compensator:

(36)

(37)

(38)

The loop response is verified by applying step input voltage transients. The goal is to minimize LED current

overshoot and undershoot with a damped response. Additional tuning of the compensation network may be

necessary to optimize PWM dimming performance.

9.1.11 Soft-Start

The soft-start time (tSS) is the time required for the LED current to reach the target set point. The required soft-

start time is programmed using a capacitor, CSS, from SS pin to GND, and is based on the LED current, output

capacitor, and output voltage.

(39)

9.1.12 Overvoltage and Undervoltage Protection

The overvoltage threshold is programmed using a resistor divider, ROV2 and ROV1, from the output voltage, VO, to

GND for Boost and SEPIC topologies, as shown in Figure 36 and Figure 38. If the LEDs are referenced to a

potential other than GND, as in the Buck-Boost, the output voltage is sensed and translated to ground by using a

PNP transistor and level-shift resistors, as shown in Figure 37. The overvoltage turn-off threshold, VO(OV), is:

Boost:

(40)

l TEXAS INSTRUMENTS D‘M ow (M NH

REF DIM

DIM2 DIM1

DIM

V V

R R

§ ·



¨ ¸

DIM DIM(MIN)

V 1 2 D  u

OV1 OV2

O(UV) OV1

R R

V 0.1 R



OV(HYS) OVP(HYS) OV2

V I R u

OV2

O(OV) OVP(THR) OV1

V V 0.7

u 

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Buck and Buck-Boost:

(41)

The overvoltage hysteresis, VOV(HYS) is:

(42)

The corresponding undervoltage fault threshold, VO(UV) is:

(43)

9.1.13 Analog to PWM Dimming Considerations

The analog to PWM duty cycle translation is based on the internal PWM generator, configured by connecting a

capacitor across RAMP pin and GND, as shown in Figure 29. The minimum PWM duty cycle is programmed by

setting the voltage on DIM/PWM pin, VDIM using a resistor divider from VREF pin to GND.

(44)

(45)

The device is designed to support a minimum PWM duty cycle of 4% with better than 5% accuracy from

DIM/PWM input to PDRV output in this operating mode. To avoid excess loading of the VREF LDO output, TI

recommends a resistor network with sum of resistors RDIM1 and RDIM2 greater than 10 kΩ. A bypass capacitor of

0.1-µF prevents noise coupling and improves performs for low dimming values.

9.1.14 Direct PWM Dimming Considerations

The device can be configured to implement dimming function based on external PWM command by disabling the

internal ramp generator, as explained in DIM/PWM Input section. The internal comparator reference is set to 2.49

V by connecting a 249-kΩresistor, RRAMP, from the RAMP pin to GND. The internal PWM duty cycle is controlled

by an external 5-V or 3.3-V signal, generated by a command module or a microcontroller.

9.1.15 Series P-Channel MOSFET Selection

When PWM dimming, the device requires another P-channel MOSFET placed in series with the LED load. Select

a P-channel MOSFET with gate-to-source voltage rating of 10-V or higher and with a drain-to-source breakdown

voltage rating greater than the output voltage. Ensure that the drain current rating of the P-channel MOSFET

exceeds the programmed LED current by at least 10%.

It is important to consider the FET input capacitance and on-resistance as it impacts the accuracy and efficiency

of the LED driver. TI recommends a FET with lower input capacitance and gate charge to minimize the errors

caused by rise and fall times when PWM dimming at low duty cycles.

l TEXAS INSTRUMENTS .am u;

GND

4700pF

GND GND

100V

VBAT2

VBAT1

4.7µF

C16

4.7µF

C17

GND

100V

0.06

R10

100

2.2µF

C29

0.1µF

C25

3.01k

R11

150k

0.01 µF

C27

0.01 µF

C28

10.0

R12

10.0

R13

GND

100V

VCC

0.039 µF

C36

20.0k

R15

0.1µF

C23

33.0k

R22

10.0

10pF

C32

29.4k

R21

68.1k

R16

0.1µF

C18

0.027 µF

C24

2.2µF

C20

GND

100k

R14

0.01 µF

C35

VREF

FLT

VIN

COMP

IMON

IADJ

DIM/PWM

10 RAMP 11

PDRV 12

CSN 13

CSP 14

OVP 15

SLOPE 16

GND 17

IS 18

GATE 19

VCC 20

DAP

TPS92692Q

10.0k

R25

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9.2 Typical Applications

9.2.1 Typical Boost LED Driver

Figure 43. Boost LED Driver With High-Side Current Sense

TEXAS INSTRUMENTS DM 8 DM 7 1 DM 1 I 0 ‘ D

 

10 10 3

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9.2.1.1 Design Requirements

Table 3 shows the design parameters for the boost LED driver application.

Table 3. Design Parameters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

Input voltage range 7 14 18 V

Input UVLO setting 4.5 V

OUTPUT CHARACTERISTICS

LED forward voltage 2.8 3.2 3.6 V

Number of LEDs in series 14

VOOutput voltage LED+ to LED– 39.2 44.8 50.4 V

ILED Output current 350 500 mA

RR LED current ripple ratio 4%

rDLED string resistance 3 Ω

PO(MAX) Maximum output power 25 W

fPWM PWM dimming frequency 240 Hz

DPWM Analog to PWM duty cycle set point (low

brightness mode) 8 %

SYSTEMS CHARACTERISTICS

PO(BDRY) Output power at CCM-DCM boundary

condition 6 W

ΔvIN(PP) Input voltage ripple 20 mV

VO(OV) Output overvoltage protection threshold 62 V

VOV(HYS) Output overvoltage protection hysteresis 3 V

tss Soft-start period 8 ms

fDM Dither Modulation Frequency 600 Hz

fSW Switching frequency 390 kHz

9.2.1.2 Detailed Design Procedure

This procedure is for the boost LED driver application.

9.2.1.2.1 Calculating Duty Cycle

Solve for D, DMAX, and DMIN:

(46)

(47)

(48)

9.2.1.2.2 Setting Switching Frequency

Solve for RT:

(49)

The closest standard resistor of 20 kΩis selected.

l TEXAS INSTRUMENTS xMODx x X AiL

O(MAX) IN(MIN)

Q(RMS) IN(MIN) O(MIN)

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9.2.1.2.3 Setting Dither Modulation Frequency

Solve for CDM:

(50)

The closest standard capacitor is 27 nF.

9.2.1.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). In most applications,

PO(BDRY) is set to be 1/3 of the maximum output power, PO(MAX). The inductor value is calculated for typical input

voltage, VIN(TYP), and output voltage, VO(TYP):

(51)

The closest standard inductor is 22 µH.

For best results, ensure that the inductor saturation current rating is greater than the peak inductor current, IL(PK).

(52)

9.2.1.2.5 Output Capacitor Selection

The specified peak-to-peak LED current ripple, ΔiLED(PP), is:

(53)

The output capacitance required to achieve the target LED current ripple is:

(54)

Four 4.7-µF, 100-V rated X7R ceramic capacitors are used in parallel to achieve a combined output capacitance

of 18.8 µF.

9.2.1.2.6 Input Capacitor Selection

The input capacitor is required to reduce switching noise conducted through the input wires and reduced the

input impedance of the LED driver. The capacitor required to limit peak-to-peak input ripple voltage ripple,

ΔvIN(PP), to 20 mV is given by:

(55)

Two 4.7-µF, 50-V X7R ceramic capacitors are used in parallel to achieve a combined input capacitance of 9.4-

µF.

9.2.1.2.7 Main N-Channel MOSFET Selection

Ensure that the MOSFET ratings exceed the maximum output voltage and RMS switch current.

(56)

(57)

A N-channel MOSFET with a voltage rating of 100-V and a current rating of 4 A is required for this design.

l TEXAS INSTRUMENTS VD 2 ID 5 H 7 3

3 3 6

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9.2.1.2.8 Rectifying Diode Selection

Select a diode should be selected based on the following voltage and current ratings:

(58)

(59)

A 100-V Schottky diode with low reverse leakage current is suitable for this design. The package must be able to

handle the power dissipation resulting from continuous forward current, ID, of 0.5 A.

9.2.1.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, RADJ1 and

RADJ2, from VREF to GND for a given sense resistor, RCS, as shown in Figure 43. To maximize the accuracy, the

IADJ pin voltage is set to 2.1 V for the specified maximum LED current of 500-mA. The current sense resistor,

RCS, is then calculated as:

(60)

A standard resistor of 0.3 Ωis selected. Table 4 summarizes the IADJ pin voltage and the choice of the RADJ1

and RADJ2 resistors for different current settings.

Table 4. Design Requirements

LED CURRENT IADJ VOLTAGE (VIADJ) RADJ1 RADJ2

100 mA 420 mV 6.34 kΩ68.1 kΩ

350 mA 1.47 V 29.4 kΩ68.1 kΩ

500 mA 2.1 V 49.9 kΩ68.1 kΩ

9.2.1.2.10 Setting Switch Current Limit

Solve for current sense resistor, RIS:

(61)

A standard value of 0.06 Ωis selected.

9.2.1.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, RSL.

(62)

A standard resistor of 100 kΩis selected.

9.2.1.2.12 Deriving Compensator Parameters

The modulator transfer function for the Boost converter is derived for nominal VIN voltage and corresponding duty

cycle, D, and is given by the following equation. (See Feedback Compensation section for more information.)

(63)

The proportional-integral compensator components CCOMP and RCOMP are obtained by solving the following

expressions:

(64)

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(65)

The closet standard capacitor of 18-nF and resistor of 4.12-kΩis selected. The high frequency pole location is

set by a 1-nF CHF capacitor.

9.2.1.2.13 Setting Start-up Duration

The soft-start capacitor required to achieve start-up in 8 ms is given by:

(66)

The closet standard capacitor of 100 nF is selected.

9.2.1.2.14 Setting Overvoltage Protection Threshold

The overvoltage protection threshold of 62 V and hysteresis of 3 V is set by the ROV1 and ROV2 resistor divider.

(67)

(68)

The standard resistor values of 150 kΩand 3.01 kΩare chosen.

9.2.1.2.15 Analog-to-PWM Dimming Considerations

The PWM dimming frequency is set by the CRAMP capacitor.

(69)

The closet standard capacitor of 10 nF is selected.

The PWM duty cycle of 8% programmed by setting the DIM/PWM voltage using resistor divider, RDIM1 and RDIM2

connected from VREF pin to GND.

(70)

The value of resistor, RDIM1 is set as of 10-kΩ. The resistor RDIM2 is calculated using the following equation:

(71)

A standard resistor of 33 kΩis selected.

A P-channel MOSFET with a voltage rating of 100-V and a current rating of 1 A is required to enable series FET

dimming for this design.

9.2.1.3 Application Curves

These curves are for the boost LED driver.

*5; TEXAS INSTRUMENTS

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Ch1: Switch node voltage;

Ch2: Switch current sense voltage;

Ch4: LED current; Time: 1 µs/div

Figure 44. Normal Operation

Ch1: Dither modulation voltage;

Ch4: LED current; Time: 400 µs/div

Figure 45. Spread Spectrum Frequency Modulation

Ch1: Input voltage; Ch2: Soft-start (SS) voltage;

Ch3: Input current;

Ch4: LED current; Time: 4 ms/div

Figure 46. Startup Transient

Ch1: Dim/PWM voltage;

Ch2: RAMP pin voltage;

Ch4: LED current; Time: 2 ms/div

Figure 47. Analog-to-PWM Dimming Transient

Ch1: External PWM input signal;

Ch2: PDRV voltage;

Ch4: LED current; Time: 2 ms/div

Figure 48. Direct PWM Dimming Transient

Ch1: External PWM input voltage;

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 4 µs/div

Figure 49. PWM Dimming Transient (Zoomed)

l TEXAS INSTRUMENTS m m ‘ ‘ UJJJJJJJJJJJ-JJJJJJJ ‘ ‘ . . I...“ mm; a. m . . I...“ mm; a. m REW 120 kHZ RBW 120 kHZ m m as m :5 mm: or; Au m as m :5 mum or; FREQUENCV manoeunno MHx FREQUENCY 1ua.uouuuuu MHz LEVEL QPK 29 6° dEpV LEVEL QPK 29.55 new —: II: 5 10 2a an as so an 70 an 90 105 s m 20 an as so an 70 ea 90 :05 mm K Ch 6W”! PA 5 10 MHI Um t Ch OWN! PA 5 10 MHz ”5 “M‘s L 5 PA ‘2“ “51042 c 5 PA "" me can PA 5 m Lme czspz PA 5 mum r Y ”A mama r 1 9“ 6GB Lme CESAS PA 5 MB Lme CZSAS PA 5 15P‘LINE 525?; PA 5 25M LINE CZSPS PA 5 m swam“ C: M FA m 5“an c 5A1 PA CW 2 PA CW 2 PA 2M 9"“ ““3 §7Emn [SLEEPS-HM 2M 2““ “"3 £1?sz MEEH'HN CW, 60m» 1 u ‘ H CW, (MEN *1 u m H czsaz UN _ \ 0st c25A2,uN_ czspsu cm; L§N cm; LIN “mew y ‘ Audﬁw V ‘ ems“ M WWW CZSASM ' \j A M. “W\ a; SGI H ﬂ ‘ Y ‘ SGl F‘ ‘A" “W ‘ Stan 150.0 kHz Stap 108.0 MHZ Start 150.0 kHz Stop 108.0 MHZ

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Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 50. LED Open-Circuit Fault

Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 51. LED Short-Circuit Fault

Figure 52. Conducted EMI Scan (SSFM Disabled) Figure 53. Conducted EMI Scan (SSFM Enabled)

‘5‘ TEXAS INSTRUMENTS z} -II|—H—- ‘ HP #

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9.2.2 Typical Buck-Boost LED Driver

Figure 54. Buck-Boost LED Driver

l TEXAS INSTRUMENTS 10 m

 

10 10 3

T1.047 1.047

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9.2.2.1 Design Requirements

Buck-Boost LED drivers provide the flexibility needed in applications that support multiple LED load

configurations. For such applications, it is necessary to modify the design procedure presented in to account for

the wider range of output voltage and LED current specifications. This design is based on the maximum output

power PO(MAX), set by the lumen output specified for the lighting application. The design procedure for a battery

connected application with 3 to 9 LEDs in series and maximum 15 W output power is outlined in this section.

Table 5. Design Parameters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

Input voltage range 7 14 18 V

Input UVLO setting 4.5 V

OUTPUT CHARACTERISTICS

LED forward voltage 2.8 3.2 3.6 V

Number of LEDs in series 3 7 11

VOOutput voltage LED+ to LED– 8.4 22.4 39.6 V

ILED Output current 100 500 1500 mA

ΔiLED(PP) LED current ripple 5%

rDLED string resistance 0.9 2.1 3.3 Ω

PO(MAX) Maximum output power 12.6 W

DPWM Direct PWM dimming range fPWM = 240 Hz 4% 100%

SYSTEMS CHARACTERISTICS

PO(BDRY) Output power at CCM-DCM boundary

condition 3 W

ΔvIN(PP) Input voltage ripple 70 mV

VO(OV) Output overvoltage protection threshold 45 V

VOV(HYS) Output overvoltage protection hysteresis 3 V

tSS Soft-start period 8 ms

fSW Switching frequency 390 kHz

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Calculating Duty Cycle

Solving for D, DMAX, and DMIN:

(72)

(73)

(74)

9.2.2.2.2 Setting Switching Frequency

Solving for RTresistor:

(75)

9.2.2.2.3 Setting Dither Modulation Frequency

Solve for CDM:

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(76)

The closest standard capacitor is 27 nF.

9.2.2.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). Typically, the boundary

condition is set to enable CCM operation at the lowest possible operating power based on minimum LED forward

voltage drop and LED current. In most applications, PO(BDRY) is set to be 1/3 of the maximum output power,

PO(MAX). The inductor value is calculated for maximum input voltage, VIN(MAX), and output voltage, VO(MAX):

(77)

The closest standard value of 33 µH is selected. The inductor ripple current is given by:

(78)

Ensure that the inductor saturation rating exceeds the calculated peak current which is based on the maximum

output power using Equation 79.

(79)

9.2.2.2.5 Output Capacitor Selection

Select the output capacitance to achieve the 5% peak-to-peak LED current ripple specification. Based on the

maximum power, the capacitor is calculated in Equation 80.

(80)

This design requires a minimum of three, 10-µF, 50-V and one 4.7-µF, 100-V, X7R ceramic capacitors in parallel

to meet the LED current ripple specification over the entire range of output power. Additional capacitance may be

required based on the derating factor under DC bias operation.

9.2.2.2.6 Input Capacitor Selection

The input capacitor is calculated based on the peak-to-peak input ripple specifications, ΔvIN(PP). The capacitor

required to limit the ripple to 70 mV over range of operation is calculated using:

(81)

A parallel combination of four 10-µF, 50-V X7R ceramic capacitors are used for a combined capacitance of 40

µF. Additional capacitance may be required based on the derating factor under DC bias operation.

9.2.2.2.7 Main N-Channel MOSFET Selection

Calculating the minimum transistor voltage and current rating:

(82)

l TEXAS INSTRUMENTS 69.3

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(83)

This application requires a 100-V N-channel MOSFET with a current rating exceeding 3 A.

9.2.2.2.8 Rectifier Diode Selection

Calculating the minimum Schottky diode voltage and current rating:

(84)

(85)

This application requires a 100-V Schottky diode with a current rating exceeding 1.5 A. TI recommends a single

high-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation over

temperature.

9.2.2.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, RADJ1 and

RADJ2, from VREF to GND for a given sense resistor, RCS, as shown in Figure 54. To maximize the accuracy, the

IADJ pin voltage is set to 2.1 V for the specified LED current of 1.5 A. The current sense resistor, RCS, is then

calculated as:

(86)

A standard resistor of 0.1 Ωis selected. Table 5 summarizes the IADJ pin voltage and the choice of the RADJ1

and RADJ2 resistors for different current settings.

Table 6. Design Requirements

LED CURRENT IADJ VOLTAGE (VIADJ) RADJ1 RADJ2

100 mA 140 mV 2.0 kΩ68.1 kΩ

500 mA 700 mV 11.2 kΩ68.1 kΩ

1.5 A 2.1 V 50 kΩ68.1 kΩ

9.2.2.2.10 Setting Switch Current Limit and Slope Compensation

Solving for RIS:

(87)

A standard resistor of 0.06 Ωis selected.

9.2.2.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, RSL.

(88)

A standard resistor of 150 kΩis selected.

9.2.2.2.12 Deriving Compensator Parameters

A simple integral compensator provides a good starting point to achieve stable operation across the wide

operating range. The modulator transfer function with the lowest frequency pole location is calculated based on

maximum output voltage, VO(MAX), duty cycle, DMAX, LED dynamic resistance, rD(MAX), and minimum LED string

current, ILED(MIN). (See Table 2 for more information.)

TEXAS INSTRUMENTS ( \ P 3 C — C p 5.9 10 (:55, x 6x55, >< bxx="" r="" 3="" 20x10="" 20x10="">

OV2

OV1 O(OV)

1.228 R 1.228 150 10

R 4.16 10

V 0.7 45 0.7

uu u

 

OV(HYS) 3

OV2 6 6

R 150 10

20 10 20 10

 

u u

6 6 3 9

SS SS

C 12.5 10 t 12.5 10 8 10 100 10

   

u u u u u u

339

COMP 3

8.75 10 R 8.75 10 0.1

C 98.3 10

8.9 10





u u u u

LED 0

COMP 3

i145.7 10

G 2.48

18.9 10

§ · § ·



¨ ¸ ¨ ¸

u u

§ · § ·



¨ ¸ ¨ ¸

TPS92692

TPS92692-Q1

www.ti.com

SLVSDD9 –MARCH 2017

Product Folder Links: TPS92692 TPS92692-Q1

(89)

The compensation capacitor needed to achieve stable response is:

(90)

A 100 nF capacitor is selected.

A proportional integral compensator can be used to achieve higher bandwidth and improved transient

performance. However, it is necessary to experimentally tune the compensator parameters over the entire

operating range to ensure stable operation.

9.2.2.2.13 Setting Startup Duration

Solving for soft-start capacitor, CSS, based on 8-ms startup duration:

(91)

A 100-nF soft-start capacitor is selected.

9.2.2.2.14 Setting Overvoltage Protection Threshold

Solving for resistors, ROV1 and ROV2:

(92)

(93)

The closest standard values of 150 kΩand 4.12 kΩalong with a 60-V PNP transistor are used to set the OVP

threshold to 45 V with 3 V of hysteresis.

9.2.2.2.15 Direct PWM Dimming Consideration

A 60-V, 2-A P-channel FET is used to achieve series FET PWM dimming.

9.2.2.3 Application Curves

These curves are for the buck-boost LED driver.

i TEXAS INSTRUMENTS 1 son 1 no —— w ~i¥~ummur UTHMJMMJJIW LJMJMJJJJLf 73H -

VIADJ (V)

LED Current (mA)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

200

400

600

800

1000

1200

1400

1600

D021

3 LEDs

LED Current (mA)

Efficiency (%)

100 200 300 400 500 700 1000 2000

100

D022

3 LEDs

5 LEDs

7 LEDs

9 LEDs

TPS92692

TPS92692-Q1

SLVSDD9 –MARCH 2017

www.ti.com

Product Folder Links: TPS92692 TPS92692-Q1

VIN = 14 V

Figure 55. LED Current vs IADJ Voltage

VIN = 14 V

Figure 56. Efficiency

Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 57. LED Open-Circuit Fault

Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 58. LED Short-Circuit Fault

10 Power Supply Recommendations

This device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input could

be a car battery or another preregulated power supply. If the input supply is located more than a few inches from

the TPS92692 or TPS92692-Q1 device, additional bulk capacitance or an input filter may be required in addition

to the ceramic bypass capacitors to address noise and EMI concerns.

l TEXAS INSTRUMENTS

TPS92692

TPS92692-Q1

www.ti.com

SLVSDD9 –MARCH 2017

Product Folder Links: TPS92692 TPS92692-Q1

11 Layout

11.1 Layout Guidelines

• The performance of the switching regulator depends as much on the layout of the PCB as the component

selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI

within the circuit.

• Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths.

The main path for discontinuous current in the devices using a buck regulator topology contains the input

capacitor, CIN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, RIS. In the

TPS92692 and TPS92692-Q1 devices using a boost regulator topology, the discontinuous current flows

through the output capacitor COUT, diode, D, N-channel MOSFET, Q1, and the current sense resistor, RIS. In

devices using a buck-boost regulator topolog. Be careful when laying out both discontinuous loops. Ensure

that these loops are as small as possible. In order to minimize parasitic inductance, ensure that the

connection between all the components are short and thick. In particular, make the switch node (where L, D,

and Q1 connect) just large enough to connect the components. To minimize excessive heating, large copper

pours can be placed adjacent to the short current path of the switch node.

• Route the CSP and CSN together with Kelvin connections to the current sense resistor with traces as short

as possible. If needed, use common mode and differential mode noise filters to attenuate switching and diode

reverse recovery noise from affecting the internal current sense amplifier.

• Because the COMP, IS, OV, DIM/PWM, and IADJ pins are all high-impedance inputs that couple external

noise easily, ensure that the loops containing these nodes are minimized whenever possible.

• In some applications, the LED or LED array can be far away from the TPS92692 and TPS92692-Q1 devices,

or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is

large or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the

effects of parasitic inductance on the AC impedance of the capacitor.

• The TPS92692 and TPS92692-Q1 devices have an exposed thermal pad to aid power dissipation. Adding

several vias under the exposed pad helps conduct heat away from the device. The junction-to-ambient

thermal resistance varies with application. The most significant variables are the area of copper in the PCB

and the number of vias under the exposed pad. The integrity of the solder connection from the device

exposed pad to the PCB is critical. Excessive voids greatly decrease the thermal dissipation capacity.

*9 TEXAS INSTRUMENTS FwOOmi 03m ._.wOOm_

VIN

FLT

VREF

COMP

IMON

INPUT

CONN

VCC

GND

GATE

OVP

CSP

SLOPE

CSN

VIN

LED+

GND

BUCK-BOOST

BOOST

VIA TO BOTTOM GROUND PLANE

IADJ

DIM

PDRV

RAMP

TPS92692Q

TPS92692

TPS92692-Q1

SLVSDD9 –MARCH 2017

www.ti.com

Product Folder Links: TPS92692 TPS92692-Q1

11.2 Layout Example

Figure 59. Layout Recommendation

l TEXAS INSTRUMENTS

TPS92692

TPS92692-Q1

www.ti.com

SLVSDD9 –MARCH 2017

Product Folder Links: TPS92692 TPS92692-Q1

12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 7. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

TPS92692 Click here Click here Click here Click here Click here

TPS92692-Q1 Click here Click here Click here Click here Click here

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS92692PWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 92692

TPS92692PWPT ACTIVE HTSSOP PWP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 92692

TPS92692QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 92692Q

TPS92692QPWPTQ1 ACTIVE HTSSOP PWP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 92692Q

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS92692, TPS92692-Q1 :

•Catalog: TPS92692

•Automotive: TPS92692-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS ‘3‘ V.'

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS92692PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

TPS92692QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS92692PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0

TPS92692QPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0

Pack Materials-Page 2

MECHANICAL DATA M 1“ AST‘C WAN OUT N’ NOTES, com» AH Hnec' d'vnensmrs c'e m m'hmekers Tm drawer ‘5 subje», ,0 change wnrau: name, Body dimensmns do nut mm mm ﬂcsh m aroms‘ms Mam am an: Drotrns'an she“ no: exceed ms pe' side ”‘3 pomagc \s CCS‘QHCd to be SO‘GL‘YQG to a “WWW pad on the boom Refer k) cchmm‘ HHcf, ’owc'Pad Tr'eurtu Erhuncec Fucmge‘ Texts \nst'mreuts Utemlue No S VAUOZ my Wow-um)" veguvcmg vecovrmenced buuvd \uyuLl Th5 duumen: Es uvu ub‘e u: wwwL r <‘vttu www="" uto'vv=""> See me accmonm hqure 'v the Jmmﬂ Dam Swee! ‘nr cams reqmdwg Me exaosed Mer'mﬂ pad features and mmensmns Fc‘s wwtmr JEDEC M0 153 PawevPAD is a trademalk 0! Texas \nurumems. {I} TEXAS INSTRUMENTS www.ti.com

THERMAL PAD MECHANICAL DATA PWP (RmPDSOmGZO) F’owerPADTM SMALL PLASTIC OUTLiNE THERMAL iNFORMATiON This PowerPAD‘“ package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board (PCB). The thermal pad must he soldered directly to the Peer After soldering. the PCB can be used as a heatsink. in addition, through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities. refer to Technical Brief, PowerPAD Thermally Enhanced Package. Texas instruments Literature Not SLMAOUZ and Application Brief PowerPAD Made Easy, Texas instruments Literature Na, SLMAOUIL Both documents are avaiinbie at www.ti.corn. The expased thermal pad dimensions for this package are shown in the following illustration iiiiiiiiii 1.15 MAX W p; a a FE LBJ—L HHiHHHHiHIHU 7 Exposed Thermal Pad Top View Exposed Thermui Pod Dimensions 4206332715/1‘0 01/15 NOTE: A. Ali iineur dimensions are in miliimeters A Exposed tie strap features may not be present. inIrPAD is a tndomark olT-xas instrumlnts {5i TEXAS INSTRUMENTS com

LAND PATTERN DATA PWP (R—PDSO—GZO) PowerPADW PLASTlC SMALL OUTLINE Example Board Layout Stencil Openln s_ Via pattern and copper pad size Based on a slencl‘t Ickness may vary dependlng on layout constraints 0' -tZ7mm (-005Inch)- Reference table below tor other l“”“5'“ae‘°we’ W“ W'” solder stencil thicknesses enhance t rmal performance (See Note D) ,3 4>T l—il8x0,65 20x0.25—— ‘— -—HHTHHHHTH 5.6 2,4 3.4 (See Note E) Y 2.4 _l x l 3.7 Solder: Mask Example Solder Mask _—|:| H :| H H H H [ H H as upper - <52:"l2tepé‘,dal l8x0.65»l="" l6="" 1/="" example="" i="" non="" saldermask="" defined="" pad="" '="" ‘/="" \‘\.="" example="" solder="" mask="" opening="" (see="" nme="" f)="" center="" power="" pud="" solder="" stencil="" opening="" stencil="" thickness="" x="" y="" 0.1mm="" 3.9="" 2.7="" 0.127rnrn="" 3.7="" 2.4="" pad="" geometry="" 0.152mm="" 3.5="" 2.2="" o="" 07="" 0.178mm="" 3.3="" 2.1="" 4207609s8/w="" 09/15="" notes:="" all="" llnear="" dimensions="" are="" ln="" millimeters="" thls="" drawing="" is="" subject="" to="" change="" without="" notice.="" customers="" should="" place="" a="" note="" on="" the="" circuit="" board="" raan'calian="" drawing="" not="" ta="" alter="" the="" center="" solder="" musk="" deﬁned="" pad.="" this="" package="" is="" deslgned="" to="" be="" soldered="" to="" a="" lnennal="" pad="" on="" the="" baard,="" reler="" to="" technical="" brier,="" powerpod="" thermally="" enhanced="" package.="" texas="" instruments="" literature="" no.="" slmaooz,="" slmaom,="" and="" also="" the="" product="" data="" sheets="" (or="" specific="" thermal="" information.="" via="" requirements.="" and="" recommended="" board="" layout.="" these="" documents="" are="" available="" at="" wwwtieam="">. Pablieatlen cherssl is recommended lor alternate deslgns. E. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should Contact their board assembly site tor stencil design recommendations. Example stencil design based on a 50% volumetric metal load Solder paste. Reler to |PCi7525 for other stencil recommendations, F. Customers should Contact their board fabrication site for solder mask tolerances between and around signal pads. 539?“? ' TEXAS INSTRUMENTS wwwltlcon

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