Datenblatt für 25AA512 von Microchip Technology

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2007-2018 Microchip Technology Inc. DS20002021G-page 1
25AA512
Device Selection Table
Features
• 20 MHz max. Clock Speed
• Byte and Page-level Write Operations:
- 128-byte page
-5 ms max.
- No page or sector erase required
• Low-Power CMOS Technology:
- Max. Write Current: 7 mA at 5.5V
- Read Current: 10 mA at 5.5V, 20 MHz
- Standby Current: 1A at 2.5V (Deep power-
down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write cycles:
- Page Erase (5 ms, typical)
- Sector Erase (10 ms/sector, typical)
- Bulk Erase (10 ms, typical)
• Sector Write Protection (16K byte/sector):
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1 Million erase/write cycles
- Data Retention: >200 years
- ESD Protection: 4000V
• Temperature Ranges Supported:
- Industrial (I):-40°C to +85°C
• Pb-free and RoHS Compliant
• Automotive AECQ-100 Qualified
Pin Function Table
Description
The Microchip Technology Inc. 25AA512 is a 512 Kbit
serial EEPROM memory with byte-level and page-level
serial EEPROM functions. It also features Page, Sector
and Chip erase functions typically associated with
Flash-based products. These functions are not required
for byte or page write operations. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled by a
Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25AA512 is available in standard packages includ-
ing 8-lead PDIP, SOIC, and advanced 8-lead DFN
package. All packages are Pb-free and RoHS
compliant.
Package Types (not to scale)
Part Number VCC Range Page Size Temp. Ranges Packages
25AA512 1.8-5.5V 128 Byte I P, SN, SM, MF
Name Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
VCC Supply Voltage
25AA512
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC/SOIJ
(P, SN, SM)
DFN
CS
SO
WP
VSS
HOLD
SCK
SI
25AA512
5
6
7
8
4
3
2
1VCC
(MF)
512 Kbit SPI Bus Serial EEPROM
exiended peiiod oi lime may aifect device reliability.
2007-2018 Microchip Technology Inc. DS20002021G-page 2
25AA512
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
*Limited industrial temp range.
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D001 VIH1High-level input
voltage .7 VCC VCC +1 V
D002 VIL1Low-level input
voltage -0.3 0.3 VCC VVCC2.7V
D003 VIL2-0.3 0.2 VCC VVCC < 2.7V
D004 VOL Low-level output
voltage —0.4VIOL = 2.1 mA
D005 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V
D006 VOH High-level output
voltage VCC -0.2 — V IOH = -400 A
D007 ILI Input leakage current — ±1 ACS = VCC, VIN = VSS TO VCC
D008 ILO Output leakage
current —±1ACS = VCC, VOUT = VSS TO VCC
D009 CINT Internal capacitance
(all inputs and
outputs)
—7pFTA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
D010 ICC Read
Operating current
—
—10
5
mA
mA
VCC = 5.5V; FCLK = 20.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 10.0 MHz;
SO = Open
D011 ICC Write —
—7
5mA
mA VCC = 5.5V
VCC = 2.5V
D012 ICCS
Standby current —
—10 AC
S = VCC = 5.5V, Inputs tied to VCC or
VSS, 85°C
D13 ICCSPD Deep power-down
current —1ACS = VCC = 2.5V, Inputs tied to VCC or
VSS, 85°C
Note: This parameter is periodically sampled and not 100% tested.
2007-2018 Microchip Technology Inc. DS20002021G-page 3
25AA512
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
*Limited industrial temp range.
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—
—
20
10
2
MHz
MHz
MHz
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
2T
CSS CS setup time 25
50
250
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
3T
CSH CS hold time 50
100
500
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
(Note 3)
4T
CSD CS disable time 50 — ns —
5 Tsu Data setup time 5
10
50
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
6THD Data hold time 10
20
100
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
7TRCLK rise time — 20 ns (Note 1)
8T
FCLK fall time — 20 ns (Note 1)
9THI Clock high time 25
50
250
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
10 TLO Clock low time 25
50
250
—
—ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
11 TCLD Clock delay time 50 — ns —
12 TCLE Clock enable time 50 — ns —
13 TVOutput valid from clock
low —
—
—
25
50
250
ns
ns
ns
4.5 VCC 5.5
2.8 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
14 THO Output hold time 0 — ns (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from Microchip’s website at www.microchip.com.
3: Includes THI time.
2007-2018 Microchip Technology Inc. DS20002021G-page 4
25AA512
15 TDIS Output disable time —
—
—
25
50
250
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
(Note 1)
16 THS HOLD setup time 10
20
100
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
17 THH HOLD hold time 10
20
100
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
18 THZ HOLD low to output
High-Z 15
30
150
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
(Note 1)
19 THV HOLD high to output
valid 15
30
150
—
—
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 5.5
1.8 VCC <2.5 at 0°C to +85°C
2.0 VCC <2.5 at -40°C to +85°C
20 TREL CS High to Standby
mode —100sVCC = 1.8V to 5.5V
21 TPD CS High to Deep power-
down —100sVCC = 1.8V to 5.5V
22 TCE Chip erase cycle time — 10 ms VCC = 1.8V to 5.5V
23 TSE Sector erase cycle time — 10 ms VCC = 1.8V to 5.5V
24 TWC Internal write cycle time — 5 ms Byte or Page mode and Page
Erase
25 — Endurance 1M — E/W
Cycles Page mode, 25°C, 5.5V (Note 2)
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V
*Limited industrial temp range.
Param.
No. Sym. Characteristic Min. Max. Units Conditions
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For endurance
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained
from Microchip’s website at www.microchip.com.
3: Includes THI time.
2007-2018 Microchip Technology Inc. DS20002021G-page 5
25AA512
TABLE 1-3: AC TEST CONDITIONS
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 30 pF —
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1:For VCC 4.0V
2: For VCC > 4.0V
CS
SCK
SO
SI
HOLD
1716 16 17
1918
Don’t Care 5
High-Impedance
n + 1 n n - 1n
nn - 1
1716 1716
1918 High-Impedance n - 2
n + 1 nn - 2
Don’t Care
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
_uj:1 X
2007-2018 Microchip Technology Inc. DS20002021G-page 6
25AA512
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
10
9
13
MSB out LSB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
\ H: :’
2007-2018 Microchip Technology Inc. DS20002021G-page 7
25AA512
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25AA512 is a 65,536 byte Serial EEPROM
designed to interface directly with the Serial Periph-
eral Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25AA512 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA512 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
BLOCK DIAGRAM
TABLE 2-1: INSTRUCTION SET
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
PE 0100 0010 Page Erase – erase one page in memory array
SE 1101 1000 Sector Erase – erase one sector in memory array
CE 1100 0111 Chip Erase – erase all sectors in memory array
RDID 1010 1011 Release from Deep power-down and read electronic signature
DPD 1011 1001 Deep Power-Down mode
2007-2018 Microchip Technology Inc. DS20002021G-page 8
25AA512
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA512 fol-
lowed by the 16-bit address. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (FFFFh), the address counter rolls
over to address 0000h allowing the read cycle to be
continued indefinitely. The READ instruction is
terminated by raising the CS pin (Figure 2-1).
FIGURE 2-1: READ SEQUENCE
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
Instruction 16-bit Address
Data Out
High-Impedance
2007-2018 Microchip Technology Inc. DS20002021G-page 9
25AA512
2.2 Write Sequence
Prior to any attempt to write data to the 25AA512, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25AA512. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
A write sequence includes an automatic, self timed
erase cycle. It is not required to erase any portion of the
memory prior to issuing a WRITE instruction.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruc-
tion, followed by the 16-bit address, and then the data
to be written. Up to 128 bytes of data can be sent to the
device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
FIGURE 2-2: BYTE WRITE SEQUENCE
Note: When doing a write of less than 128 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note: Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’), and end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
SO
SI
CS
91011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte
High-Impedance
SCK
0 23456718
Twc
2007-2018 Microchip Technology Inc. DS20002021G-page 10
25AA512
FIGURE 2-3: PAGE WRITE SEQUENCE
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n (128 max)
SCK
32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
2007-2018 Microchip Technology Inc. DS20002021G-page 11
25AA512
2.3 Write Enable (WREN) and Write
Disable (WRDI)
The 25AA512 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•PE instruction successfully executed
•SE instruction successfully executed
•CE instruction successfully executed
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
0
2007-2018 Microchip Technology Inc. DS20002021G-page 12
25AA512
2.4 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2: STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
25AA512 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
7 654 3 2 1 0
W/R –––W/RW/R R R
WPEN X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9101112131415
11000000
7654 210
Instruction
Data from STATUS Register
High-Impedance
SCK
0 23456718
3
2007-2018 Microchip Technology Inc. DS20002021G-page 13
25AA512
2.5 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3: ARRAY PROTECTION
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1 BP0 Array Addresses
Write-Protected Array Addresses
Unprotected
00 none All (Sectors 0, 1, 2 & 3)
(0000h-FFFFh)
01
Upper 1/4 (Sector 3)
(C000h-FFFFh) Lower 3/4 (Sectors 0, 1 & 2)
(0000h-BFFFh)
10
Upper 1/2 (Sectors 2 & 3)
(8000h-FFFFh) Lower 1/2 (Sectors 0 & 1)
(0000h-7FFFh)
11
All (Sectors 0, 1, 2 & 3)
(0000h-FFFFh) none
SO
SI
CS
9101112131415
01000000
7654 210
Instruction Data to STATUS Register
High-Impedance
SCK
0 23456718
3
2007-2018 Microchip Technology Inc. DS20002021G-page 14
25AA512
2.6 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.7 Power-On State
The 25AA512 powers on in the following state:
• The device is in low-power Standby mode
(CS =1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1) WPEN
(SR bit 7) WP
(pin 3) Protected Blocks Unprotected Blocks STATUS Register
0xxProtected Protected Protected
10xProtected Writable Writable
110 (low) Protected Writable Protected
111 (high) Protected Writable Writable
x = don’t care
2007-2018 Microchip Technology Inc. DS20002021G-page 15
25AA512
2.8 PAGE ERASE
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable (WREN) instruc-
tion must be given prior to attempting a PAGE ERASE.
This is done by setting CS low and then clocking out
the proper instruction into the 25AA512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits
(BP0, BP1) then the sequence will be aborted and no
erase will occur.
FIGURE 2-8: PAGE ERASE SEQUENCE
SO
SI
SCK
CS
0 234567891011 2122231
0000010115 14 13 12 210
Instruction 16-bit Address
High-Impedance
2007-2018 Microchip Technology Inc. DS20002021G-page 16
25AA512
2.9 SECTOR ERASE
The SECTOR ERASE instruction will erase all bits
(FFh) inside the given sector. A Write Enable (WREN)
instruction must be given prior to attempting a SECTOR
ERASE. This is done by setting CS low and then clock-
ing out the proper instruction into the 25AA512. After
all eight bits of the instruction are transmitted, the CS
must be brought high to set the write enable latch.
The SECTOR ERASE instruction is entered by driving
CS low, followed by the instruction code (Figure 2-9)
and two address bytes. Any address inside the sector
to be erased is a valid address.
CS must then be driven high after the last bit of the
address or the SECTOR ERASE will not execute. Once
the CS is driven high the self-timed SECTOR ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the SECTOR ERASE
cycle is complete.
If a SECTOR ERASE instruction is given to an address
that has been protected by the Block Protect bits
(BP0, BP1) then the sequence will be aborted and no
erase will occur.
See Table 2-3 for Sector Addressing.
FIGURE 2-9: SECTOR ERASE SEQUENCE
SO
SI
SCK
CS
0 234567891011 2122231
0011011015 14 13 12 210
Instruction 16-bit Address
High-Impedance
2007-2018 Microchip Technology Inc. DS20002021G-page 17
25AA512
2.10 CHIP ERASE
The CHIP ERASE instruction will erase all bits (FFh) in
the array. A Write Enable (WREN) instruction must be
given prior to executing a CHIP ERASE. This is done
by setting CS low and then clocking out the proper
instruction into the 25AA512. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The CHIP ERASE instruction is entered by driving the
CS low, followed by the instruction code (Figure 2-10)
onto the SI line.
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the CHIP
ERASE instruction will not be executed. Once the CS
pin is driven high the self-timed CHIP ERASE instruc-
tion begins. While the device is executing the CHIP
ERASE instruction the WIP bit in the STATUS register
can be read to determine when the CHIP ERASE
instruction is complete.
The CHIP ERASE instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ¼,
½, or all of the array is protected.
FIGURE 2-10: CHIP ERASE SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
111000 11
2007-2018 Microchip Technology Inc. DS20002021G-page 18
25AA512
2.11 DEEP POWER-DOWN MODE
Deep Power-Down mode of the 25AA512 is its lowest
power consumption state. The device will not respond
to any of the Read or Write commands while in Deep
Power-Down mode, and therefore it can be used as an
additional software write protection feature.
The Deep Power-Down mode is entered by driving CS
low, followed by the instruction code (Figure 2-11) onto
the SI line, followed by driving CS high.
If the CS pin is not driven high after the eighth bit of
the instruction code has been given, the device will not
execute Deep power-down. Once the CS line is driven
high there is a delay (TDP) before the current settles to
its lowest consumption.
All instructions given during Deep Power-Down mode
are ignored except the Read Electronic Signature
command (RDID). The RDID command will release
the device from Deep power-down and outputs the
electronic signature on the SO pin, and then returns
the device to Standby mode after delay (TREL)
Deep Power-Down mode automatically releases at
device power-down. Once power is restored to the
device it will power-up in the Standby mode.
FIGURE 2-11: DEEP POWER-DOWN SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
100111 10
2007-2018 Microchip Technology Inc. DS20002021G-page 19
25AA512
2.12 RELEASE FROM DEEP
POWER-DOWN AND READ
ELECTRONIC SIGNATURE
Once the device has entered Deep Power-Down
mode all instructions are ignored except the Release
from Deep Power-down and Read Electronic Signa-
ture command. This command can also be used when
the device is not in Deep power-down to read the
electronic signature out on the SO pin unless another
command is being executed such as Erase, Program
or Write Status Register.
Release from Deep Power-Down mode and Read
Electronic Signature is entered by driving CS low,
followed by the RDID instruction code (Figure 2-12)
and then a dummy address of 16 bits (A15-A0). After
the last bit of the dummy address is clock in, the 8-bit
Electronic Signature is clocked out on the SO pin.
After the signature has been read out at least once,
the sequence can be terminated by driving CS high.
After a delay of TREL, the device will then return to
Standby mode and will wait to be selected so it can be
given new instructions. If additional clock cycles are
sent after the electronic signature has been read once,
it will continue to output the signature on the SO line
until the sequence is terminated.
FIGURE 2-12: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure
the device will be taken out of Deep Power-Down mode, as shown in Figure 2-13.
FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
01101011
15 14 13 12 210
76543210
Instruction 16-bit Address
Electronic Signature Out
High-Impedance
0 1010010
Manufacturer’s ID = 0x29
T
REL
SO
SI
SCK
CS
0 2345671
01101011
Instruction
High-Impedance
TREL
2007-2018 Microchip Technology Inc. DS20002021G-page 20
25AA512
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25AA512.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
3.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25AA512 in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
3.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25AA512. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25AA512 while in the middle of a serial sequence with-
out having to re-transmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence.
The HOLD pin should be brought low while SCK is low,
otherwise the HOLD function will not be invoked until
the next SCK high-to-low transition. The 25AA512 must
remain selected during this sequence. The SI and SCK
levels are “don’t cares” during the time the device is
paused and any transitions on these pins will be
ignored. To resume serial communication, HOLD
should be brought high while the SCK pin is low, other-
wise serial communication will not be resumed until the
next SCK high-to-low transition.
The SO line will tri-state immediately upon a high-to-
low transition of the HOLD pin, and will begin outputting
again immediately upon a subsequent low-to-high
transition of the HOLD pin, independent of the state of
SCK.
Name Pin Number Function
CS 1 Chip Select Input
SO 2 Serial Data Output
WP 3 Write-Protect Pin
VSS 4 Ground
SI 5 Serial Data Input
SCK 6 Serial Clock Input
HOLD 7 Hold Input
VCC 8 Supply Voltage
Note: The exposed pad on DFN package
can be connected to VSS or left
floating.
o 0‘5 06‘ 0° HHHH 0‘3 ofi‘ UUUU HUM HHHH NNN 06 0% W UUUU NNN
2007-2018 Microchip Technology Inc. DS20002021G-page 21
25AA512
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC
XXXXYYWW
XXXXXXXT
NNN
I/P 1L7
25AA512
0728
Example:
Example:
SN 0728
25AA512I
1L7
8-Lead DFN Example:
XXXXXXX
T/XXXXX
YYWW
25AA512
I/MF
0728
1L7
NNN
Legend: XX...X Part number or part number code
T Temperature (I)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
8-Lead SOIJ
T/XXXXXX
XXXXXXXX
YYWWNNN
Example:
I/SM
25AA512
3
e
3
e
07281L7
2007-2018 Microchip Technology Inc. DS20002021G-page 22
25AA512
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1RWHV
 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV
 3DFNDJHLVVDZVLQJXODWHG
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3LWFK H %6&
2YHUDOO+HLJKW $   
6WDQGRII $   
&RQWDFW7KLFNQHVV $ 5()
2YHUDOO/HQJWK ' %6&
2YHUDOO:LGWK ( %6&
([SRVHG3DG/HQJWK '   
([SRVHG3DG:LGWK (   
&RQWDFW:LGWK E   
&RQWDFW/HQJWK /   
&RQWDFWWR([SRVHG3DG .  ± ±
NOTE 2
A1
A
A3
NOTE 1 12
E
N
D
EXPOSED PAD
NOTE 1
21
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
8-Lead Plasfic Dual FIaL No Lead Package (MF) - 6x5 mm Body [DFN-S] T2 —»“<— x1="" *wuue“="" s‘lk="" screen="" recommended="" land="" pattern="" note'="" this="" package="" may="" also="" be="" used="" w‘th="" the="" el="" soxc="" (3="" 90="" mm)="" land="" pattern="" unils="" m‘llimeters="" dimensxon="" limils="" nhn="" \="" nom="" \="" max="" cumact="" pitch="" e="" 1.27="" asc="" omicna‘="" center="" pad="" width="" w2="" 2="" 40="" ophena‘="" center="" pad="" length="" t2="" 4="" 10="" contam="" pan="" spacing="" c="" 5="" 60="" cumact="" pad="" width="" (x8)="" x1="" 0="" 45="" comact="" pad="" length="" (x3)="" y1="" 1="" 10="" notes="" 1.="" dxmenswomng="" and="" mlerancmg="" perasme="" y14.5m="" bsc:="" baswc="" dwmension.="" theareticahy="" exact="" vame="" shown="" without="" tolerances.="" mmcmp="" techno‘ogy="" drawing="" no="" 00472122a="">
2007-2018 Microchip Technology Inc. DS20002021G-page 23
25AA512
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
2007-2018 Microchip Technology Inc. DS20002021G-page 24
25AA512
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2007-2018 Microchip Technology Inc. DS20002021G-page 25
25AA512
A <7 n="" note="" 5="" note1="" ii="" 2'="" i="" a="" a2="" i="" seating="" 7777777777="" plane="" 8x="" e-i="" a1="" —="" side="" view="" see="" view="" c="" view="" a—a="" p="" microchip="" technoiogy="" drawing="" n="">
2007-2018 Microchip Technology Inc. DS20002021G-page 26
25AA512
0.25 CA–B D
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
VIEW A–A
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
12
N
h
h
A1
A2
A
A
B
e
D
E
E
2
E1
2
E1
NOTE 5
NOTE 5
NX b
0.10 CA–B
2X
H0.23
(L1)
L
R0.13
R0.13
VIEW C
SEE VIEW C
NOTE 1
D
2007-2018 Microchip Technology Inc. DS20002021G-page 27
25AA512
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°
Mold Draft Angle Bottom
15°-5°
Mold Draft Angle Top
0.51-0.31
b
Lead Width
0.25-0.17
c
Lead Thickness
1.27-0.40LFoot Length
0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
§
Footprint L1 1.04 REF
5. Datums A & B to be determined at Datum H.
/ QQQE I .Q Q Q E : DH
2007-2018 Microchip Technology Inc. DS20002021G-page 28
25AA512
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev B
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIJ] E1/2 q. i i I i H \ \\\\ \Q\\ \\ \ \ \ / / / Q 0.10 c D /%/////J l 2x N/2 TIPS NOTE1 1 2 ‘ N/2 3-- 9/2 —»1 } . e \ |._ a f m TOP VIEW A'5 E WA‘j A M W 5-6 1 _,7 iSEATING PLANE A A‘ 7 SIDE VIEW V» 4 m =J E g 9’ L VIEW A-A Mlcmcmp Technology Drawmg co4-ossc Sheet 1 of 2
2007-2018 Microchip Technology Inc. DS20002021G-page 29
25AA512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIJ] Unlls MlLLIMETERS Dlmensmn Limlls MIN | NOM | MAX Number of Plns N a Pllch e 1.27 BSC Overall Height A 1 77 , 2 03 Standofl § A1 0 05 o 25 Molded Package Thickness AZ 1 75 - 1 BB Overall Wldlh E 7.94 580 Molded Package Wldlh E1 5.25 550 Overall Lengm D 5.26 BSC Foo! Length L 0 51 , D 76 Lead Thickness C 0 15 - 0 25 Lead Width b 0.35 — 0.51 Mold Draft Angle 91 . . 15“ Lead Angle 02 0“ . 8“ Foo! Angle 63 0“ . 5° Notes' 1 SOIJ,JE|TA/E1AJ Slandam. Formerly called SOIC 2 §Signlllcam Chalaclerislic a Dlmenslons D and E1 do not lrlclude mold flash or prulmslons Mold flash or protmsluns shall n01 EXCEEd 0 25mm per slde Microenlp Technology Drawing No. COAVOSSC Sheet 2 M2
2007-2018 Microchip Technology Inc. DS20002021G-page 30
25AA512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIJ] :13 EM z1c1e1 D / S‘LK SCREEN DU; ——E<— _.‘="" l—="" x1="" recommended="" land="" pattern="" umts="" milumeters="" d1men5|on="" ants="" min="" \="" nom="" \="" max="" contact="" pncn="" e="" 1="" 27="" bsc="" overau="" wmn="" z1="" 9="" 00="" contact="" pad="" spacmg="" c1="" 7="" 30="" contact="" pad="" wmm="" (x8)="" x1="" 0.65="" contact="" pad="" length="" txs)="" y1="" 1.70="" distance="" between="" pads="" (31="" 5.60="" distance="" between="" pads="" 6="" 0.62="" nolas.="" 1="" d1mens1onlng="" and="" toteranclng="" per="" asme="" v14="" sm="" 380.="" basic="" dimens1on.thecret1ca\ly="" exacl="" value="" shown="" w1thoul="" (o‘erances.="" microcmp="" technology="" drawmg="" no.="" 304720550="">
2007-2018 Microchip Technology Inc. DS20002021G-page 31
25AA512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2007-2018 Microchip Technology Inc. DS20002021G-page 32
25AA512
APPENDIX A: REVISION HISTORY
Revision A
Original release.
Revision B (06/2007)
Revised Device Selection Table; Revised Features
section; Revised Table 1-1 DC Characteristics;
Revised Table 1-2 AC Characteristics; Replaced Pack-
age Drawings (Rev. AP); Revised Package Marking
(SOIC, SOIJ); Revised Product ID section.
Revision C (10/2007)
Removed 25LC512 part number; New data sheet
created for 25LC512 (DS22065); Revised Tables;
Updates throughout.
Revision D (03/2008)
Revise Figures 2-11 and 2-12; Revise title to Figure
2-13; Update Package Drawings.
Revision E (5/2008)
Modified parameter D006 in Table 1-1; Revised
Package Marking Information; Replaced Package
Drawings; Revised Product ID section.
Revision F (05/2010)
Revised Table 1-2, Param. No. 25 Conditions;
Revised Section 2.2, added note; Added SOIC Land
Pattern and updated SOIJ package drawings.
Revision G (06/2018)
Updated Features section; Updated Figures 2-8, 2-9
and 2-12; Updated Table 3-1; Updated Package Draw-
ings.
2007-2018 Microchip Technology Inc. DS20002021G-page 33
25AA512
THE MICROCHIP WEBSITE
Microchip provides online support via our WWW site at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
PART NO. /X)(
2007-2018 Microchip Technology Inc. DS20002021G-page 34
25AA512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTape & Reel
Device
Device: 25AA512 512 Kbit, 1.8V, 128-Byte Page SPI Serial EEPROM
Tape & Reel: Blank =
T=
Standard packaging (tube)
Tape & Reel
Temperature
Range: I=-40C to+85C
Package: MF =
P=
SN =
SM =
Micro Lead Frame (6 x 5 mm body), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic SOIJ (5.28 mm body), 8-lead
Examples:
a) 25AA512-I/SN = 512 Kbit, 1.8V Serial
EEPROM, Industrial temp., SOIC package
b) 25AA512T-I/SM = 512 Kbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIJ
package
c) 25AA512T-I/MF = 512 Kbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, DFN
package
–
Note: Contact Microchip for Automotive grade
ordering part numbers.
X
Temp Range
YSTEM
2007-2018 Microchip Technology Inc. DS20002021G-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-3253-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ ‘MICRDCHIP
2007-2018 Microchip Technology Inc. DS20002021G-page 36
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10/25/17