Datenblatt für TSV911, 912, 914 von Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS
ZLOAD
+
RSHUNT
0.1
VBUS
5 V
RF
165 k
RG
3.4 k
VOUT
ILOAD
TSV91x
VSHUNT
0
10
20
30
40
50
60
0 50 100 150 200 250 300
Overshoot (%)
Capacitive Load (pF)
Overshoot+
Overshoot-
C025
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
TSV91x Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers
1
1 Features
1• Rail-to-rail input and output
• Low noise: 18 nV/√Hz at 1 kHz
• Low power consumption: 550 µA (typical)
• High-gain bandwidth: 8 MHz
• Operating supply voltage from 2.5 V to 5.5 V
• Low input bias current: 1 pA (typical)
• Low input offset voltage: 1.5 mV (maximum)
• Low offset voltage drift: ±0.5 µV/°C (typical)
• ESD internal protection: ±4-kV human-body model
(HBM)
• Extended temperature range: –40°C to 125°C
2 Applications
• Battery-powered applications
• Motor control
• Power modules
• HVAC: heating, ventilating, and air conditioning
• Washing machines
• Refrigerators
• Medical instrumentation
• Active filters
• Sensor signal conditioning
• Audio receiver
• Automotive infotainment
3 Description
The TSV91x family, which includes single-, dual-, and
quad-channel operational amplifiers (op amps), is
specifically designed for general-purpose
applications. Featuring rail-to-rail input and output
(RRIO) swings, wide bandwidth (8 MHz), and low
offset voltage (0.3 mV, typical), this family is designed
for a variety of applications that require a good
balance between speed and power consumption. The
op amps are unity-gain stable and feature an ultra-
low input bias current, which enables the family to be
used in applications with high-source impedances.
The low input bias current allows the devices to be
used for sensor interfaces, battery-supplied and
portable applications, and active filtering.
The robust design of the TSV91x provides ease-of-
use to the circuit designer. Features include a unity-
gain stable, integrated RFI-EMI rejection filter, no
phase reversal in overdrive condition, and high
electrostatic discharge (ESD) protection (4-kV HBV).
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TSV911 SOT-23 (5) 1.60 mm × 2.90 mm
SC70 (5) 1.25 mm × 2.00 mm
TSV912
SOIC (8) 3.91 mm × 4.90 mm
WSON (8) 2.00 mm × 2.00 mm
SOT-23 (8) 1.60 mm × 2.90 mm
TSV914 SOIC (14) 8.65 mm × 3.91 mm
TSSOP (14) 4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Low-Side Motor Control Small-Signal Overshoot vs Load Capacitance
l TEXAS INSTRUMENTS
2
TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions......................... 5
7 Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information: TSV911................................... 8
7.5 Thermal Information: TSV912................................... 9
7.6 Thermal Information: TSV914................................... 9
7.7 Electrical Characteristics: VS(Total Supply Voltage) =
(V+) – (V–) = 2.5 V to 5.5 V..................................... 10
7.8 Typical Characteristics............................................ 12
8 Detailed Description............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
9 Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 22
10.1 Input and ESD Protection ..................................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1 Documentation Support ........................................ 24
12.2 Related Links ........................................................ 24
12.3 Receiving Notification of Documentation Updates 24
12.4 Community Resources.......................................... 24
12.5 Trademarks........................................................... 24
12.6 Electrostatic Discharge Caution............................ 24
12.7 Glossary................................................................ 24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision C (January 2019) to Revision D Page
• Added SOT-23 (8) (DDF) package information to data sheet................................................................................................ 1
Changes from Revision B (April 2018) to Revision C Page
• Deleted preview notations for TSV911IDBV ......................................................................................................................... 1
• Added SC70 package information to Device Information table.............................................................................................. 1
• Deleted package preview notation from TSV911 DBV (SOT-23) package ........................................................................... 4
• Added DCK (SC70) package information to Device Comparison Table................................................................................ 4
• Deleted TSV911 DBV (SOT-23) package preview notation from Pin Configuration and Functions section.......................... 5
• Added TSV911 DCK (SC70) package drawing and pin functions ........................................................................................ 5
• Added TSV911 DBV and DCK package thermal information................................................................................................. 8
Changes from Revision A (October 2017) to Revision B Page
• Changed TSV914 14-pin TSSOP package from preview to production data in Device Information table ............................ 1
• Deleted package preview note from 8-pin WSON package in Device Information table ...................................................... 1
• Deleted package preview note from PW (TSSOP) package from Device Comparison table ............................................... 4
• Deleted package preview note from DSG (WSON) package from Device Comparison table............................................... 4
• Deleted package preview note from TSV912 DSG package pinout drawing in Pin Configuration and Functions section.... 6
• Added DGK (VSSOP) thermal information to Thermal Information: TSV912 table .............................................................. 9
• Deleted package preview note to TSV914 PW (TSSOP) package Thermal Information table.............................................. 9
• Added PW (TSSOP) package information to Thermal Information: TSV914 table................................................................ 9
• Changed TSV914 PW (TSSOP) junction-to-ambient thermal resistance from 135.8°C/W to 205.8°C/W............................. 9
• Changed TSV914 PW (TSSOP) junction-to-case(top) thermal resistance from 64°C/W to 106.7°C/W................................ 9
• Changed TSV914 PW (TSSOP) junction-to-board thermal resistance from 79°C/W to 133.9°C/W...................................... 9
l TEXAS INSTRUMENTS
3
TSV911
,
TSV912
,
TSV914
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SBOS878D –JULY 2017–REVISED OCTOBER 2019
Product Folder Links: TSV911 TSV912 TSV914
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• Changed TSV914 PW (TSSOP) junction-to-top characterization parameter from 15.7°C/W to 34.4°C/W ........................... 9
• Changed TSV914 PW (TSSOP) junction-to-board characterization parameter from 78.4°C/W to 132.6°C/W ..................... 9
Changes from Original (July 2017) to Revision A Page
• Changed TSV914 14-pin SOIC package from preview to production data in Device Information table................................ 1
• Deleted TSV911 SC70, SOT-553 and SOIC packages from Device Information table ........................................................ 1
• Deleted TSV912 VSSOP packages from Device Information table ...................................................................................... 1
• Deleted TSV911 SC70 and SOIC packages from pinout drawings and Pin Functions table ................................................ 5
• Deleted TSV912 DGK and DGS packages from pinout images Pin Functions table ............................................................ 6
• Deleted package preview note from TSV914 pinout drawing and Pin Functions table ........................................................ 7
• Added TSV914 Thermal Information table ............................................................................................................................ 9
• Added 2017 copyright notice to Figure 35............................................................................................................................ 20
l TEXAS INSTRUMENTS
4
TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
www.ti.com
Product Folder Links: TSV911 TSV912 TSV914
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5 Device Comparison Table
DEVICE NO. OF
CHANNELS
PACKAGE LEADS
DBV DCK D DSG PW DDF
TSV911 1 5 5 — — — —
TSV912 2 — — 8 8 — 8
TSV914 4 — — 14 — 14 —
l TEXAS INSTRUMENTS WWW 4% U U U] HHH
1IN+
2V±
3IN±4 OUT
5 V+
Not to scale
5
TSV911
,
TSV912
,
TSV914
www.ti.com
SBOS878D –JULY 2017–REVISED OCTOBER 2019
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6 Pin Configuration and Functions
TSV911 DBV Package
5-Pin SOT-23
Top View
TSV911 DCK Package
5-Pin SC70
Top View
Pin Functions: TSV911
PIN
I/O DESCRIPTION
NAME NO.
DBV (SOT-23) DCK (SC70)
–IN 4 3 I Inverting input
+IN 3 1 I Noninverting input
OUT 1 4 O Output
V– 2 2 — Negative (lowest) supply or ground (for single-supply operation)
V+ 5 5 — Positive (highest) supply
‘5‘ TEXAS INSTRUMENTS flflflfl UUUU _______
OUT A
-IN A
+IN A
V-
1
2
3
4
V+
OUT B
-IN B
+IN B
8
7
6
5
Exposed
Thermal
Die Pad
on
Underside(1)
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
6
TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
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TSV912 D, DGK, DDF Packages
8-Pin SOIC, VSSOP
Top View TSV912 DSG Package (1)
8-Pin WSON With Exposed Thermal Pad
Top View
(1) Connect exposed thermal pad to V–. See
Packages with an Exposed Thermal Pad
section for more information.
Pin Functions: TSV912
PIN I/O DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 — Negative (lowest) supply or ground (for single-supply operation)
V+ 8 — Positive (highest) supply
‘5‘ TEXAS INSTRUMENTS
1
2
3
4
14
13
12
11
OUTD
-IND
+IND
V-
OUTA
-INA
+INA
V+
5
6
7
10
9
8
+INC
-INC
OUTC
+INB
-INB
OUTB
A
B
D
C
7
TSV911
,
TSV912
,
TSV914
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TSV914 D, PW Packages
14-Pin SOIC, TSSOP
Top View
Pin Functions: TSV914
PIN I/O DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
–IN C 9 I Inverting input, channel C
+IN C 10 I Noninverting input, channel C
–IN D 13 I Inverting input, channel D
+IN D 12 I Noninverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V– 11 — Negative (lowest) supply or ground (for single-supply operation)
V+ 4 — Positive (highest) supply
l TEXAS INSTRUMENTS
8
TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
www.ti.com
Product Folder Links: TSV911 TSV912 TSV914
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 6 V
Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V
Differential (V+) – (V–) + 0.2
Current(2) –10 10 mA
Output short-circuit(3) Continuous mA
Specified, TA–40 125 °C
Junction, TJ150 °C
Storage, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VSSupply voltage 2.5 5.5 V
Specified temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information: TSV911
THERMAL METRIC(1)
TSV911
UNITDBV (SOT-23) DCK (SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 221.7 263.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 144.7 75.5 °C/W
RθJB Junction-to-board thermal resistance 49.7 51.0 °C/W
ψJT Junction-to-top characterization parameter 26.1 1.0 °C/W
ψJB Junction-to-board characterization parameter 49.0 50.3 °C/W
l TEXAS INSTRUMENTS
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TSV911
,
TSV912
,
TSV914
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SBOS878D –JULY 2017–REVISED OCTOBER 2019
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TSV912
THERMAL METRIC(1)
TSV912
UNITD (SOIC) DGK (VSSOP) DSG (WSON) DDF (SOT-23)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal
resistance 157.6 201.2 94.4 184.4 °C/W
RθJC(top) Junction-to-case(top) thermal
resistance 104.6 85.7 116.5 112.8 °C/W
RθJB Junction-to-board thermal resistance 99.7 122.9 61.3 99.9 °C/W
ψJT Junction-to-top characterization
parameter 55.6 21.2 13 18.7 °C/W
ψJB Junction-to-board characterization
parameter 99.2 121.4 61.7 99.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal
resistance N/A N/A 34.4 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TSV914
THERMAL METRIC(1)
TSV914
UNITD (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 106.9 205.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69 106.7 °C/W
RθJB Junction-to-board thermal resistance 63 133.9 °C/W
ψJT Junction-to-top characterization parameter 25.9 34.4 °C/W
ψJB Junction-to-board characterization parameter 62.7 132.6 °C/W
l TEXAS INSTRUMENTS
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TSV911
,
TSV912
,
TSV914
SBOS878D –JULY 2017–REVISED OCTOBER 2019
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Product Folder Links: TSV911 TSV912 TSV914
Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
7.7 Electrical Characteristics: VS(Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V
at TA= 25°C, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage
VS= 5 V ±0.3 ±1.5
mV
VS= 5 V
TA= –40°C to 125°C ±3
dVOS/dT Drift VS= 5 V
TA= –40°C to 125°C ±0.5 µV/°C
PSRR Power-supply rejection ratio VS= 2.5 V – 5.5 V, VCM = (V–) ±7 µV/V
Channel separation, DC At DC 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range VS= 2.5 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio
VS= 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA= –40°C to 125°C 80 103
dB
VS= 5.5 V, VCM = –0.1 V to 5.6 V
TA= –40°C to 125°C 57 87
VS= 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA= –40°C to 125°C 88
VS= 2.5 V, VCM = –0.1 V to 1.9 V
TA= –40°C to 125°C 81
INPUT BIAS CURRENT
IBInput bias current ±1 pA
IOS Input offset current ±0.05 pA
NOISE
EnInput voltage noise (peak-to-peak) VS= 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP
enInput voltage noise density VS= 5 V, f = 10 kHz 12 nV/√Hz
VS= 5 V, f = 1 kHz 18
inInput current noise density f = 1 kHz 10 fA/√Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain
VS= 2.5 V, (V–) + 0.04 V < VO< (V+) – 0.04 V
RL= 10 kΩ100
dB
VS= 5.5 V, (V–) + 0.05 V < VO< (V+) – 0.05 V
RL= 10 kΩ104 130
VS= 2.5 V, (V–) + 0.06 V < VO< (V+) – 0.06 V
RL= 2 kΩ100
VS= 5.5 V, (V–) + 0.15 V < VO< (V+) – 0.15 V
RL= 2 kΩ130
FREQUENCY RESPONSE
GBP Gain bandwidth product VS= 5 V, G = 1 8 MHz
φmPhase margin VS= 5 V, G = 1 55 °
SR Slew rate VS= 5 V, G = 1
RL= 2 kΩ
CL= 100 pF 4.5 V/µs
tSSettling time
To 0.1%, VS= 5 V, 2-V step , G = 1
CL= 100 pF 0.5
µs
To 0.01%, VS= 5 V, 2-V step , G = 1
CL= 100 pF 1
tOR Overload recovery time VS= 5 V, VIN × gain > VS0.2 µs
THD + N Total harmonic distortion + noise(1) VS= 5 V, VO= 1 VRMS, G = 1, f = 1 kHz 0.0008%
OUTPUT
VOVoltage output swing from supply
rails
VS= 5.5 V, RL= 10 kΩ15 mV
VS= 5.5 V, RL= 2 kΩ50
l TEXAS INSTRUMENTS
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TSV911
,
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,
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Electrical Characteristics: VS(Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V (continued)
at TA= 25°C, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISC Short-circuit current VS= 5 V ±50 mA
ZOOpen-loop output impedance VS= 5 V, f = 10 MHz 100 Ω
POWER SUPPLY
IQQuiescent current per amplifier VS= 5.5 V, IO= 0 mA 550 750 µA
VS= 5.5 V, IO= 0 mA TA= –40°C to 125°C 1100
l TEXAS INSTRUMENTS was ‘20 mo Supp‘y Vouage (V)
Frequency (Hz)
Open Loop Voltage Gain (dB)
Phase Margin (q)
-20 0
0 30
20 60
40 90
60 120
80 150
100 180
120 210
100 1k 10k 100k 1M 10M
C006
Gain
Phase
±1000
±500
0
500
1000
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Offset Voltage (µV)
Supply Voltage (V) C004
±500
±400
±300
±200
±100
0
100
200
300
400
500
±50 ±25 0 25 50 75 100 125 150
Offset Voltage (µV)
Temperature (ƒC)
C003
±2500
±2000
±1500
±1000
±500
0
500
1000
1500
2000
2500
-4 -3 -2 -1 0 1 2 3 4
Offset Voltage (µV)
Input Common Mode Voltage (V)
C005
0
5
10
15
20
25
30
35
-1500
-1250
-1000
-750
-500
-250
0
250
500
750
1000
1250
1500
Population (%)
Offset Voltage (µV)
C001
0
10
20
30
40
50
0
0.4
0.8
1.2
1.6
2
2.4
2.8
Population (%)
Offset Voltage Drift (µV/C)
C002
12
TSV911
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,
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7.8 Typical Characteristics
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
Figure 1. Offset Voltage Production Distribution
TA= –40°C to 125°C
Figure 2. Offset Voltage Drift Distribution
Figure 3. Offset Voltage vs Temperature
V+ = 2.75 V, V– = –2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
VS= 2.5 V to 5.5 V
Figure 5. Offset Voltage vs Power Supply
CL= 10 pF
Figure 6. Open-Loop Gain and Phase vs Frequency
l TEXAS INSTRUMENTS 7 // ( CH ' \ 5’ _ i 2: \ \‘ L1 \ 7 ‘ \ m )— \ k \ Wm
30
35
40
45
50
55
±50 ±25 0 25 50 75 100 125
CMRR (µV/V)
Temperature (ƒC)
C012
1
2
3
4
5
6
7
8
9
10
±50 ±25 0 25 50 75 100 125 150
CMRR (µV/V)
Temperature (ƒC)
C016
Frequency (Hz)
PSRR and CMRR (dB)
0
20
40
60
80
100
120
1k 10k 100k 1M 10M
C011
PSRR-
PSRR+
CMRR
±3
±2
±1
0
1
2
3
10 20 30 40 50 60
Output Voltage (V)
Output Current (mA)
C009
125ƒC
85ƒC 25ƒC
-40ƒC
125ƒC 85ƒC 25ƒC
-40ƒC
±50
0
50
100
150
200
250
±50 ±25 0 25 50 75 100 125
Input Bias Current and offset current (pA)
Temperature (ƒC)
IBN
IBP
IOS
C008
Frequency (Hz)
Closed Loop Voltage Gain (dB)
-40
-30
-20
-10
0
10
20
30
40
1k 10k 100k 1M 10M
C007
G = +1
G = +10
G = -1
13
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Typical Characteristics (continued)
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
Figure 7. Closed-Loop Gain vs Frequency Figure 8. Input Bias Current vs Temperature
V+ = 2.75 V, V– = –2.75 V
Figure 9. Output Voltage Swing vs Output Current Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)
VS= 5.5 V VCM = (V–) – 0.1 V to
(V+) + 0.1 V RL= 10 kΩ
TA= –40°C to 125°C
Figure 11. CMRR vs Temperature
VS= 5.5 V VCM = (V–) –0.1 V to
(V+) –1.4 V RL= 10 kΩ
TA= –40°C to 125°C
Figure 12. CMRR vs Temperature
l TEXAS INSTRUMENTS 120 790 ms ms
±120
±100
±80
±60
±40
0.001 0.01 0.1 1
THD + N (dB)
Output Voltage Amplitude (VRMS)
C018
±120
±100
±80
±60
±40
0.001 0.01 0.1 1
THD + N (dB)
Output Voltage Amplitude (VRMS)
C019
Frequency (Hz)
Input Voltage Noise
Spectral Density (nV/—Hz)
0
20
40
60
80
100
120
10 100 1k 10k 100k
C015
Frequency (Hz)
THD + N (dB)
-120
-115
-110
-105
-100
-95
-90
100 1k 10k
C017
5
6
7
8
9
10
±50 ±25 0 25 50 75 100 125
PSRR (µV/V)
Temperature (ƒC)
C013
Voltage (1µV/div)
Time (1s/div)
C014
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Typical Characteristics (continued)
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
VS= 2.5 V to 5.5 V
Figure 13. PSRR vs Temperature
VS= 2.5 V to 5.5 V
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 15. Input Voltage Noise Spectral Density vs
Frequency
VS= 5.5 V VCM = 2.5 V RL= 2 kΩ
G = 1 VOUT = 0.5 VRMS BW = 80 kHz
Figure 16. THD + N vs Frequency
VS= 5.5 V VCM = 2.5 V RL= 2 kΩ
G = 1 BW = 80 kHz f = 1 kHz
Figure 17. THD + N vs Amplitude
VS= 5.5 V VCM = 2.5 V RL= 2 kΩ
G = –1 BW = 80 kHz f = 1 kHz
Figure 18. THD + N vs Amplitude
l TEXAS INSTRUMENTS 200 / // ‘ / / /“ /“ /¢ / \ / \ / / \ / \
0
10
20
30
40
50
60
0 50 100 150 200 250 300
Overshoot (%)
Capacitive Load (pF)
Overshoot(+)
Overshoot(-)
C026
Voltage (1V/div)
Time (200 µs/div)
Input
Output
C036
Frequency (Hz)
Open Loop Output Impedance (:)
0
40
80
120
160
200
10k 100k 1M 10M
C024
0
10
20
30
40
50
60
0 50 100 150 200 250 300
Overshoot (%)
Capacitive Load (pF)
Overshoot+
Overshoot-
C025
500
520
540
560
580
600
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Quiescent current (µA)
Supply Voltage (V) C020
0
100
200
300
400
500
600
700
800
±50 ±25 0 25 50 75 100 125
Quiescent Current (µA)
Temperature (ƒC)
C021
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Typical Characteristics (continued)
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
Figure 19. Quiescent Current vs Supply Voltage Figure 20. Quiescent Current vs Temperature
Figure 21. Open-Loop Output Impedance vs Frequency
V+ = 2.75 V V– = –2.75 V G = 1 V/V
RL= 10 kΩVOUT step = 100 mVp-p
Figure 22. Small-Signal Overshoot vs Load Capacitance
V+ = 2.75 V V– = –2.75 V RL= 10 kΩ
G = –1 V/V VOUT step = 100 mVp-p
Figure 23. Small-Signal Overshoot vs Load Capacitance
V+ = 2.75 V, V– = –2.75 V
Figure 24. No Phase Reversal
l TEXAS INSTRUMENTS
Frequency (Hz)
Channel Seperation (dB)
-140
-120
-100
-80
-60
-40
-20
0
100 1k 10k 100k 1M 10M
C038
0
20
40
60
80
100
120
140
10M 100M 1G
EMIRR (dB)
Frequency (Hz)
C041
Voltage (1 V/div)
Time (1 µs/div)
Input
Output
C031
±80
±60
±40
±20
0
20
40
60
80
±50 ±25 0 25 50 75 100 125
Short Circuit Current Limit (mA)
Temperature (ƒC)
Sinking
Sourcing
C034
Voltage (20 mV/div)
Time (0.1µs/div)
Input
Output
C030
Voltage (2 V/V)
Time (1 µs/div)
INPUT
OUTPUT
C028
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Typical Characteristics (continued)
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
Figure 25. Overload Recovery
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
Figure 26. Small-Signal Step Response
V+ = 2.75 V V– = –2.75 V CL= 100 pF
G = 1 V/V
Figure 27. Large-Signal Step Response Figure 28. Short-Circuit Current vs Temperature
PRF = –10 dBm
Figure 29. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
V+ = 2.75 V, V– = –2.75 V
Figure 30. Channel Separation vs Frequency
l TEXAS INSTRUMENTS
±100
±75
±50
±25
0
25
50
75
100
0 0.3 0.6 0.9
Output Voltage (mV)
Settling time (µs)
C032
-150
-125
-100
-75
-50
-25
0
25
50
75
100
0 0.3 0.6 0.9 1.2 1.5
Output voltage (mV)
Settling time (µs)
C033
0
15
30
45
60
75
90
0 10 20 30 40 50 60 70 80 90 100
Phase Margin (degrees)
Capacitive Load (pF)
C037
0
40
80
120
160
200
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Open Loop Voltage Gain (dB)
Output Voltage (V)
C023
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Typical Characteristics (continued)
at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2 (unless otherwise noted)
VS= 5.5 V
Figure 31. Phase Margin vs Capacitive Load
VS= 5.5 V
Figure 32. Open Loop Voltage Gain vs Output Voltage
Figure 33. Large Signal Settling Time (Positive) Figure 34. Large Signal Settling Time (Negative)
‘‘‘‘‘‘‘‘‘‘ JWE :JFLK
Reference
Current
V+
VIN+ V
INÛ
VÛ
(Ground)
VBIAS2
VBIAS1 Class AB
Control
Circuitry
VO
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8 Detailed Description
8.1 Overview
The TSV91x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from
2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes both rails and allows the TSV91x series to be used in virtually any
single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
l TEXAS INSTRUMENTS
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TSV91x family extends 100 mV beyond the supply rails for the full
supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage: an N-
channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TSV91x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.3 Packages with an Exposed Thermal Pad
The TSV91x family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal pad.
Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this
reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or
left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of the
device is not assured when doing so.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TSV91x series is approximately 200 ns.
8.4 Device Functional Modes
The TSV91x family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
l TEXAS INSTRUMENTS
ZLOAD
+
RSHUNT
0.1
VBUS
5 V
RF
165 k
RG
3.4 k
VOUT
ILOAD
TSV91x
VSHUNT
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TSV91x series features 8-MHz bandwidth and 4.5-V/µs slew rate with only 550 µA of supply current per
channel, providing good AC performance at low power consumption. DC applications are well served with a low
input noise voltage of 18 nV / √Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.
9.2 Typical Application
Figure 35 shows the TSV91x configured in a low-side, motor-control application.
Figure 35. TSV91x in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
l TEXAS INSTRUMENTS V0 : \L >
0
1
2
3
4
5
0 0.2 0.4 0.6 0.8 1
Output (V)
ILOAD (A)
C219
 
F
G
R
Gain 1
R
 
 
_ _
_ _
OUT MAX OUT MIN
IN MAX IN MIN
V V
Gain
V V
_
_
SHUNT MAX
SHUNT
LOAD MAX
V100mV
R 100m
I 1A
:
OUT LOAD SHUNT
V I R Gain u u
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 35 is shown in Equation 1.
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
(2)
Using Equation 2, RSHUNT is 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the TSV91x
to produce an output voltage of approximately 0 V to 4.95 V. The gain required by the TSV91x to produce the
necessary output voltage is calculated using Equation 3:
(3)
Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RFand RG.
Equation 4 is used to size the resistors, RFand RG, to set the gain of the TSV91x to 49.5 V/V.
(4)
Selecting RFas 165 kΩand RGas 3.4 kΩprovides a combination that equals roughly 49.5 V/V. Figure 36 shows
the measured transfer function of the circuit shown in Figure 35.
9.2.3 Application Curve
Figure 36. Low-Side, Current-Sense, Transfer Function
l TEXAS INSTRUMENTS c
5 kW
10-mA maximum
V+
VIN
VOUT
IOVERLOAD
Device
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10 Power Supply Recommendations
The TSV91x series is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Example section.
10.1 Input and ESD Protection
The TSV91x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection consists of current-steering diodes connected between the input and power-supply pins. These ESD
protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-mA, as
stated in the Absolute Maximum Ratings table. Figure 37 shows how a series input resistor is added to the driven
input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value
must be kept to a minimum in noise-sensitive applications.
Figure 37. Input Current Protection
OUT A
-IN A
+IN A
V±
OUT B
-IN B
+IN B
V+
VS±
GND
Ground (GND) plane on another layer
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Place components
close to device and to
each other to reduce
parasitic errors.
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VIN A
GND
RF
RG
VIN B
GND
RF
RG
VS+
GND
OUT A
OUT B
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
+
VIN B
VOUT B
RG
RF
+
VIN A
VOUT A
RG
RF
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 39, keeping RF
and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
Figure 38. Schematic Representation for Figure 39
Figure 39. Layout Example
l TEXAS INSTRUMENTS
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Circuit Board Layout Techniques, SLOA089
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TSV911 Click here Click here Click here Click here Click here
TSV912 Click here Click here Click here Click here Click here
TSV914 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Sep-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TSV911AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1U2F
TSV911AIDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1EK
TSV912AIDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T12A
TSV912AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T912
TSV912AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T912
TSV912AIDR ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TSV912
TSV912AIDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T912
TSV912AIDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T912
TSV912AIPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TSV912
TSV914AIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AD
TSV914AIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TSV914
TSV914AIPWT ACTIVE TSSOP PW 14 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TSV914
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 28-Sep-2021
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TSV911AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TSV911AIDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TSV912AIDDFR SOT-
23-THIN DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TSV912AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TSV912AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TSV912AIDR SOIC D 8 2500 330.0 15.4 6.4 5.2 2.1 8.0 12.0 Q1
TSV912AIDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TSV912AIDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TSV912AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TSV912AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TSV914AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TSV914AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TSV914AIPWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Apr-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSV911AIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TSV911AIDCKR SC70 DCK 5 3000 190.0 190.0 30.0
TSV912AIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
TSV912AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TSV912AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
TSV912AIDR SOIC D 8 2500 333.2 345.9 28.6
TSV912AIDSGR WSON DSG 8 3000 210.0 185.0 35.0
TSV912AIDSGT WSON DSG 8 250 210.0 185.0 35.0
TSV912AIPWR TSSOP PW 8 2000 853.0 449.0 35.0
TSV912AIPWR TSSOP PW 8 2000 366.0 364.0 50.0
TSV914AIDR SOIC D 14 2500 853.0 449.0 35.0
TSV914AIPWR TSSOP PW 14 2000 366.0 364.0 50.0
TSV914AIPWT TSSOP PW 14 250 366.0 364.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Apr-2022
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WSON - 0.8 mm max heightDSG 8
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
4224783/A
,Cl, LII, 7|:|
www.ti.com
PACKAGE OUTLINE
C
8X 0.32
0.18
1.6 0.1
2X
1.5
0.9 0.1
6X 0.5
8X 0.4
0.2
0.05
0.00
0.8 MAX
A2.1
1.9 B
2.1
1.9
0.32
0.18
0.4
0.2
(0.2) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
ALTERNATIVE TERMINAL SHAPE
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.25)
(1.6)
(1.9)
6X (0.5)
(0.9) ( 0.2) VIA
TYP
(0.55)
8X (0.5)
(R0.05) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.25)
8X (0.5)
(0.9)
(0.7)
(1.9)
(0.45)
6X (0.5)
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
45
8
METAL
SYMM 9
PW0008A '
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
PW0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PW0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
DDF0008A / —— \ JI- \ /~x
www.ti.com
PACKAGE OUTLINE
C
TYP
2.95
2.65
1.1 MAX
6X 0.65
8X 0.4
0.2
2X
1.95
TYP
0.20
0.08
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.3
A
NOTE 3
2.95
2.85
B1.65
1.55
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 4.000
DDF0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(2.6)
8X (1.05)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
1
45
8
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DDF0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
6X (0.65)
8X (0.45)
8X (1.05)
(R ) TYP0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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