Datenblatt für SN54LVC74A, SN74LVC74A von Texas Instruments

V'.‘ 1!. I TEXAS INSTRUMENTS X E CLR 070
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
1
1 Features
1• Operate From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Maximum tpd of 5.2 ns at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA= 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA= 25°C
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• Servers
• Medical, Healthcare, and Fitness
• Telecom Infrastructures
• TVs, Set-Top Boxes, and Audio
• Test and Measurement
• Industrial Transport
• Wireless Infrastructure
• Enterprise Switching
• Motor Drives
• Factory Automation and Control
3 Description
The SNx4LVC74A devices integrate two positive-
edge triggered D-type flip-flops in one convenient
device.
The SN54LVC74A is designed for 2.7-V to 3.6-V VCC
operation, and the SN74LVC74A is designed for
1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
The data I/Os and control inputs are overvoltage
tolerant. This feature allows the use of these devices
for down-translation in a mixed-voltage environment.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SNJ54LVC74AFK LCCC (20) 8.89 mm × 8.89 mm
SNJ54LVC74AJ CDIP (14) 19.56 mm × 6.67 mm
SNJ54LVC74AW CFP (14) 9.21 mm × 5.97 mm
SN74LVC74AD SOIC (14) 8.65 mm × 3.91 mm
SN74LVC74ADB SSOP (14) 6.20 mm × 5.30 mm
SN74LVC74ANS SO (14) 10.30 mm × 5.30 mm
SN74LVC74APW TSSOP (14) 5.00 mm × 4.40 mm
SN74LVC74ARGY VQFN (14) 3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Flip-Flop (Positive Logic)
l TEXAS INSTRUMENTS
2
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
www.ti.com
Product Folder Links: SN54LVC74A SN74LVC74A
Submit Documentation Feedback Copyright © 1993–2017, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: SN74LVC74A ......................... 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements: SN54LVC74A ....................... 6
6.7 Timing Requirements: SN74LVC74A ....................... 6
6.8 Timing Requirements: SN74LVC74A, –40°C to
125°C and –40°C to 85°C.......................................... 7
6.9 Switching Characteristics: SN54LVC74A ................. 7
6.10 Switching Characteristics: SN74LVC74A ............... 7
6.11 Switching Characteristics: SN74LVC74A, –40°C to
125°C and –40°C to 85°C.......................................... 8
6.12 Operating Characteristics........................................ 8
6.13 Typical Characteristics............................................ 8
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1 Documentation Support ........................................ 14
12.2 Related Links ........................................................ 14
12.3 Receiving Notification of Documentation Updates 14
12.4 Community Resource............................................ 14
12.5 Trademarks........................................................... 14
12.6 Electrostatic Discharge Caution............................ 14
12.7 Glossary................................................................ 14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision T (July 2013) to Revision U Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed Package thermal impedance, RθJA, values in Thermal Information: SN74LVC74A From: 86 To: 93.7 (D),
From: 96 To: 107.3 (DB), From: 76 To: 90.3 (NS), From: 113 To: 121.7 (PW), and From: 47 To: 54.9 (RGY).................... 5
Changes from Revision S (May 2005) to Revision T Page
• Extended maximum temperature operating range from 85°C to 125°C................................................................................. 4
l TEXAS INSTRUMENTS A No| |o some
41CLK
5NC
61PRE
7NC
81Q
91Q
10GND
11NC
122Q
132Q
14 2PRE
15 NC
16 2CLK
17 NC
18 2D
19 2CLR
20 VCC
1 NC
2 1CLR
3 1D
Not to scale
1 14
7 8
2
3
4
5
6
13
12
11
10
9
2CLR
2D
2CLK
2PRE
2Q
1D
1CLK
1PRE
1Q
1Q
1CLR
2Q V
GND
CC
11CLR 14 VCC
21D 13 2CLR
31CLK 12 2D
41PRE 11 2CLK
51Q 10 2PRE
61Q 9 2Q
7GND 8 2Q
Not to scale
3
SN54LVC74A
,
SN74LVC74A
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5 Pin Configuration and Functions
D, DB, J, PW, NS, or W Package
14-Pin SOIC, SSOP, CDIP, TSSOP, SO, or CFP
Top View
RGY Package
14-Pin VQFN With Exposed Thermal Pad
Top View
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME CDIP, CFP, PDIP, SO, SOIC,
SSOP, TSSOP, VQFN LCCC
1CLK 3 4 I Channel 1 clock input
1CLR 1 2 I Channel 1 clear input. Pull low to set Q output low.
1D 2 3 I Channel 1 data input
1PRE 4 6 I Channel 1 preset input. Pull low to set Q output high.
1Q 5 8 O Channel 1 output
1Q 6 9 O Channel 1 inverted output
2CLK 11 16 I Channel 2 clock input
2CLR 13 19 I Channel 2 clear input. Pull low to set Q output low.
2D 12 18 I Channel 2 data input
2PRE 10 14 I Channel 2 preset input. Pull low to set Q output high.
2Q 9 13 O Channel 2 output
2Q 8 12 O Channel 2 Inverted output
GND 7 10 — Ground
NC — 1, 5, 7, 11, 15, 17 — No connect
VCC 14 20 — Supply
l TEXAS INSTRUMENTS
4
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in Recommended Operating Conditions.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC –0.5 6.5 V
Input voltage, VI(2) –0.5 6.5 V
Output voltage, VO(2)(3) –0.5 VCC + 0.5 V
Input clamp current, IIK VI< 0 –50 mA
Output clamp current, IOK VO< 0 –50 mA
Continuous output current, IO±50 mA
Continuous current through VCC or GND ±100 mA
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.3 Recommended Operating Conditions
see(1)
MIN MAX UNIT
VCC Supply voltage Operating SN54LVC74A 2 3.6
VSN74LVC74A 1.65 3.6
Data retention only 1.5
VIH High-level input voltage
VCC = 1.65 V to 1.95 V SN74LVC74A 0.65 × VCC
VVCC = 2.3 V to 2.7 V SN74LVC74A 1.7
VCC = 2.7 V to 3.6 V 2
VIL Low-level input voltage
VCC = 1.65 V to 1.95 V SN74LVC74A 0.35 × VCC
VVCC = 2.3 V to 2.7 V SN74LVC74A 0.7
VCC = 2.7 V to 3.6 V 0.8
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
IOH High-level output current
VCC = 1.65 V SN74LVC74A –4
mA
VCC = 2.3 V SN74LVC74A –8
VCC = 2.7 V –12
VCC = 3 V –24
IOL Low-level output current
VCC = 1.65 V SN74LVC74A 4
mA
VCC = 2.3 V SN74LVC74A 8
VCC = 2.7 V 12
VCC = 3 V 24
Δt/Δv Input transition rise or fall rate 10 ns/V
l TEXAS INSTRUMENTS
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,
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Recommended Operating Conditions (continued)
see(1)
MIN MAX UNIT
TAOperating free-air temperature SN54LVC74A –55 125 °C
SN74LVC74A –40 125
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information: SN74LVC74A
THERMAL METRIC(1)
SN74LVC74A
UNIT
D
(SOIC) DB
(SSOP) NS
(SO) PW
(TSSOP) RGY
(VQFN)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.7 107.3 90.3 121.7 54.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.8 59.2 48.1 50.3 52.2 °C/W
RθJB Junction-to-board thermal resistance 48 54.6 49.1 63.4 30.8 °C/W
ψJT Junction-to-top characterization parameter 20.3 24.1 17.9 6.2 2.4 °C/W
ψJB Junction-to-board characterization parameter 47.7 54.1 48.8 62.8 30.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — 12.5 °C/W
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage
IOH = –100 µA
VCC = 1.65 V to 3.6 V and TA= –55°C to
125°C (SN54LVC74A only) VCC – 0.2
V
VCC = 2.7 V to 3.6 V and TA= –40°C to
125°C (SN74LVC74A only) VCC – 0.2
IOH = –4 mA, VCC = 1.65 V, and TA= –40°C to 125°C
(SN74LVC74A only) 1.2
IOH = –8 mA, VCC = 2.3 V, and TA= –40°C to 125°C
(SN74LVC74A only) 1.7
IOH = –12 mA VCC = 2.7 V 2.2
VCC = 3 V 2.4
IOH = –24 mA, VCC = 3 V 2.2
VOL Low-level output voltage
IOL = 100 µA
VCC = 1.65 V to 3.6 V, and TA= –40°C
to 125°C (SN74LVC74A only) 0.2
V
VCC = 2.7 V to 3.6 V and TA= –55°C to
125°C (SN54LVC74A only) 0.2
IOL = 4 mA, VCC = 1.65 V, and TA= –40°C to 125°C
(SN74LVC74A only) 0.45
IOL = 8 mA, VCC = 2.3 V, and TA= –40°C to 125°C
(SN74LVC74A only) 0.7
IOL = 12 mA, VCC = 2.7 V 0.4
IOL = 24 mA, VCC = 3 V 0.55
IIInput current VI= 5.5 V or GND, VCC = 3.6 V ±5 µA
ICC Supply current VI= VCC or GND, IO= 0, VCC = 3.6 V 10 µA
ΔICC Change in supply current One input at VCC – 0.6 V, other inputs at VCC or GND, and
VCC = 2.7 V to 3.6 V 500 µA
CiInput capacitance VI= VCC or GND, VCC = 3.3 V, TA= 25°C 5 pF
l TEXAS INSTRUMENTS
6
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
www.ti.com
Product Folder Links: SN54LVC74A SN74LVC74A
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6.6 Timing Requirements: SN54LVC74A
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
MIN MAX UNIT
fclock Clock frequency VCC = 2.7 V 83 MHz
VCC = 3.3 V ± 0.3 V 100
twPulse duration PRE or CLR low 3.3 ns
CLK high or low 3.3
tsu Setup time before CLK↑
Data VCC = 2.7 V 3.4
ns
VCC = 3.3 V ± 0.3 V 3
PRE or CLR inactive VCC = 2.7 V 2.2
VCC = 3.3 V ± 0.3 V 2
thHold time, data after CLK↑1 ns
6.7 Timing Requirements: SN74LVC74A
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
MIN MAX UNIT
fclock Clock frequency VCC = 1.8 V or 2.5 V 83 MHz
twPulse duration
PRE or CLR low VCC = 1.8 V ± 0.15 V 4.1
ns
VCC = 2.5 V ± 0.2 V 3.3
CLK high or low VCC = 1.8 V ± 0.15 V 4.1
VCC = 2.5 V ± 0.2 V 3.3
tsu Setup time before CLK↑
Data VCC = 1.8 V ± 0.15 V 3.6
ns
VCC = 2.5 V ± 0.2 V 2.3
PRE or CLR inactive VCC = 1.8 V ± 0.15 V 2.7
VCC = 2.5 V ± 0.2 V 1.9
thHold time, data after CLK↑VCC = 1.8 V or 2.5 V 1 ns
l TEXAS INSTRUMENTS
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,
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6.8 Timing Requirements: SN74LVC74A, –40°C to 125°C and –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
MIN MAX UNIT
fclock Clock frequency
TA= –40°C to
125°C
VCC = 2.7 V 83
MHzVCC = 3.3 V ± 0.3 V 100
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 150
twPulse duration PRE or CLR low VCC = 2.7 V or 3.3 V 3.3 ns
CLK high or low VCC = 2.7 V or 3.3 V 3.3
tsu Setup time before CLK↑
Data TA= –40°C to 125°C VCC = 2.7 V 3.4
ns
VCC = 3.3 V ± 0.3 V 3
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 3
PRE or CLR
inactive
TA= –40°C to 125°C VCC = 2.7 V 2.2
VCC = 3.3 V ± 0.3 V 2
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 2
thHold time, data after
CLK↑VCC = 2.7 V or 3.3 V 1 ns
6.9 Switching Characteristics: SN54LVC74A
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN MAX UNIT
fmax Maximum clock
frequency — — VCC = 2.7 V 83 MHz
VCC = 3.3 V ± 0.3 V 100
tpd Propagation (delay)
time
CLK
Q or Q
VCC = 2.7 V 6
ns
VCC = 2.7 V 1 5.2
PRE or CLR VCC = 3.3 V ± 0.3 V 6.4
VCC = 3.3 V ± 0.3 V 1 5.4
6.10 Switching Characteristics: SN74LVC74A
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN MAX UNIT
fmax Maximum clock
frequency — — 83 MHz
tpd Propagation (delay)
time
CLKPRE
Q or Q
VCC = 1.8 V ± 0.15 V 1 7.1
ns
VCC = 2.5 V ± 0.2 V 1 4.4
or CLR VCC = 1.8 V ± 0.15 V 1 6.9
VCC = 2.5 V ± 0.2 V 1 4.6
‘5‘ TEXAS INSTRUMENTS 1a m: w 2:; 33 5.332; \ . 14 m: ‘ 2:: 53 5:32;: ‘ .
2
4
6
8
10
0 50 100 150 200 250 300
CL– Load Capacitance – pF
t – Propagation Delay Time – ns
pd
VCC = 3 V,
TA= 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
SN54LVC74A
,
SN74LVC74A
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6.11 Switching Characteristics: SN74LVC74A, –40°C to 125°C and –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted; see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN MAX UNIT
fmax Maximum clock
frequency — — TA= –40°C to 125°C VCC = 2.7 V 83
MHzVCC = 3.3 V ± 0.3 V 100
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 150
tpd Propagation (delay)
time
CLK
Q or Q
TA= –40°C to 125°C VCC = 2.7 V 1 6
ns
VCC = 3.3 V ± 0.3 V 5.2
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 1 5.2
PRE or CLR TA= –40°C to 125°C VCC = 2.7 V 1 6.4
VCC = 3.3 V ± 0.3 V 5.4
TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 1 5.4
tsk(o) Skew (time), output — — TA= –40°C to 85°C and VCC = 3.3 V ± 0.3 V 1 ns
6.12 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop f = 10 MHz
VCC = 1.8 V 24
pFVCC = 2.5 V 24
VCC = 3.3 V 26
6.13 Typical Characteristics
Figure 1. Propagation Delay (Low-to-High Transition)
vs Load Capacitance Figure 2. Figure 2. Propagation Delay (High-to-Low
Transition) vs Load Capacitance
l TEXAS INSTRUMENTS O V SI 0 hi 4H INVERTING AND NDNINVERTING OUTPUTS Low-AND HIGH-LEVEL ENABLING
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + VΔ
VOH V– Δ
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
2.7 V
3.3 V ±0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2×VCC
2×VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
VΔ
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
9
SN54LVC74A
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7 Parameter Measurement Information
A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS C C A; \ D TG TG \ T C C 0‘0 TG
Copyright © 2016, Texas Instruments Incorporated
10
SN54LVC74A
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8 Detailed Description
8.1 Overview
The SNx4LVC74A devices feature two independent positive-edge triggered D flip-flops. Integrated preset (PRE)
and clear (CLR) functions allow for easy setup and control during operation.
The SN54LVC74A device is specified from –55°C to 125°C, and the SN74LVC74A device is specified from
–40°C to 125°C.
8.2 Functional Block Diagram
8.3 Feature Description
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
8.4 Device Functional Modes
Table 1 describes the SNx4LVC74A functionality and interactions between the PRE, CLR, CLK, and D inputs.
(1) This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
Table 1. Function Table
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H(1) H(1)
H H ↑H H L
H H ↑L L H
H H L X Q0Q0
l TEXAS INSTRUMENTS Copyngm cc> 201619an \nskumems \ncorporated
SN74LVC74A
Clock Input
VCC
1CLK
Q
GND
Q
1D
3 V
Output
Copyright © 2016, Texas Instruments Incorporated
11
SN54LVC74A
,
SN74LVC74A
www.ti.com
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
Product Folder Links: SN54LVC74A SN74LVC74A
Submit Documentation FeedbackCopyright © 1993–2017, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A common application for the SN74LVC74A is a frequency divider. By connecting the Q output to the D input, the
Q output toggles states on each positive edge of the incoming clock signal. Because it takes two positive edges,
or two clock pulses, to complete one complete pulse on the output (one pulse to toggle from low to high, another
to toggle from high to low), the incoming clock frequency is effectively divided by two.
9.2 Typical Application
Figure 4. Frequency Divider
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive also creates fast edges into light loads, so consider routing
and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specification, see (Δt/ΔV) in Recommended Operating Conditions.
– For specified high and low levels, see (VIH and VIL)inRecommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as (VImax) in Recommended Operating
Conditions at any valid VCC.
2. Recommended maximum output conditions:
– Load currents must not exceed (IOmax) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs must not be pulled above VCC.
l TEXAS INSTRUMENTS —mA 100 VoH
–100
–80
–60
–40
–20
0
20
40
60
–1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TA= 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
VOH – V
IOH – mA
VOL – V
–20
0
20
40
60
80
100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
TA= 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
IOL – mA
12
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
www.ti.com
Product Folder Links: SN54LVC74A SN74LVC74A
Submit Documentation Feedback Copyright © 1993–2017, Texas Instruments Incorporated
Typical Application (continued)
9.2.3 Application Curves
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
l TEXAS INSTRUMENTS
VCC
Unused Input
Input
Output Output
Input
Unused Input
13
SN54LVC74A
,
SN74LVC74A
www.ti.com
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
Product Folder Links: SN54LVC74A SN74LVC74A
Submit Documentation FeedbackCopyright © 1993–2017, Texas Instruments Incorporated
10 Power Supply Recommendations
The power supply may be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-µF or 0.022-µF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
Inputs must not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or
VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
Figure 7. Layout Diagram
l TEXAS INSTRUMENTS
14
SN54LVC74A
,
SN74LVC74A
SCAS287U –JANUARY 1993–REVISED JANUARY 2017
www.ti.com
Product Folder Links: SN54LVC74A SN74LVC74A
Submit Documentation Feedback Copyright © 1993–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
SN54LVC74A Click here Click here Click here Click here Click here
SN74LVC74A Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9761601Q2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
9761601Q2A
SNJ54LVC
74AFK
Samples
5962-9761601QCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9761601QC
A
SNJ54LVC74AJ
Samples
5962-9761601QDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9761601QD
A
SNJ54LVC74AW
Samples
5962-9761601VDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9761601VD
A
SNV54LVC74AW
Samples
SN74LVC74AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A Samples
SN74LVC74ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A Samples
SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A Samples
SN74LVC74ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A Samples
SN74LVC74ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A Samples
SN74LVC74APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
Addendum-Page 1
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A Samples
SN74LVC74ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC74A Samples
SNJ54LVC74AFK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
9761601Q2A
SNJ54LVC
74AFK
Samples
SNJ54LVC74AJ ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9761601QC
A
SNJ54LVC74AJ
Samples
SNJ54LVC74AW ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9761601QD
A
SNJ54LVC74AW
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A :
•Catalog : SN74LVC74A, SN54LVC74A
•Automotive : SN74LVC74A-Q1, SN74LVC74A-Q1
•Enhanced Product : SN74LVC74A-EP, SN74LVC74A-EP
•Military : SN54LVC74A
•Space : SN54LVC74A-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC74ADBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LVC74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC74ADBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LVC74ADR SOIC D 14 2500 356.0 356.0 35.0
SN74LVC74ADT SOIC D 14 250 210.0 185.0 35.0
SN74LVC74ANSR SO NS 14 2000 356.0 356.0 35.0
SN74LVC74APWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC74APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC74APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC74APWT TSSOP PW 14 250 356.0 356.0 35.0
SN74LVC74ARGYR VQFN RGY 14 3000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9761601Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9761601VDA W CFP 14 1 506.98 26.16 6220 NA
SN74LVC74AD D SOIC 14 50 506.6 8 3940 4.32
SN74LVC74APW PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC74APWG4 PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54LVC74AFK FK LCCC 20 1 506.98 12.06 2030 NA
Pack Materials-Page 3
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THERMAL PAD MECHANICAL DATA RGY (87PVQFN7N14) PLASTlC QUAD FLATPACK NOiLEAD THERMAL lNFORMATlON This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical Schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB, This design optimizes the heat transfer from the integrated circuit (IC). For iniormatlon on the Quad Flatpack No—Lead (QFN) package and its advantages. reier to Application Report. OFN/SON PCB Attachment. Texas instruments Literature No. SLUA271. This document is available at wwwti‘cam, The exposed thermal pad dimensions for this package are shown in the following illustration. —Exposed Thermal Pad UUU s U T 13 ‘t/C7 2,05i0,i0 -l- l i4 U Q i3 9 2,05i0,i0 Bottom View Exposed Thermal Pad Dimensions 4206353—2/P 03/14 NOTE: All linear dimensions are in millimeters ”I. "-216 ‘5 INSTRUMENTS www.li.com
LAND PATTERN DATA PLASTIC QUAD FLATPACK NO—LEAD RGY (s—PVQFN—Ni 4) Example Stencil Design 0‘125mm stencil ihichness Example Eaard Lawut (Note E) <—4,3o—» us="" h="" u="" u="" u="" note="" d="" h="" u="" u="" u="" l="" —d="" (:l="" 7:2,.="" «f="" t:l="" £50="" ledf="" 2.05’="" "25="" 7551—="" 82="" t="" 1,50="" 7="" 7="" use="" _="" _="" 1:)="" z'i="" ~;l="" l:)="" -°—l="" 7="" ‘-="" 0.50="" x="" h="" pl="" non="" solder="" mask="" .e="" du="" 4="" e="" 54%="" solder="" coverage="" by="" printed="" area="" on="" center="" thermal="" pad="" example="" ma="" layout="" design="" may="" vary="" depending="" on="" constraints="" defined="" pad="" ..’="" .....="" example="" \="" (note="" a.="" f)="" l="" ‘\="" solder="" mask="" opening="" w,="" (note="" f)="" o="" l="" ,="" +="" 4397="" l‘="" '="" “="" o="" l="" \l\="" example="" 6x¢0,3="" ‘.\="" 7="" pad="" geometry="" .‘="" 0'07="" (note="" c)="" all="" around="" \\="" ‘\="" \_\="">. Customers should Laser cutting apertures with trapezoidal walls and also rounding carriers will orler better paste release. Reler to we 7525 tor stencil design considerations. contact their board ossemoly site tar stencil design recommendations, Customers should contact their board fabrication site for minimum solder mask wea tolerances between signal pods. TEXAS INSTRUMENTS www.ti.com til!
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
GENERIC PACKAGE VIEW J 14 CDIP - 5.08 mm max heigm CERAMIC DUAL IN LINE PACKAGE [I l l 'I I.“ Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the produd dala sheel for package details. 4040053756 I TEXAS INSTRI IMFNTS
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
fi©©©©©©© ““w“‘¢‘w‘w““‘ ,w@@@@@@ A RLr
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
oo A‘ioyi 55 fiHHHHHHHHHHHHfi {'3 TEXAS INSTRUMENTS
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA W (R—GDFP—F14) CERAM‘C DUAL FLATPACK Ease and Seating Wane 0.250 (6.60) 00‘5 (W) 0235 (5.97) f 0. 026 (0 as) ‘ ‘ 0.005 0.20 _ 00 2.03) 0.004 (0.10) 0,045 1.14 47 0,280 (7.11) MAX 4» 0.019 0.48 1 H i 0.015 50.35; :3 I: T I: :1 :I I: 0.050 (1.27) (:3 ::I 0.390 (9 91) 7' I: :1 0.335 (0.51) :l I: 1:3 ::1 1:3 ::1 “-005 (0-13) “‘N 4 Manes 1:3 I: i 7 E f 0.560 (9.11) 0.360 (0.14) 0.250 (0.35) 0,250 (6.35) 404013072/r 01/11 NOTES: A. AH Hnear dimensions are in inches (m1111meters). B. This dram’ng 1: 5mm \0 change mm nofice. c, This package can be hermeticany sea1ed mm 0 ceramic lid usmg glass iriL 0, \ndex paint '15 pmw'ded an cap for terminm idenmcutiun omy. E. Faus within M1L STD 1835 GDFPW’FH i TEXAS INSTRUMENTS www.mmm
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